arch, cpu: Do not forward snoops to table walker

This patch simplifies the overall CPU by changing the TLB caches such
that they do not forward snoops to the table walker port(s). Note that
only ARM and X86 are affected.

There is no reason for the ports to snoop as they do not actually take
any action, and from a performance point of view we are better of not
snooping more than we have to.

Should it at a later point be required to snoop for a particular TLB
design it is easy enough to add it back.

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 9f7ac7a85654e36bbb18c8764f15d83e59248c26..6687a967c8188aa30588db5bcf0732a850289afa 100644 (file)
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -79,4 +79,5 @@ class PageTableWalkerCache(BaseCache):
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
+    forward_snoops = False
     is_top_level = True

diff --git a/configs/common/O3_ARM_v7a.py b/configs/common/O3_ARM_v7a.py
index 1bb2b4a5e3bb5b789b0ae72084e45dead9108df7..c291525eab6eb3446cccab943171c1b76453e3e8 100644 (file)
--- a/configs/common/O3_ARM_v7a.py
+++ b/configs/common/O3_ARM_v7a.py
@@ -174,7 +174,7 @@ class O3_ARM_v7aWalkCache(BaseCache):
     assoc = 8
     write_buffers = 16
     is_top_level = True
-
+    forward_snoops = False
 
 # L2 Cache
 class O3_ARM_v7aL2(BaseCache):

diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index 41a10e62328b41376c508e21b50c939a53233de1..132d1b7f51bb35b3ce4b85af9ab74416bf91b68f 100755 (executable)
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -57,40 +57,8 @@ class Stage2MMU : public SimObject
 
   protected:
 
-    /**
-     * A snooping DMA port that currently does nothing besides
-     * extending the DMA port to accept snoops without
-     * complaining. Currently we take no action on any snoops.
-     */
-    class SnoopingDmaPort : public DmaPort
-    {
-
-      protected:
-
-        virtual void recvTimingSnoopReq(PacketPtr pkt)
-        { }
-
-        virtual Tick recvAtomicSnoop(PacketPtr pkt)
-        { return 0; }
-
-        virtual void recvFunctionalSnoop(PacketPtr pkt)
-        { }
-
-        virtual bool isSnooping() const { return true; }
-
-      public:
-
-        /**
-         * A snooping DMA port merely calls the construtor of the DMA
-         * port.
-         */
-        SnoopingDmaPort(MemObject *dev, System *s) :
-            DmaPort(dev, s)
-        { }
-    };
-
     /** Port to issue translation requests from */
-    SnoopingDmaPort port;
+    DmaPort port;
 
     /** Request id for requests generated by this MMU */
     MasterID masterId;

diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh
index 181d6fb6c8f3f6cf6546f85544488bc7ab735ea4..9be35e6ccd0b1f45c3ef6f4d64dfb81bd60cc505 100644 (file)
--- a/src/arch/x86/pagetable_walker.hh
+++ b/src/arch/x86/pagetable_walker.hh
@@ -70,15 +70,7 @@ namespace X86ISA
             Walker *walker;
 
             bool recvTimingResp(PacketPtr pkt);
-
-            /**
-             * Snooping a coherence request, do nothing.
-             */
-            void recvTimingSnoopReq(PacketPtr pkt) { }
-            Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
-            void recvFunctionalSnoop(PacketPtr pkt) { }
             void recvReqRetry();
-            bool isSnooping() const { return true; }
         };
 
         friend class WalkerPort;