ARM: Add a base class for extend and add instructions.

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index f8106c33a55c276acdf1ca978793c7dd1b8dd91d..c5430400d6417d615f4a98ca5265ff8b5809a65c 100644 (file)
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -154,6 +154,20 @@ RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     return ss.str();
 }
 
+std::string
+RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    printMnemonic(ss);
+    printReg(ss, dest);
+    ss << ", ";
+    printReg(ss, op1);
+    ss << ", ";
+    printReg(ss, op2);
+    ccprintf(ss, ", #%d", imm);
+    return ss.str();
+}
+
 std::string
 RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {

diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index fed2e2479fa78e1d3061ddcbfd34252ffa73c5cc..d990070fba9f5728f21d372510864aa87419eeb1 100644 (file)
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -124,6 +124,24 @@ class RegImmRegOp : public PredOp
     std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 };
 
+class RegRegRegImmOp : public PredOp
+{
+  protected:
+    IntRegIndex dest;
+    IntRegIndex op1;
+    IntRegIndex op2;
+    uint32_t imm;
+
+    RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
+                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+                   uint32_t _imm) :
+        PredOp(mnem, _machInst, __opClass),
+        dest(_dest), op1(_op1), op2(_op2), imm(_imm)
+    {}
+
+    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
 class RegImmRegShiftOp : public PredOp
 {
   protected:

diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index ec660c5a1a06e0216b865a4a556ca1948dcdd274..3b4c6a6f8f85c626bfe082318a1b095f991cf996 100644 (file)
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -120,6 +120,32 @@ def template RevOpConstructor {{
     }
 }};
 
+def template RegRegRegImmOpDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  protected:
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst,
+                       IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+                       uint32_t _imm);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template RegRegRegImmOpConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _dest,
+                                          IntRegIndex _op1,
+                                          IntRegIndex _op2,
+                                          uint32_t _imm)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                         _dest, _op1, _op2, _imm)
+    {
+        %(constructor)s;
+    }
+}};
+
 def template RegImmRegOpDeclare {{
 class %(class_name)s : public %(base_class)s
 {