case PKT3_PFP_SYNC_ME:
break;
case PKT3_NOP:
- if (header == 0xffff1000) {
+ if (header == PKT3_NOP_PAD) {
count = -1; /* One dword NOP. */
} else if (count == 0 && ib->cur_dw < ib->num_dw &&
AC_IS_TRACE_POINT(ib->ib[ib->cur_dw])) {
#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
+#define PKT2_NOP_PAD PKT_TYPE_S(2)
+#define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */
+
#define PKT3_CP_DMA 0x41
/* 1. header
* 2. SRC_ADDR_LO [31:0] or DATA [31:0]
while (cs->cdw & 7) {
if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
- radeon_emit(cs, 0x80000000);
+ radeon_emit(cs, PKT2_NOP_PAD);
else
- radeon_emit(cs, 0xffff1000);
+ radeon_emit(cs, PKT3_NOP_PAD);
}
device->gfx_init = device->ws->buffer_create(device->ws,
ib_size = MIN2(ib_size, 0xfffff);
while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
- radeon_emit(&cs->base, 0xffff1000);
+ radeon_emit(&cs->base, PKT3_NOP_PAD);
*cs->ib_size_ptr |= cs->base.cdw + 4;
if (cs->ws->use_ib_bos) {
while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
- radeon_emit(&cs->base, 0xffff1000);
+ radeon_emit(&cs->base, PKT3_NOP_PAD);
*cs->ib_size_ptr |= cs->base.cdw;
struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
uint32_t bo_list;
struct radv_amdgpu_cs_request request;
- uint32_t pad_word = 0xffff1000U;
+ uint32_t pad_word = PKT3_NOP_PAD;
bool emit_signal_sem = sem_info->cs_emit_signal;
if (radv_amdgpu_winsys(ws)->info.chip_class == GFX6)
/* Pad with NOPs and add INDIRECT_BUFFER packet */
while ((rcs->current.cdw & 7) != 4)
- radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
+ radeon_emit(rcs, PKT3_NOP_PAD);
radeon_emit(rcs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
radeon_emit(rcs, va);
/* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
if (ws->info.gfx_ib_pad_with_type2) {
while (rcs->current.cdw & 7)
- radeon_emit(rcs, 0x80000000); /* type2 nop packet */
+ radeon_emit(rcs, PKT2_NOP_PAD);
} else {
while (rcs->current.cdw & 7)
- radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
+ radeon_emit(rcs, PKT3_NOP_PAD);
}
if (cs->ring_type == RING_GFX)
ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
/* Also pad secondary IBs. */
if (cs->compute_ib.ib_mapped) {
while (cs->compute_ib.base.current.cdw & 7)
- radeon_emit(&cs->compute_ib.base, 0xffff1000); /* type3 nop packet */
+ radeon_emit(&cs->compute_ib.base, PKT3_NOP_PAD);
}
break;
case RING_UVD: