amd: add proper definitions for NOP packets
authorMarek Olšák <marek.olsak@amd.com>
Thu, 18 Jun 2020 05:04:51 +0000 (01:04 -0400)
committerMarge Bot <eric+marge@anholt.net>
Fri, 26 Jun 2020 07:02:57 +0000 (07:02 +0000)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>

src/amd/common/ac_debug.c
src/amd/common/sid.h
src/amd/vulkan/si_cmd_buffer.c
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

index 77c0e0aa790cd13046d8d7e23ae0ebed06941cce..b81897811a143ac374548ab4e1ea166ba719e2f3 100644 (file)
@@ -441,7 +441,7 @@ static void ac_parse_packet3(FILE *f, uint32_t header, struct ac_ib_parser *ib,
        case PKT3_PFP_SYNC_ME:
                break;
        case PKT3_NOP:
-               if (header == 0xffff1000) {
+               if (header == PKT3_NOP_PAD) {
                        count = -1; /* One dword NOP. */
                } else if (count == 0 && ib->cur_dw < ib->num_dw &&
                           AC_IS_TRACE_POINT(ib->ib[ib->cur_dw])) {
index d77d2ff57509a39633e5f9d513eda3bdc73cdbd3..fef3e14d5e2b2742ee78e09b64f8d49173a99c4b 100644 (file)
 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 
+#define PKT2_NOP_PAD                    PKT_TYPE_S(2)
+#define PKT3_NOP_PAD                    PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */
+
 #define PKT3_CP_DMA                                    0x41
 /* 1. header
  * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
index d53aaf331442630ec6f8b7eee100e4a4123d4191..e6a3bcd45a2449230cc46da4e59c8b01f3059346 100644 (file)
@@ -520,9 +520,9 @@ cik_create_gfx_config(struct radv_device *device)
 
        while (cs->cdw & 7) {
                if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
-                       radeon_emit(cs, 0x80000000);
+                       radeon_emit(cs, PKT2_NOP_PAD);
                else
-                       radeon_emit(cs, 0xffff1000);
+                       radeon_emit(cs, PKT3_NOP_PAD);
        }
 
        device->gfx_init = device->ws->buffer_create(device->ws,
index 65b6bb4187d423706ab6bc70deed0e096134eed6..7f391a60a7263b07ff15c1354a9c9d921a4de809 100644 (file)
@@ -424,7 +424,7 @@ static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
        ib_size = MIN2(ib_size, 0xfffff);
 
        while (!cs->base.cdw || (cs->base.cdw & 7) != 4)
-               radeon_emit(&cs->base, 0xffff1000);
+               radeon_emit(&cs->base, PKT3_NOP_PAD);
 
        *cs->ib_size_ptr |= cs->base.cdw + 4;
 
@@ -480,7 +480,7 @@ static VkResult radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
 
        if (cs->ws->use_ib_bos) {
                while (!cs->base.cdw || (cs->base.cdw & 7) != 0)
-                       radeon_emit(&cs->base, 0xffff1000);
+                       radeon_emit(&cs->base, PKT3_NOP_PAD);
 
                *cs->ib_size_ptr |= cs->base.cdw;
 
@@ -1042,7 +1042,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
        struct radeon_winsys *ws = (struct radeon_winsys*)cs0->ws;
        uint32_t bo_list;
        struct radv_amdgpu_cs_request request;
-       uint32_t pad_word = 0xffff1000U;
+       uint32_t pad_word = PKT3_NOP_PAD;
        bool emit_signal_sem = sem_info->cs_emit_signal;
 
        if (radv_amdgpu_winsys(ws)->info.chip_class == GFX6)
index a8e7ed0f21b1ae5e84c50ff5ef71348f5a66a341..80eb0f6b7f0c6f744f08a5c17392b6dc7328c447 100644 (file)
@@ -1099,7 +1099,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
 
    /* Pad with NOPs and add INDIRECT_BUFFER packet */
    while ((rcs->current.cdw & 7) != 4)
-      radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
+      radeon_emit(rcs, PKT3_NOP_PAD);
 
    radeon_emit(rcs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
    radeon_emit(rcs, va);
@@ -1680,10 +1680,10 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
       /* pad GFX ring to 8 DWs to meet CP fetch alignment requirements */
       if (ws->info.gfx_ib_pad_with_type2) {
          while (rcs->current.cdw & 7)
-            radeon_emit(rcs, 0x80000000); /* type2 nop packet */
+            radeon_emit(rcs, PKT2_NOP_PAD);
       } else {
          while (rcs->current.cdw & 7)
-            radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
+            radeon_emit(rcs, PKT3_NOP_PAD);
       }
       if (cs->ring_type == RING_GFX)
          ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
@@ -1691,7 +1691,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
       /* Also pad secondary IBs. */
       if (cs->compute_ib.ib_mapped) {
          while (cs->compute_ib.base.current.cdw & 7)
-            radeon_emit(&cs->compute_ib.base, 0xffff1000); /* type3 nop packet */
+            radeon_emit(&cs->compute_ib.base, PKT3_NOP_PAD);
       }
       break;
    case RING_UVD: