struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
LLVMBuilderRef builder = bld_base->base.gallivm->builder;
- LLVMValueRef result, ptr;
+ LLVMValueRef result = NULL, ptr;
if (swizzle == ~0) {
LLVMValueRef values[TGSI_NUM_CHANNELS];
break;
case TGSI_FILE_TEMPORARY:
- if (uses_temp_indirect_addressing(bld_base))
+ if (uses_temp_indirect_addressing(bld_base)) {
+ temp_ptr = NULL;
break;
+ }
temp_ptr = ctx->temps[ TGSI_NUM_CHANNELS * reg->Register.Index + chan_index];
break;
for (j = 0; j < ndw; j++) {
if (j && !(j % 8)) {
uint32_t offset = (j - 8) << 2;
- fprintf(dump, " /* [0x%08x] va[0x%016lx] */\n ", offset, offset + csc->relocs_bo[i]->va);
+ fprintf(dump, " /* [0x%08x] va[0x%016llx] */\n ", offset, offset + csc->relocs_bo[i]->va);
}
fprintf(dump, " 0x%08x,", ptr[j]);
}
ptr = radeon_bo_do_map(csc->relocs_bo[i]);
if (ptr) {
- fprintf(dump, " bo[%d] = bo_new(&ctx, %d, bo_%04d_data, 0x%016lx, 0x%08x);\n",
+ fprintf(dump, " bo[%d] = bo_new(&ctx, %d, bo_%04d_data, 0x%016llx, 0x%08x);\n",
i, ndw, i, csc->relocs_bo[i]->va, csc->relocs_bo[i]->base.alignment);
} else {
- fprintf(dump, " bo[%d] = bo_new(&ctx, %d, NULL, 0x%016lx, 0x%08x);\n",
+ fprintf(dump, " bo[%d] = bo_new(&ctx, %d, NULL, 0x%016llx, 0x%08x);\n",
i, ndw, csc->relocs_bo[i]->va, csc->relocs_bo[i]->base.alignment);
}
}