bank: add RE signal for registers made of fields

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index c87650898b99f007037723937ba2d2eeb69983c9..fed5058dc57a756f626054491e2726382da07281 100644 (file)
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -34,6 +34,7 @@ class Bank:
                                                bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
                                        offset += field.size
                                if len(bwra) > 1:
+                                       bwra.append(reg.re.eq(1))
                                        bwcases.append(bwra)
                        else:
                                raise TypeError

diff --git a/migen/bank/description.py b/migen/bank/description.py
index 415ed809a9c49a1748952f2a299b39a94ce508b0..4c9b5b6d5d7ba79942f142697f5c48a6a0560b3b 100644 (file)
--- a/migen/bank/description.py
+++ b/migen/bank/description.py
@@ -27,9 +27,13 @@ class Field:
                                self.we = Signal()
 
 class RegisterFields:
-       def __init__(self, name, fields):
+       def __init__(self, name, fields, re=None):
                self.name = name
                self.fields = fields
+               if re is None:
+                       self.re = Signal()
+               else:
+                       self.re = re
 
 class RegisterField(RegisterFields):
        def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
@@ -71,7 +75,7 @@ def expand_description(description, busword):
                                else:
                                        f.append(field)
                        if f:
-                               d.append(RegisterFields(reg.name, f))
+                               d.append(RegisterFields(reg.name, f, reg.re))
                else:
                        raise TypeError
        return d