ecp5 to use abc_map.v and _unmap.v

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 73e18112f98ac792d8f82f1cfc5462f1ac21f176..cffd5c3a43787a208de0537b975b015c812bb58d 100644 (file)
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))

diff --git a/techlibs/ecp5/abc_5g.box b/techlibs/ecp5/abc_5g.box
index c757d137d816ed16ec5300b2310c69f2884830b7..66ebe196abe02116b97b94c735978b9b801f7d65 100644 (file)
--- a/techlibs/ecp5/abc_5g.box
+++ b/techlibs/ecp5/abc_5g.box
@@ -15,16 +15,16 @@ CCU2C   1      1   9      3
 630  379  630  379  526   275  392  141  273
 516  516  516  516  412   412  278  278  43
 
-# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
+# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
 # Outputs: DO0, DO1, DO2, DO3
-# name            ID  w/b   ins   outs
-TRELLIS_DPR16X4   2     0   14    4
-
-#DI0   DI1   DI2   DI3   RAD0   RAD1   RAD2   RAD3   WAD0    WAD1   WAD2   WAD3  WCK   WRE
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
--      -     -     -     141    379    275    379    -       -      -      -     -     -
+# name               ID  w/b   ins   outs
+$__ABC_RAM16X2_COMB  2     0   8    4
+
+#A0   A1   A2   A3   RAD0   RAD1   RAD2   RAD3
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
+0     0    0    0    141    379    275    379
 
 # Box 3 : PFUMX (MUX2)
 # Outputs: Z

diff --git a/techlibs/ecp5/abc_map.v b/techlibs/ecp5/abc_map.v
new file mode 100644 (file)
index 0000000..e8187ed
--- /dev/null
+++ b/techlibs/ecp5/abc_map.v
@@ -0,0 +1,24 @@
+// ---------------------------------------
+
+module TRELLIS_DPR16X4 (
+       input  [3:0] DI,
+       input  [3:0] WAD,
+       input        WRE,
+       input        WCK,
+       input  [3:0] RAD,
+       output [3:0] DO
+);
+       parameter WCKMUX = "WCK";
+       parameter WREMUX = "WRE";
+       parameter [63:0] INITVAL = 64'h0000000000000000;
+    wire [3:0] \$DO ;
+
+    \$__ABC_DPR16X4_SEQ #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(\$DO )
+    );
+
+    \$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
+endmodule

diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
new file mode 100644 (file)
index 0000000..4eb923c
--- /dev/null
+++ b/techlibs/ecp5/abc_model.v
@@ -0,0 +1,18 @@
+// ---------------------------------------
+
+(* abc_box_id=2 *)
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+       input  [3:0] DI,
+       input  [3:0] WAD,
+       input        WRE,
+       input        WCK,
+       input  [3:0] RAD,
+       output [3:0] DO
+);
+       parameter WCKMUX = "WCK";
+       parameter WREMUX = "WRE";
+       parameter [63:0] INITVAL = 64'h0000000000000000;
+endmodule

diff --git a/techlibs/ecp5/abc_unmap.v b/techlibs/ecp5/abc_unmap.v
new file mode 100644 (file)
index 0000000..0f918c2
--- /dev/null
+++ b/techlibs/ecp5/abc_unmap.v
@@ -0,0 +1,25 @@
+// ---------------------------------------
+
+module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
+    assign Y = A;
+endmodule
+
+module \$__ABC_DPR16X4_SEQ (
+       input  [3:0] DI,
+       input  [3:0] WAD,
+       input        WRE,
+       input        WCK,
+       input  [3:0] RAD,
+       output [3:0] DO
+);
+       parameter WCKMUX = "WCK";
+       parameter WREMUX = "WRE";
+       parameter [63:0] INITVAL = 64'h0000000000000000;
+
+    TRELLIS_DPR16X4 #(
+      .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
+    ) _TECHMAP_REPLACE_ (
+      .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
+      .RAD(RAD), .DO(DO)
+    );
+endmodule

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369edf1a0839bc4560f4d3a3f6c18f06496..f79a2731270c76dcc32af4649595b6fe655b4615 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -107,11 +107,10 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
 endmodule
 
 // ---------------------------------------
-//(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-       (* abc_scc_break *) input [3:0] DI,
-       (* abc_scc_break *) input [3:0] WAD,
-       (* abc_scc_break *) input       WRE,
+       input  [3:0] DI,
+       input  [3:0] WAD,
+       input        WRE,
        input        WCK,
        input  [3:0] RAD,
        output [3:0] DO

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 143d1f95c0c48828d133e77a12c183c9a077357a..93e1cd5b5a28204604f21eb76b18de70f85ce401 100644 (file)
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -278,12 +278,18 @@ struct SynthEcp5Pass : public ScriptPass
                        if (abc2 || help_mode) {
                                run("abc", "      (only if -abc2)");
                        }
-                       run("techmap -map +/ecp5/latches_map.v");
+                       std::string techmap_args = "-map +/ecp5/latches_map.v";
+                       if (abc9)
+                               techmap_args += " -map +/ecp5/abc_map.v";
+                       run("techmap " + techmap_args);
+
                        if (abc9) {
+                               run("read_verilog -icells -lib +/ecp5/abc_model.v");
                                if (nowidelut)
                                        run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
                                else
                                        run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
+                               run("techmap -map +/ecp5/abc_unmap.v");
                        } else {
                                if (nowidelut)
                                        run("abc -lut 4 -dress");