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diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 86ae3b4de7f76a98fa4d215635735e2d5a986980..ca1eb1539da170cb05198c8b062141b353fb678a 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -39,7 +39,7 @@ When Rc=1 the CR element however is still stored in the CR regfile, even if the
 basic structure packing on sub-elements. Bits 4-5 (normally elwidth) are
 taken up as Pack/Unpack bits. Saturation may be simultaneously enabled.
 
-Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  normal, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.
+Note that ffirst and reduce modes are not anticipated to be high-performance in some implementations.  ffirst due to interactions with VL, and reduce due to it requiring additional operations to produce a result.  simple, saturate and pred-result are however inter-element independent and may easily be parallelised to give high performance, regardless of the value of VL.
 
 The Mode table for Arithmetic and Logical operations
  is laid out as follows: