Fix gearing

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index 0841ea25f2155708e7c1e30a38f299d9ddd68bf0..dda05f23b0a87be2a0620eb09c9265c7426a146a 100644 (file)
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -58,7 +58,7 @@ class DDR3SoC(SoC, Elaboratable):
             write_latency=cwl_sys_latency
         )
 
-        ddrmodule = MT41K256M16(clk_freq, "1:4")
+        ddrmodule = MT41K256M16(clk_freq, "1:2")
         self.ddrphy = FakePHY(module=ddrmodule,
             settings=physettings,
             verbosity=SDRAM_VERBOSE_DBG)