Define PLL's PHASELOADREG input

diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index 769e2da92997dd7ae4fa1e7167bd285385ce3a49..90f874a06af86671e6c9472e12b826716963e5ed 100644 (file)
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -68,6 +68,7 @@ class PLL(Elaboratable):
                        i_PHASESEL1=1,
                        i_PHASEDIR=0,
                        i_PHASESTEP=0,
+                       i_PHASELOADREG=0,
                        i_PLLWAKESYNC=0,
                        i_ENCLKOP=1,
                        i_ENCLKOS=1,