-#Copyright (c) 2005
-#The Regents of The University of Michigan
-#All Rights Reserved
+# Copyright (c) 2005
+# The Regents of The University of Michigan
+# All Rights Reserved
#
-#This code is part of the M5 simulator, developed by Nathan Binkert,
-#Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
-#from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
-#Schultz.
+# This code is part of the M5 simulator, developed by Nathan Binkert,
+# Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+# from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
+# Schultz.
#
-#Permission is granted to use, copy, create derivative works and
-#redistribute this software and such derivative works for any purpose,
-#so long as the copyright notice above, this grant of permission, and
-#the disclaimer below appear in all copies made; and so long as the
-#name of The University of Michigan is not used in any advertising or
-#publicity pertaining to the use or distribution of this software
-#without specific, written prior authorization.
+# Permission is granted to use, copy, create derivative works and
+# redistribute this software and such derivative works for any purpose,
+# so long as the copyright notice above, this grant of permission, and
+# the disclaimer below appear in all copies made; and so long as the
+# name of The University of Michigan is not used in any advertising or
+# publicity pertaining to the use or distribution of this software
+# without specific, written prior authorization.
#
-#THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-#UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
-#WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
-#IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
-#MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
-#THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
-#INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
-#DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
-#WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
-#ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-
-DBMENTRY = fffffc0000010000
-CFLAGS=-I . -I ../h -I$(M5)/dev -nostdinc++ -Wa,-m21164
-
-ARCHNAME=$(shell uname -m)
+# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
+# WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
+# THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
+# INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+# DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
+# WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
### If we are not compiling on an alpha, we must use cross tools ###
-ifneq ($(ARCHNAME), alpha)
+ifneq ($(shell uname -m), alpha)
CROSS_COMPILE?=alpha-unknown-linux-gnu-
endif
CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
+DBMENTRY= fffffc0000010000
+CFLAGS=-I . -I ../h -I$(M5)/dev -fno-builtin -Wa,-m21164
OBJS=dbmentry.o printf.o paljtokern.o paljtoslave.o
TLOBJS+=$(OBJS) console_tl.o
TSOBJS+=$(OBJS) console_ts.o
$(CC) $(CFLAGS) -nostdinc -o $@ -c $<
console_ts.o: console.c
- $(CC) -g3 $(CFLAGS) -D _TIME_T -D TSUNAMI -o $@ -c $<
+ $(CC) -g3 $(CFLAGS) -D TSUNAMI -o $@ -c $<
console_tl.o: console.c
- $(CC) -g3 $(CFLAGS) -D _TIME_T -D TLASER -o $@ -c $<
+ $(CC) -g3 $(CFLAGS) -D TLASER -o $@ -c $<
printf.o: printf.c
$(CC) -g3 $(CFLAGS) -o $@ -c $<
console_ts: $(TSOBJS)
- $(LD) -o console_ts -N -Ttext $(DBMENTRY) -non_shared $(TSOBJS) -lc
+ $(LD) -o console_ts -N -Ttext $(DBMENTRY) -non_shared $(TSOBJS) -lc
console_tl: $(TLOBJS)
- $(LD) -o console_tl -N -Ttext $(DBMENTRY) -non_shared $(TLOBJS) -lc
+ $(LD) -o console_tl -N -Ttext $(DBMENTRY) -non_shared $(TLOBJS) -lc
clean:
rm -f *.o console_t?
/*
-Copyright (c) 2003, 2004
-The Regents of The University of Michigan
-All Rights Reserved
-
-This code is part of the M5 simulator, developed by Nathan Binkert,
-Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
-from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
-Schultz.
-
-Permission is granted to use, copy, create derivative works and
-redistribute this software and such derivative works for any purpose,
-so long as the copyright notice above, this grant of permission, and
-the disclaimer below appear in all copies made; and so long as the
-name of The University of Michigan is not used in any advertising or
-publicity pertaining to the use or distribution of this software
-without specific, written prior authorization.
-
-THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
-WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
-IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
-THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
-INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
-DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
-WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
-ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-*/
+ * Copyright (c) 2003, 2004
+ * The Regents of The University of Michigan
+ * All Rights Reserved
+ *
+ * This code is part of the M5 simulator, developed by Nathan Binkert,
+ * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+ * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
+ * Schultz.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * redistribute this software and such derivative works for any purpose,
+ * so long as the copyright notice above, this grant of permission, and
+ * the disclaimer below appear in all copies made; and so long as the
+ * name of The University of Michigan is not used in any advertising or
+ * publicity pertaining to the use or distribution of this software
+ * without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
+ * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
+ * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
+ * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
+ * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-/* ******************************************
- * SimOS SRM Console
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
*
- * Derived from Lance Berc's SRM console
- * for the SRC XXMÂ Machine
- * ******************************************/
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+/* ******************************************
+ * M5 Console
+ * ******************************************/
-typedef unsigned long long uint64_t;
-typedef unsigned long long uint64;
-typedef unsigned int uint32_t;
-typedef unsigned int uint32;
+#include <linux/stddef.h>
+#include <sys/types.h>
#define CONSOLE
#include "alpha_access.h"
-
-#if 0
-#include "new_aouthdr.h"
-#include "srcmax.h"
-#endif
-
-/* from ../h */
-#include "lib.h"
-#include "rpb.h"
#include "cserve.h"
+#include "rpb.h"
#define CONS_INT_TX 0x01 /* interrupt enable / state bits */
#define CONS_INT_RX 0x02
+#define PAGE_SIZE (8192)
+
#define KSEG 0xfffffc0000000000
#define K1BASE 0xfffffc8000000000
-#define KSEG_TO_PHYS(x)(((ul)x) & ~KSEG)
+#define KSEG_TO_PHYS(x) (((ulong)x) & ~KSEG)
#ifdef TSUNAMI
#define ALPHA_ACCESS_BASE 0xfffffd0200000000
#error TSUNAMI/TLASER not defined.
#endif
-#define PHYS_TO_K1(_x) (K1BASE|(_x))
+#define ROUNDUP8(x) ((ulong)(((ulong)x)+7) & ~7)
+#define ROUNDUP128(x) ((ulong)(((ulong)x) + 127) & ~127)
+#define ROUNDUP8K(x) ((ulong)(((ulong)(x)) + 8191) & ~8191)
-#define AOUT_LOAD_ADDR (KSEG|0xf000)
-
-#define ROUNDUP8(x) ((ul)(((ul)x)+7) & ~7)
-#define ROUNDUP128(x) ((ul)(((ul)x)+127) & ~127)
-#define ROUNDUP8K(x) ((ul)(((ul)(x))+8191) & ~8191)
-
-#define FIRST(x) ((((ul)(x)) >> 33) & 0x3ff)
-#define SECOND(x) ((((ul)(x)) >> 23) & 0x3ff)
-#define THIRD(x) ((((ul)(x)) >> 13) & 0x3ff)
-#define THIRD_XXX(x) ((((ul)(x)) >> 13) & 0xfff)
-#define PFN(x) ((((ul)(x) & ~KSEG) >> 13))
+#define FIRST(x) ((((ulong)(x)) >> 33) & 0x3ff)
+#define SECOND(x) ((((ulong)(x)) >> 23) & 0x3ff)
+#define THIRD(x) ((((ulong)(x)) >> 13) & 0x3ff)
+#define THIRD_XXX(x) ((((ulong)(x)) >> 13) & 0xfff)
+#define PFN(x) ((((ulong)(x) & ~KSEG) >> 13))
/* Kernel write | kernel read | valid */
-#define KPTE(x) ((ul)((((ul)(x)) << 32) | 0x1101))
+#define KPTE(x) ((ulong)((((ulong)(x)) << 32) | 0x1101))
#define HWRPB_PAGES 16
#define MDT_BITMAP_PAGES 4
-#define CSERVE_K_JTOKERN 0x18
-
#define NUM_KERNEL_THIRD (4)
-#define printf_lock(args...) \
- do { \
- SpinLock(&theLock); \
- printf(args); \
- SpinUnlock(&theLock); \
+#define printf_lock(args...) \
+ do { \
+ SpinLock(&theLock); \
+ printf(args); \
+ SpinUnlock(&theLock); \
} while (0)
-static unixBoot(int go, int argc, char **argv);
-void jToPal(ul bootadr);
+void unixBoot(int go, int argc, char **argv);
+void JToKern(char *bootadr, ulong rpb_percpu, ulong free_pfn, ulong k_argc,
+ char **k_argv, char **envp);
+void JToPal(ulong bootadr);
void SlaveLoop(int cpu);
+struct AlphaAccess m5Conf;
-struct AlphaAccess simosConf;
-
-/* **************************************************************
- * Console callbacks use VMS calling conventions
- * read AXP manual, 2-64.
- * ***************************************************************/
-typedef struct OpenVMSFunc {
- long dummy;
- long func;
-}OpenVMSFunc;
-
-OpenVMSFunc callbackFunc, fixupFunc;
+ulong theLock;
-
-
-
-ul theLock;
-
-
-extern void SpinLock(ul *lock);
+extern void SpinLock(ulong *lock);
#define SpinUnlock(_x) *(_x) = 0;
struct _kernel_params {
- char *bootadr;
- ul rpb_percpu;
- ul free_pfn;
- ul argc;
- ul argv;
- ul envp; /* NULL */
+ char *bootadr;
+ ulong rpb_percpu;
+ ulong free_pfn;
+ ulong argc;
+ ulong argv;
+ ulong envp; /* NULL */
};
-
extern consoleCallback[];
extern consoleFixup[];
long CallBackDispatcher();
long CallBackFixup();
/*
- * simos console output
+ * m5 console output
*/
-void InitConsole(void)
+void
+InitConsole()
{
-#if 0
- CDR->intr_status =(DevRegister)(DEV_CNSLE_RX_INTR |DEV_CNSLE_TX_INTR);
-#endif
}
-char GetChar()
+char
+GetChar()
{
- struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
- return k1Conf->inputChar;
+ struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
+ return k1Conf->inputChar;
}
-void PutChar(char c)
+void
+PutChar(char c)
{
-#if 0
- CDR->data = c;
-#endif
-#if 0
- *(int*) PHYS_TO_K1(SLOT_D_COM1<<5) = c;
-#endif
- struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
- k1Conf->outputChar = c;
-
+ struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
+ k1Conf->outputChar = c;
}
-
int
passArgs(int argc)
-{ return 0; }
+{
+ return 0;
+}
int
main(int argc, char **argv)
{
- int x,i;
- struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
- ui *k1ptr,*ksegptr;
-
-
- InitConsole();
- printf_lock("M5 console\n");
- /*
- * get configuration from backdoor
- */
- simosConf.last_offset = k1Conf->last_offset;
- printf_lock("Got Configuration %d \n",simosConf.last_offset);
-
- simosConf.last_offset = k1Conf->last_offset;
- simosConf.version = k1Conf->version;
- simosConf.numCPUs = k1Conf->numCPUs;
- simosConf.intrClockFrequency = k1Conf->intrClockFrequency;
- simosConf.cpuClock = k1Conf->cpuClock;
- simosConf.mem_size = k1Conf->mem_size;
- simosConf.kernStart = k1Conf->kernStart;
- simosConf.kernEnd = k1Conf->kernEnd;
- simosConf.entryPoint = k1Conf->entryPoint;
- simosConf.diskUnit = k1Conf->diskUnit;
- simosConf.diskCount = k1Conf->diskCount;
- simosConf.diskPAddr = k1Conf->diskPAddr;
- simosConf.diskBlock = k1Conf->diskBlock;
- simosConf.diskOperation = k1Conf->diskOperation;
- simosConf.outputChar = k1Conf->outputChar;
- simosConf.inputChar = k1Conf->inputChar;
- simosConf.bootStrapImpure = k1Conf->bootStrapImpure;
- simosConf.bootStrapCPU = k1Conf->bootStrapCPU;
-
- if (simosConf.version != ALPHA_ACCESS_VERSION) {
- panic("Console version mismatch. Console expects %d. has %d \n",
- ALPHA_ACCESS_VERSION,simosConf.version);
- }
-
-
- /*
- * setup arguments to kernel
- */
- unixBoot(1,argc,argv);
-
- x = *(volatile int *)(K1BASE-4);
- while(1) continue;
- return x;
+ int x, i;
+ struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
+ uint *k1ptr, *ksegptr;
+
+ InitConsole();
+ printf_lock("M5 console\n");
+
+ /*
+ * get configuration from backdoor
+ */
+ m5Conf.last_offset = k1Conf->last_offset;
+ printf_lock("Got Configuration %d\n", m5Conf.last_offset);
+
+ m5Conf.last_offset = k1Conf->last_offset;
+ m5Conf.version = k1Conf->version;
+ m5Conf.numCPUs = k1Conf->numCPUs;
+ m5Conf.intrClockFrequency = k1Conf->intrClockFrequency;
+ m5Conf.cpuClock = k1Conf->cpuClock;
+ m5Conf.mem_size = k1Conf->mem_size;
+ m5Conf.kernStart = k1Conf->kernStart;
+ m5Conf.kernEnd = k1Conf->kernEnd;
+ m5Conf.entryPoint = k1Conf->entryPoint;
+ m5Conf.diskUnit = k1Conf->diskUnit;
+ m5Conf.diskCount = k1Conf->diskCount;
+ m5Conf.diskPAddr = k1Conf->diskPAddr;
+ m5Conf.diskBlock = k1Conf->diskBlock;
+ m5Conf.diskOperation = k1Conf->diskOperation;
+ m5Conf.outputChar = k1Conf->outputChar;
+ m5Conf.inputChar = k1Conf->inputChar;
+ m5Conf.bootStrapImpure = k1Conf->bootStrapImpure;
+ m5Conf.bootStrapCPU = k1Conf->bootStrapCPU;
+
+ if (m5Conf.version != ALPHA_ACCESS_VERSION) {
+ panic("Console version mismatch. Console expects %d. has %d \n",
+ ALPHA_ACCESS_VERSION, m5Conf.version);
+ }
+
+ /*
+ * setup arguments to kernel
+ */
+ unixBoot(1, argc, argv);
+
+ x = *(volatile int *)(K1BASE-4);
+ while (1)
+ continue;
+ return x;
}
/*
* BOOTING
*/
-struct rpb xxm_rpb = {
- NULL, /* 000: physical self-reference */
- ((long)'H') | (((long)'W') << 8) | (((long)'R') << 16) |
- ((long)'P' << 24) | (((long)'B') << 32), /* 008: contains string "HWRPB" */
- 6, /* 010: HWRPB version number */
- /* the byte count is wrong, but who needs it? - lance */
- 0, /* 018: bytes in RPB perCPU CTB CRB MEDSC */
- 0, /* 020: primary cpu id */
- 8192, /* 028: page size in bytes */
- 43, /* 030: number of phys addr bits */
- 127, /* 038: max valid ASN */
- {'0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '1'}, /* 040: system serial num: 10 ascii chars */
-#ifdef undef
-/* To be legitimate, the following system type and variation are correct for the XXM.
- But there are too many #ifdefs etc to deal with in Unix, so we tell the kernel
- that we're an Avanti, which is similar enough.
- */
- 31, /* 050: system type - XXM is now in the Alpha SRM */
- (1 << 10) | (2<<1),/* 058: system variation - XXM w/EV5 & embeded console */
-#endif
-#if 0
- 0x12, /* 050: system type - masquarade as some random 21064 */
-#endif
- 0, /* OVERRIDDEN */
- (1<<10), /* 058: system variation OVERRIDDEN */
- 'c'|('o'<<8)|('o'<<16)|('l'<< 24), /* 060: system revision */
- 1024*4096, /* 068: scaled interval clock intr freq OVERRIDEN*/
- 0, /* 070: cycle counter frequency */
- 0x200000000, /* 078: virtual page table base */
- 0, /* 080: reserved */
- 0, /* 088: offset to translation buffer hint */
- 1, /* 090: number of processor slots OVERRIDDEN*/
- sizeof(struct rpb_percpu), /* 098: per-cpu slot size. OVERRIDDEN */
- 0, /* 0A0: offset to per_cpu slots */
- 1, /* 0A8: number of CTBs */
-#ifdef bugnion_gone
- sizeof(struct rpb_ctb), /* 0B0: bytes in largest CTB */
-#else
- sizeof(struct ctb_tt),
-#endif
- 0, /* 0B8: offset to CTB (cons term block) */
- 0, /* 0C0: offset to CRB (cons routine block) */
- 0, /* 0C8: offset to memory descriptor table */
- 0, /* 0D0: offset to config data block */
- 0, /* 0D8: offset to FRU table */
- 0, /* 0E0: virt addr of save term routine */
- 0, /* 0E8: proc value for save term routine */
- 0, /* 0F0: virt addr of restore term routine */
- 0, /* 0F8: proc value for restore term routine */
- 0, /* 100: virt addr of CPU restart routine */
- 0, /* 108: proc value for CPU restart routine */
- 0, /* 110: used to determine presence of kdebug */
- 0, /* 118: reserved for hardware */
+struct rpb m5_rpb = {
+ NULL, /* 000: physical self-reference */
+ ((long)'H') | (((long)'W') << 8) | (((long)'R') << 16) |
+ ((long)'P' << 24) | (((long)'B') << 32), /* 008: contains "HWRPB" */
+ 6, /* 010: HWRPB version number */
+ /* the byte count is wrong, but who needs it? - lance */
+ 0, /* 018: bytes in RPB perCPU CTB CRB MEDSC */
+ 0, /* 020: primary cpu id */
+ PAGE_SIZE, /* 028: page size in bytes */
+ 43, /* 030: number of phys addr bits */
+ 127, /* 038: max valid ASN */
+ {'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1'},
+ /* 040: system serial num: 10 ascii chars */
+ 0, /* OVERRIDDEN */
+ (1<<10), /* 058: system variation */
+ 'c'|('o'<<8)|('o'<<16)|('l'<< 24), /* 060: system revision */
+ 1024*4096, /* 068: scaled interval clock intr freq */
+ 0, /* 070: cycle counter frequency */
+ 0x200000000, /* 078: virtual page table base */
+ 0, /* 080: reserved */
+ 0, /* 088: offset to translation buffer hint */
+ 1, /* 090: number of processor slots OVERRIDDEN*/
+ sizeof(struct rpb_percpu), /* 098: per-cpu slot size. OVERRIDDEN */
+ 0, /* 0A0: offset to per_cpu slots */
+ 1, /* 0A8: number of CTBs */
+ sizeof(struct ctb_tt),
+ 0, /* 0B8: offset to CTB (cons term block) */
+ 0, /* 0C0: offset to CRB (cons routine block) */
+ 0, /* 0C8: offset to memory descriptor table */
+ 0, /* 0D0: offset to config data block */
+ 0, /* 0D8: offset to FRU table */
+ 0, /* 0E0: virt addr of save term routine */
+ 0, /* 0E8: proc value for save term routine */
+ 0, /* 0F0: virt addr of restore term routine */
+ 0, /* 0F8: proc value for restore term routine */
+ 0, /* 100: virt addr of CPU restart routine */
+ 0, /* 108: proc value for CPU restart routine */
+ 0, /* 110: used to determine presence of kdebug */
+ 0, /* 118: reserved for hardware */
/* the checksum is wrong, but who needs it? - lance */
- 0, /* 120: checksum of prior entries in rpb */
- 0, /* 128: receive ready bitmask */
- 0, /* 130: transmit ready bitmask */
- 0, /* 138: Dynamic System Recog. offset */
+ 0, /* 120: checksum of prior entries in rpb */
+ 0, /* 128: receive ready bitmask */
+ 0, /* 130: transmit ready bitmask */
+ 0, /* 138: Dynamic System Recog. offset */
};
-ul xxm_tbb[] = { 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e,
- 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e};
-
-struct rpb_percpu xxm_rpb_percpu = {
- {0,0,0,0,0,0,1,{0,0},{0,0,0,0,0,0,0,0}}, /* 000: boot/restart HWPCB */
- (STATE_PA | STATE_PP | STATE_CV | STATE_PV | STATE_PMV | STATE_PL), /* 080: per-cpu state bits */
- 0xc000, /* 088: palcode memory length */
- 0x2000, /* 090: palcode scratch length */
- 0x4000, /* 098: phys addr of palcode mem space */
- 0x2000, /* 0A0: phys addr of palcode scratch space */
- (2 << 16) | (5 << 8) | 1, /* 0A8: PALcode rev required */
- 11 | (2L << 32), /* 0B0: processor type */
- 7, /* 0B8: processor variation */
- 'M'|('5'<<8)|('A'<<16)|('0'<<24), /* 0C0: processor revision */
- {'M','5','/','A','l','p','h','a','0','0','0','0','0','0','0','0'}, /* 0C8: proc serial num: 10 ascii chars */
- 0, /* 0D8: phys addr of logout area */
- 0, /* 0E0: length in bytes of logout area */
- 0, /* 0E8: halt pcb base */
- 0, /* 0F0: halt pc */
- 0, /* 0F8: halt ps */
- 0, /* 100: halt arg list (R25) */
- 0, /* 108: halt return address (R26) */
- 0, /* 110: halt procedure value (R27) */
- 0, /* 118: reason for halt */
- 0, /* 120: for software */
- {0}, /* 128: inter-console communications buffer */
- {1,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0}, /* 1D0: PALcode revs available */
- 0 /* 250: reserved for arch use */
+ulong m5_tbb[] = { 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e,
+ 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e,
+ 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e,
+ 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e };
+
+struct rpb_percpu m5_rpb_percpu = {
+ {0,0,0,0,0,0,1,{0,0},{0,0,0,0,0,0,0,0}}, /* 000: boot/restart HWPCB */
+ (STATE_PA | STATE_PP | STATE_CV |
+ STATE_PV | STATE_PMV | STATE_PL), /* 080: per-cpu state bits */
+ 0xc000, /* 088: palcode memory length */
+ 0x2000, /* 090: palcode scratch length */
+ 0x4000, /* 098: paddr of pal mem space */
+ 0x2000, /* 0A0: paddr of pal scratch space */
+ (2 << 16) | (5 << 8) | 1, /* 0A8: PALcode rev required */
+ 11 | (2L << 32), /* 0B0: processor type */
+ 7, /* 0B8: processor variation */
+ 'M'|('5'<<8)|('A'<<16)|('0'<<24), /* 0C0: processor revision */
+ {'M','5','/','A','l','p','h','a','0','0','0','0','0','0','0','0'},
+ /* 0C8: proc serial num: 10 chars */
+ 0, /* 0D8: phys addr of logout area */
+ 0, /* 0E0: len in bytes of logout area */
+ 0, /* 0E8: halt pcb base */
+ 0, /* 0F0: halt pc */
+ 0, /* 0F8: halt ps */
+ 0, /* 100: halt arg list (R25) */
+ 0, /* 108: halt return address (R26) */
+ 0, /* 110: halt procedure value (R27) */
+ 0, /* 118: reason for halt */
+ 0, /* 120: for software */
+ {0}, /* 128: inter-console comm buffer */
+ {1,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0}, /* 1D0: PALcode revs available */
+ 0 /* 250: reserved for arch use */
/* the dump stack grows from the end of the rpb page not to reach here */
};
-struct _xxm_rpb_mdt {
- long rpb_checksum; /* 000: checksum of entire mem desc table */
- long rpb_impaddr; /* 008: PA of implementation dep info */
- long rpb_numcl; /* 010: number of clusters */
- struct rpb_cluster rpb_cluster[3]; /* first instance of a cluster */
+struct _m5_rpb_mdt {
+ long rpb_checksum; /* 000: checksum of entire mem desc table */
+ long rpb_impaddr; /* 008: PA of implementation dep info */
+ long rpb_numcl; /* 010: number of clusters */
+ struct rpb_cluster rpb_cluster[3]; /* first instance of a cluster */
};
-struct _xxm_rpb_mdt xxm_rpb_mdt = {
- 0, /* 000: checksum of entire mem desc table */
- 0, /* 008: PA of implementation dep info */
- 0, /* 010: number of clusters */
- {{ 0, /* 000: starting PFN of this cluster */
+struct _m5_rpb_mdt m5_rpb_mdt = {
+ 0, /* 000: checksum of entire mem desc table */
+ 0, /* 008: PA of implementation dep info */
+ 0, /* 010: number of clusters */
+ {{ 0, /* 000: starting PFN of this cluster */
0, /* 008: count of PFNs in this cluster */
0, /* 010: count of tested PFNs in cluster */
0, /* 018: va of bitmap */
0, /* 020: pa of bitmap */
0, /* 028: checksum of bitmap */
1 /* 030: usage of cluster */
- },
- { 0, /* 000: starting PFN of this cluster */
- 0, /* 008: count of PFNs in this cluster */
- 0, /* 010: count of tested PFNs in cluster */
- 0, /* 018: va of bitmap */
- 0, /* 020: pa of bitmap */
- 0, /* 028: checksum of bitmap */
- 0 /* 030: usage of cluster */
- },
- { 0, /* 000: starting PFN of this cluster */
- 0, /* 008: count of PFNs in this cluster */
- 0, /* 010: count of tested PFNs in cluster */
- 0, /* 018: va of bitmap */
- 0, /* 020: pa of bitmap */
- 0, /* 028: checksum of bitmap */
- 0 /* 030: usage of cluster */
- }}
+ },
+ { 0, /* 000: starting PFN of this cluster */
+ 0, /* 008: count of PFNs in this cluster */
+ 0, /* 010: count of tested PFNs in cluster */
+ 0, /* 018: va of bitmap */
+ 0, /* 020: pa of bitmap */
+ 0, /* 028: checksum of bitmap */
+ 0 /* 030: usage of cluster */
+ },
+ { 0, /* 000: starting PFN of this cluster */
+ 0, /* 008: count of PFNs in this cluster */
+ 0, /* 010: count of tested PFNs in cluster */
+ 0, /* 018: va of bitmap */
+ 0, /* 020: pa of bitmap */
+ 0, /* 028: checksum of bitmap */
+ 0 /* 030: usage of cluster */
+ }}
};
/* constants for slotinfo bus_type subfield */
#define SLOTINFO_EISA 2
#define SLOTINFO_PCI 3
-struct rpb_ctb xxm_rpb_ctb = {
- CONS_DZ, /* 000: console type */
- 0, /* 008: console unit */
- 0, /* 010: reserved */
- 0 /* 018: byte length of device dep portion */
+struct rpb_ctb m5_rpb_ctb = {
+ CONS_DZ, /* 000: console type */
+ 0, /* 008: console unit */
+ 0, /* 010: reserved */
+ 0 /* 018: byte length of device dep portion */
};
/* we don't do any fixup (aka relocate the console) - we hope */
-struct rpb_crb xxm_rpb_crb = {
- 0, /* va of call-back dispatch rtn */
- 0, /* pa of call-back dispatch rtn */
- 0, /* va of call-back fixup rtn */
- 0, /* pa of call-back fixup rtn */
- 0, /* number of entries in phys/virt map */
- 0 /* Number of pages to be mapped */
+struct rpb_crb m5_rpb_crb = {
+ 0, /* va of call-back dispatch rtn */
+ 0, /* pa of call-back dispatch rtn */
+ 0, /* va of call-back fixup rtn */
+ 0, /* pa of call-back fixup rtn */
+ 0, /* number of entries in phys/virt map */
+ 0 /* Number of pages to be mapped */
};
struct _rpb_name {
- unsigned long length;
- char name[16];
+ ulong length;
+ char name[16];
};
-extern struct _rpb_name xxm_name;
+extern struct _rpb_name m5_name;
-struct rpb_dsr xxm_rpb_dsr = {
- 0,
- 0,
- 0,
+struct rpb_dsr m5_rpb_dsr = {
+ 0,
+ 0,
+ 0,
};
-struct _rpb_name xxm_name = {
- 16,
- {'D','E','C',' ','S','R','C',' ','X','X','M',' ','D','G','C',0},
+struct _rpb_name m5_name = {
+ 16,
+ {'U','M','I','C','H',' ','M','5','/','A','L','P','H','A',' ',0},
};
-/* XXM has one LURT entry - 1050 is for workstations, 1100 is servers (and is needed for CXX) */
-long xxm_lurt[10] = { 9, 12, -1, -1, -1, -1, -1, -1, 1100, 1100 };
+/*
+ * M5 has one LURT entry:
+ * 1050 is for workstations
+ * 1100 is servers (and is needed for CXX)
+ */
+long m5_lurt[10] = { 9, 12, -1, -1, -1, -1, -1, -1, 1100, 1100 };
+
+ulong unix_boot_mem;
+ulong bootadr;
-ul unix_boot_mem;
-unsigned long bootadr;
-#if 0
-unsigned long aout_bss_addr, aout_bss_size, aout_entry, aout_text_start, aout_data_addr;
-#endif
char **kargv;
int kargc;
-ul free_pfn;
+ulong free_pfn;
struct rpb_percpu *rpb_percpu;
-
#define MAX_CPUS 32
-ul bootStrapImpure[MAX_CPUS];
+ulong bootStrapImpure[MAX_CPUS];
-
-char *unix_boot_alloc(int pages)
+char *
+unix_boot_alloc(int pages)
{
- char *ret = (char *) unix_boot_mem;
- unix_boot_mem += (pages * 8192);
- return ret;
+ char *ret = (char *) unix_boot_mem;
+ unix_boot_mem += (pages * PAGE_SIZE);
+ return ret;
}
-ul *first = 0;
-ul *third_rpb = 0;
-ul *reservedFixup = 0;
+ulong *first = 0;
+ulong *third_rpb = 0;
+ulong *reservedFixup = 0;
int strcpy(char *dst, char *src);
struct rpb *rpb;
+extern ulong _end;
+void
unixBoot(int go, int argc, char **argv)
{
- ul *second, *third_kernel, ptr, *tbb, size, *percpu_logout;
- unsigned char *mdt_bitmap;
- long *lp1, *lp2, sum;
- int i, cl;
- int kern_first_page;
- int mem_size = simosConf.mem_size;
-
- int mem_pages = mem_size / 8192, cons_pages;
- ul kernel_bytes, ksp, kernel_end, *unix_kernel_stack, bss, ksp_bottom, ksp_top;
- struct rpb_ctb *rpb_ctb;
- struct ctb_tt *ctb_tt;
- struct rpb_dsr *rpb_dsr;
- struct rpb_crb *rpb_crb;
- struct _xxm_rpb_mdt *rpb_mdt;
- int *rpb_lurt;
- char *rpb_name;
- ul nextPtr;
-
- printf_lock( "memsize %x pages %x \n",mem_size,mem_pages);
-
-
-
-#ifdef notnow
- if (unixArgs()) return;
-#endif
-
- /* Allocate:
- * two pages for the HWRPB
- * five page table pages:
- * 1: First level page table
- * 1: Second level page table
- * 1: Third level page table for HWRPB
- * 2: Third level page table for kernel (for up to 16MB)
- * set up the page tables
- * load the kernel at the physical address 0x230000
- * build the HWRPB
- * set up memory descriptor table to give up the
- * physical memory between the end of the page
- * tables and the start of the kernel
- * enable kseg addressing
- * jump to the kernel
- */
-
- unix_boot_mem = ROUNDUP8K(&_end);
-
- printf_lock("First free page after ROM 0x%x\n", unix_boot_mem);
-
- rpb = (struct rpb *) unix_boot_alloc( HWRPB_PAGES);
-
- mdt_bitmap = (unsigned char *) unix_boot_alloc(MDT_BITMAP_PAGES);
- first = (ul *)unix_boot_alloc(1);
- second = (ul *)unix_boot_alloc(1);
- third_rpb = (ul *)unix_boot_alloc(1);
- reservedFixup = (ul*) unix_boot_alloc(1);
- third_kernel = (ul *)unix_boot_alloc(NUM_KERNEL_THIRD);
- percpu_logout = (ul*)unix_boot_alloc(1);
-
-
- cons_pages = KSEG_TO_PHYS(unix_boot_mem) / 8192;
-
- /* Set up the page tables */
- bzero((char *)first, 8192);
- bzero((char *)second, 8192);
- bzero((char *)reservedFixup,8192);
- bzero((char *)third_rpb, HWRPB_PAGES * 8192);
- bzero((char *)third_kernel, 8192 * NUM_KERNEL_THIRD);
-
- first[0] = KPTE(PFN(second));
- first[1] = KPTE(PFN(first)); /* Region 3 */
-
- second[SECOND(0x10000000)] = KPTE(PFN(third_rpb)); /* Region 0 */
-
- for (i=0;i<NUM_KERNEL_THIRD;i++) {
- second[SECOND(0x20000000)+i] = KPTE(PFN(third_kernel)+i); /* Region 1 */
- }
- second[SECOND(0x40000000)] = KPTE(PFN(second)); /* Region 2 */
-
-
- {
-
- /* For some obscure reason, Dec Unix's database read
- * from /etc/sysconfigtab is written to this fixed
- * mapped memory location. Go figure, since it is
- * not initialized by the console. Maybe it is
- * to look at the database from the console
- * after a boot/crash.
- *
- * Black magic to estimate the max size. SEGVs on overflow
- * bugnion
- */
+ ulong *second, *third_kernel, ptr, *tbb, size, *percpu_logout;
+ unsigned char *mdt_bitmap;
+ long *lp1, *lp2, sum;
+ int i, cl;
+ int kern_first_page;
+ int mem_size = m5Conf.mem_size;
+
+ int mem_pages = mem_size / PAGE_SIZE, cons_pages;
+ ulong kernel_bytes, ksp, kernel_end, *unix_kernel_stack, bss,
+ ksp_bottom, ksp_top;
+ struct rpb_ctb *rpb_ctb;
+ struct ctb_tt *ctb_tt;
+ struct rpb_dsr *rpb_dsr;
+ struct rpb_crb *rpb_crb;
+ struct _m5_rpb_mdt *rpb_mdt;
+ int *rpb_lurt;
+ char *rpb_name;
+ ulong nextPtr;
+
+ printf_lock("memsize %x pages %x \n", mem_size, mem_pages);
+
+ /* Allocate:
+ * two pages for the HWRPB
+ * five page table pages:
+ * 1: First level page table
+ * 1: Second level page table
+ * 1: Third level page table for HWRPB
+ * 2: Third level page table for kernel (for up to 16MB)
+ * set up the page tables
+ * load the kernel at the physical address 0x230000
+ * build the HWRPB
+ * set up memory descriptor table to give up the
+ * physical memory between the end of the page
+ * tables and the start of the kernel
+ * enable kseg addressing
+ * jump to the kernel
+ */
+
+ unix_boot_mem = ROUNDUP8K(&_end);
+
+ printf_lock("First free page after ROM 0x%x\n", unix_boot_mem);
+
+ rpb = (struct rpb *) unix_boot_alloc( HWRPB_PAGES);
+
+ mdt_bitmap = (unsigned char *) unix_boot_alloc(MDT_BITMAP_PAGES);
+ first = (ulong *)unix_boot_alloc(1);
+ second = (ulong *)unix_boot_alloc(1);
+ third_rpb = (ulong *)unix_boot_alloc(1);
+ reservedFixup = (ulong*) unix_boot_alloc(1);
+ third_kernel = (ulong *)unix_boot_alloc(NUM_KERNEL_THIRD);
+ percpu_logout = (ulong*)unix_boot_alloc(1);
+
+ cons_pages = KSEG_TO_PHYS(unix_boot_mem) / PAGE_SIZE;
+
+ /* Set up the page tables */
+ bzero((char *)first, PAGE_SIZE);
+ bzero((char *)second, PAGE_SIZE);
+ bzero((char *)reservedFixup, PAGE_SIZE);
+ bzero((char *)third_rpb, HWRPB_PAGES * PAGE_SIZE);
+ bzero((char *)third_kernel, PAGE_SIZE * NUM_KERNEL_THIRD);
+
+ first[0] = KPTE(PFN(second));
+ first[1] = KPTE(PFN(first)); /* Region 3 */
+
+ /* Region 0 */
+ second[SECOND(0x10000000)] = KPTE(PFN(third_rpb));
+
+ for (i = 0; i < NUM_KERNEL_THIRD; i++) {
+ /* Region 1 */
+ second[SECOND(0x20000000) + i] = KPTE(PFN(third_kernel) + i);
+ }
+ /* Region 2 */
+ second[SECOND(0x40000000)] = KPTE(PFN(second));
+
+
+ /* For some obscure reason, Dec Unix's database read
+ * from /etc/sysconfigtab is written to this fixed
+ * mapped memory location. Go figure, since it is
+ * not initialized by the console. Maybe it is
+ * to look at the database from the console
+ * after a boot/crash.
+ *
+ * Black magic to estimate the max size. SEGVs on overflow
+ * bugnion
+ */
#define DATABASE_BASE 0x20000000
-#ifdef not_not
-#define DATABASE_END 0x20230000 /* don't need all that */
-#endif
-
#define DATABASE_END 0x20020000
- int i;
- ul *dbPage = (ul*)unix_boot_alloc(1);
- second[SECOND(DATABASE_BASE)] = KPTE(PFN(dbPage));
- for (i=DATABASE_BASE; i <DATABASE_END ; i+= 8096) {
- ul *db = (ul*)unix_boot_alloc(1);
- dbPage[THIRD(i)] = KPTE(PFN(db));
- }
- }
+ ulong *dbPage = (ulong*)unix_boot_alloc(1);
+ second[SECOND(DATABASE_BASE)] = KPTE(PFN(dbPage));
+ for (i = DATABASE_BASE; i < DATABASE_END ; i += 8096) {
+ ulong *db = (ulong*)unix_boot_alloc(1);
+ dbPage[THIRD(i)] = KPTE(PFN(db));
+ }
- /* Region 0 */
- /* Map the HWRPB */
- for (i = 0; i < HWRPB_PAGES; i++) third_rpb[i] = KPTE(PFN(rpb) + i);
+ /* Region 0 */
+ /* Map the HWRPB */
+ for (i = 0; i < HWRPB_PAGES; i++)
+ third_rpb[i] = KPTE(PFN(rpb) + i);
- /* Map the MDT bitmap table */
- for (i=0;i<MDT_BITMAP_PAGES;i++) {
- third_rpb[HWRPB_PAGES+i] = KPTE(PFN(mdt_bitmap)+i);
- }
+ /* Map the MDT bitmap table */
+ for (i = 0; i < MDT_BITMAP_PAGES; i++) {
+ third_rpb[HWRPB_PAGES + i] = KPTE(PFN(mdt_bitmap) + i);
+ }
- /* Protect the PAL pages */
- for (i = 1; i < PFN(first); i++) third_rpb[HWRPB_PAGES + MDT_BITMAP_PAGES + i] = KPTE(i);
+ /* Protect the PAL pages */
+ for (i = 1; i < PFN(first); i++)
+ third_rpb[HWRPB_PAGES + MDT_BITMAP_PAGES + i] = KPTE(i);
/* Set up third_kernel after it's loaded, when we know where it is */
+ kern_first_page = (KSEG_TO_PHYS(m5Conf.kernStart)/PAGE_SIZE);
+ kernel_end = ksp_top = ROUNDUP8K(m5Conf.kernEnd);
+ bootadr = m5Conf.entryPoint;
+
+ printf_lock("HWRPB 0x%x l1pt 0x%x l2pt 0x%x l3pt_rpb 0x%x l3pt_kernel 0x%x"
+ " l2reserv 0x%x\n",
+ rpb, first, second, third_rpb, third_kernel, reservedFixup);
+ if (kernel_end - m5Conf.kernStart > (0x800000*NUM_KERNEL_THIRD)) {
+ printf_lock("Kernel is more than 8MB 0x%x - 0x%x = 0x%x\n",
+ kernel_end, m5Conf.kernStart,
+ kernel_end - m5Conf.kernStart );
+ panic("kernel too big\n");
+ }
+
+ /* Map the kernel's pages into the third level of region 2 */
+ for (ptr = m5Conf.kernStart; ptr < kernel_end; ptr += PAGE_SIZE) {
+ third_kernel[THIRD_XXX(ptr)] = KPTE(PFN(ptr));
+ }
+
+ /* blow 2 pages of phys mem for guards since it maintains 1-to-1 mapping */
+ ksp = ksp_top + (3 * PAGE_SIZE);
+ if (ksp - m5Conf.kernStart > (0x800000*NUM_KERNEL_THIRD)) {
+ printf_lock("Kernel stack pushd us over 8MB\n");
+ panic("ksp too big\n");
+ }
+ if (THIRD_XXX((ulong)ksp_top) > NUM_KERNEL_THIRD * 1024) {
+ panic("increase NUM_KERNEL_THIRD, and change THIRD_XXX\n");
+ }
+ ptr = (ulong) ksp_top;
+ bzero((char *)ptr, PAGE_SIZE * 2);
+ third_kernel[THIRD_XXX(ptr)] = 0; /* Stack Guard Page */
+ ptr += PAGE_SIZE;
+ third_kernel[THIRD_XXX(ptr)] = KPTE(PFN(ptr)); /* Kernel Stack Pages */
+ ptr += PAGE_SIZE;
+ third_kernel[THIRD_XXX(ptr)] = KPTE(PFN(ptr));
+ ptr += PAGE_SIZE;
+ third_kernel[THIRD_XXX(ptr)] = 0; /* Stack Guard Page */
+
+ /* put argv into the bottom of the stack - argv starts at 1 because
+ * the command thatr got us here (i.e. "unixboot) is in argv[0].
+ */
+ ksp -= 8; /* Back up one longword */
+ ksp -= argc * sizeof(char *); /* Make room for argv */
+ kargv = (char **) ksp;
+ for (i = 1; i < argc; i++) { /* Copy arguments to stack */
+ ksp -= ((strlen(argv[i]) + 1) + 7) & ~0x7;
+ kargv[i-1] = (char *) ksp;
+ strcpy(kargv[i - 1], argv[i]);
+ }
+ kargc = i - 1;
+ kargv[kargc] = NULL; /* just to be sure; doesn't seem to be used */
+ ksp -= sizeof(char *); /* point above last arg for no real reason */
+
+ free_pfn = PFN(ptr);
+
+ bcopy((char *)&m5_rpb, (char *)rpb, sizeof(struct rpb));
+
+ rpb->rpb_selfref = (struct rpb *) KSEG_TO_PHYS(rpb);
+ rpb->rpb_string = 0x0000004250525748;
+
+ tbb = (ulong *) (((char *) rpb) + ROUNDUP8(sizeof(struct rpb)));
+ rpb->rpb_trans_off = (ulong)tbb - (ulong)rpb;
+ bcopy((char *)m5_tbb, (char *)tbb, sizeof(m5_tbb));
+
+ /*
+ * rpb_counter. Use to determine timeouts in OS.
+ * XXX must be patched after a checkpoint restore (I guess)
+ */
+
+ printf_lock("CPU Clock at %d MHz IntrClockFrequency=%d \n",
+ m5Conf.cpuClock, m5Conf.intrClockFrequency);
+ rpb->rpb_counter = m5Conf.cpuClock * 1000 * 1000;
+
+ /*
+ * By definition, the rpb_clock is scaled by 4096 (in hz)
+ */
+ rpb->rpb_clock = m5Conf.intrClockFrequency * 4096;
+
+ /*
+ * Per CPU Slots. Multiprocessor support.
+ */
+ int percpu_size = ROUNDUP128(sizeof(struct rpb_percpu));
+
+ printf_lock("Booting with %d processor(s) \n", m5Conf.numCPUs);
+
+ rpb->rpb_numprocs = m5Conf.numCPUs;
+ rpb->rpb_slotsize = percpu_size;
+ rpb_percpu = (struct rpb_percpu *)
+ ROUNDUP128(((ulong)tbb) + (sizeof(m5_tbb)));
+
+ rpb->rpb_percpu_off = (ulong)rpb_percpu - (ulong)rpb;
+
+ for (i = 0; i < m5Conf.numCPUs; i++) {
+ struct rpb_percpu *thisCPU = (struct rpb_percpu*)
+ ((ulong)rpb_percpu + percpu_size * i);
+
+ bzero((char *)thisCPU, percpu_size);
+ bcopy((char *)&m5_rpb_percpu, (char *)thisCPU,
+ sizeof(struct rpb_percpu));
+
+ thisCPU->rpb_pcb.rpb_ksp = ksp;
+ thisCPU->rpb_pcb.rpb_ptbr = PFN(first);
+
+ thisCPU->rpb_logout = KSEG_TO_PHYS(percpu_logout);
+ thisCPU->rpb_logout_len = PAGE_SIZE;
+
+ printf_lock("KSP: 0x%x PTBR 0x%x\n",
+ thisCPU->rpb_pcb.rpb_ksp, thisCPU->rpb_pcb.rpb_ptbr);
+
+ if (i) {
+ bootStrapImpure[i] = (ulong)unix_boot_alloc(1);
+ }
+ }
+
+ nextPtr = (ulong)rpb_percpu + percpu_size * m5Conf.numCPUs;
+
+ /*
+ * Console Terminal Block
+ */
+ rpb_ctb = (struct rpb_ctb *) nextPtr;
+ ctb_tt = (struct ctb_tt*) rpb_ctb;
+
+ rpb->rpb_ctb_off = ((ulong)rpb_ctb) - (ulong)rpb;
+ rpb->rpb_ctb_size = sizeof(struct rpb_ctb);
+
+ bzero((char *)rpb_ctb, sizeof(struct ctb_tt));
+
+ rpb_ctb->rpb_type = CONS_DZ;
+ rpb_ctb->rpb_length = sizeof(ctb_tt) - sizeof(rpb_ctb);
+
+ /*
+ * uart initizliation
+ */
+ ctb_tt->ctb_csr = 0;
+ ctb_tt->ctb_tivec = 0x6c0; /* matches tlaser pal code */
+ ctb_tt->ctb_rivec = 0x680; /* matches tlaser pal code */
+ ctb_tt->ctb_baud = 9600;
+ ctb_tt->ctb_put_sts = 0;
+ ctb_tt->ctb_get_sts = 0;
+
+ rpb_crb = (struct rpb_crb *) (((ulong)rpb_ctb) + sizeof(struct ctb_tt));
+ rpb->rpb_crb_off = ((ulong)rpb_crb) - (ulong)rpb;
+
+ bzero((char *)rpb_crb, sizeof(struct rpb_crb));
+
+ /*
+ * console callback stuff (m5)
+ */
+ rpb_crb->rpb_num = 1;
+ rpb_crb->rpb_mapped_pages = HWRPB_PAGES;
+ rpb_crb->rpb_map[0].rpb_virt = 0x10000000;
+ rpb_crb->rpb_map[0].rpb_phys = KSEG_TO_PHYS(((ulong)rpb) & ~0x1fff);
+ rpb_crb->rpb_map[0].rpb_pgcount = HWRPB_PAGES;
-#ifdef original__xxm
- if (unixLoadKernel(AOUT_LOAD_ADDR, argv[1]) == -1) return;
- aoutfixup(AOUT_LOAD_ADDR);
-#else
- /* aoutfixup(simosConf.kernelFileHdr); */
-#endif
-#if 0
- bss = aout_bss_addr;
-
- kern_first_page = (KSEG_TO_PHYS(aout_text_start) / 8192);
- kernel_end = ksp_top = ROUNDUP8K(aout_bss_addr + aout_bss_size);
- bootadr = aout_entry;
-#endif
-
- kern_first_page = (KSEG_TO_PHYS(simosConf.kernStart)/8192);
- kernel_end = ksp_top = ROUNDUP8K(simosConf.kernEnd);
- bootadr = simosConf.entryPoint;
-
-
- printf_lock("HWRPB 0x%x l1pt 0x%x l2pt 0x%x l3pt_rpb 0x%x l3pt_kernel 0x%x l2reserv 0x%x\n",
- rpb, first, second, third_rpb, third_kernel,reservedFixup);
- if (kernel_end - simosConf.kernStart > (0x800000*NUM_KERNEL_THIRD)) {
- printf_lock("Kernel is more than 8MB 0x%x - 0x%x = 0x%x\n",
- kernel_end, simosConf.kernStart,
- kernel_end -simosConf.kernStart );
- panic("kernel too big\n");
-
- }
- /* Map the kernel's pages into the third level of region 2 */
-
- for (ptr = simosConf.kernStart; ptr < kernel_end; ptr += 8192) {
-
- third_kernel[THIRD_XXX(ptr)] = KPTE(PFN(ptr));
- }
- /* blow 2 pages of phys mem for guards since it maintains 1-to-1 mapping */
- ksp = ksp_top + (3 * 8192);
- if (ksp - simosConf.kernStart > (0x800000*NUM_KERNEL_THIRD)) {
- printf_lock("Kernel stack pushd us over 8MB\n");
- panic("ksp too big\n");
- }
- if (THIRD_XXX((ul)ksp_top) > NUM_KERNEL_THIRD * 1024) {
- panic("increase NUM_KERNEL_THIRD, and change THIRD_XXX\n");
- }
- ptr = (ul) ksp_top;
- bzero((char *)ptr, 8192 * 2);
- third_kernel[THIRD_XXX(ptr)] = 0; /* Stack Guard Page */
- ptr += 8192;
- third_kernel[THIRD_XXX(ptr)] = KPTE(PFN(ptr)); /* Kernel Stack Pages */
- ptr += 8192;
- third_kernel[THIRD_XXX(ptr)] = KPTE(PFN(ptr));
- ptr += 8192;
- third_kernel[THIRD_XXX(ptr)] = 0; /* Stack Guard Page */
+ printf_lock("Console Callback at 0x%x, fixup at 0x%x, crb offset: 0x%x\n",
+ rpb_crb->rpb_va_disp, rpb_crb->rpb_va_fixup, rpb->rpb_crb_off);
- /* put argv into the bottom of the stack - argv starts at 1 because
- * the command thatr got us here (i.e. "unixboot) is in argv[0].
- */
- ksp -= 8; /* Back up one longword */
- ksp -= argc * sizeof(char *); /* Make room for argv */
- kargv = (char **) ksp;
- for (i = 1; i < argc; i++) { /* Copy arguments to stack */
- ksp -= ((strlen(argv[i]) + 1) + 7) & ~0x7;
- kargv[i-1] = (char *) ksp;
- strcpy(kargv[i-1], argv[i]);
- }
- kargc = i - 1;
- kargv[kargc] = NULL; /* just to be sure; doesn't seem to be used */
- ksp -= sizeof(char *); /* point above last arg for no real reason */
+ rpb_mdt = (struct _m5_rpb_mdt *)((ulong)rpb_crb + sizeof(struct rpb_crb));
+ rpb->rpb_mdt_off = (ulong)rpb_mdt - (ulong)rpb;
+ bcopy((char *)&m5_rpb_mdt, (char *)rpb_mdt, sizeof(struct _m5_rpb_mdt));
+
+
+ cl = 0;
+ rpb_mdt->rpb_cluster[cl].rpb_pfncount = kern_first_page;
+ cl++;
+
+ rpb_mdt->rpb_cluster[cl].rpb_pfn = kern_first_page;
+ rpb_mdt->rpb_cluster[cl].rpb_pfncount = mem_pages - kern_first_page;
+ rpb_mdt->rpb_cluster[cl].rpb_pfntested =
+ rpb_mdt->rpb_cluster[cl].rpb_pfncount;
+ rpb_mdt->rpb_cluster[cl].rpb_pa = KSEG_TO_PHYS(mdt_bitmap);
+ rpb_mdt->rpb_cluster[cl].rpb_va = 0x10000000 + HWRPB_PAGES * PAGE_SIZE;
+ cl++;
+
+ rpb_mdt->rpb_numcl = cl;
+
+ for (i = 0; i < cl; i++)
+ printf_lock("Memory cluster %d [%d - %d]\n", i,
+ rpb_mdt->rpb_cluster[i].rpb_pfn,
+ rpb_mdt->rpb_cluster[i].rpb_pfncount);
- free_pfn = PFN(ptr);
-
- bcopy((char *)&xxm_rpb, (char *)rpb, sizeof(struct rpb));
-
- rpb->rpb_selfref = (struct rpb *) KSEG_TO_PHYS(rpb);
- rpb->rpb_string = 0x0000004250525748;
-
- tbb = (ul *) (((char *) rpb) + ROUNDUP8(sizeof(struct rpb)));
- rpb->rpb_trans_off = (ul)tbb - (ul)rpb;
- bcopy((char *)xxm_tbb, (char *)tbb, sizeof(xxm_tbb));
-
-
- /*
- * rpb_counter. Use to determine timeouts in OS.
- * XXX must be patched after a checkpoint restore (I guess)
- */
-
- printf_lock("CPU Clock at %d MHz IntrClockFrequency=%d \n", simosConf.cpuClock,simosConf.intrClockFrequency);
- rpb->rpb_counter = simosConf.cpuClock * 1000 * 1000;
-
- /*
- * By definition, the rpb_clock is scaled by 4096 (in hz)
- */
- rpb->rpb_clock = simosConf.intrClockFrequency * 4096;
-
-
-
- /*
- * Per CPU Slots. Multiprocessor support.
- */
- {
- int i;
- int size = ROUNDUP128(sizeof(struct rpb_percpu));
-
- printf_lock("Booting with %d processor(s) \n",simosConf.numCPUs);
-
- rpb->rpb_numprocs = simosConf.numCPUs;
- rpb->rpb_slotsize = size;
- rpb_percpu = (struct rpb_percpu *)
- ROUNDUP128(((ul) tbb) +(sizeof(xxm_tbb)));
-
- rpb->rpb_percpu_off = (ul)rpb_percpu - (ul)rpb;
-
- for (i=0;i<simosConf.numCPUs;i++) {
- struct rpb_percpu *thisCPU = (struct rpb_percpu*)
- ((ul)rpb_percpu + size*i);
-
- bzero((char *)thisCPU, size);
- bcopy((char *)&xxm_rpb_percpu,
- (char *)thisCPU,
- sizeof(struct rpb_percpu));
-
- thisCPU->rpb_pcb.rpb_ksp = ksp;
- thisCPU->rpb_pcb.rpb_ptbr = PFN(first);
-
- thisCPU->rpb_logout = KSEG_TO_PHYS(percpu_logout);
- thisCPU->rpb_logout_len = 8192;
-
-/* thisCPU->rpb_pcb.rpb_ptbr = PFN(second);*/
-
- printf_lock("KSP: 0x%x PTBR 0x%x\n", thisCPU->rpb_pcb.rpb_ksp, thisCPU->rpb_pcb.rpb_ptbr);
-
- if (i) {
- bootStrapImpure[i] = (ul)unix_boot_alloc(1);
- }
-
- }
-
- nextPtr = (ul)rpb_percpu + size*simosConf.numCPUs;
- }
-
- /*
- * Console Terminal Block
- */
-
-
- rpb_ctb = (struct rpb_ctb *) nextPtr;
- ctb_tt = (struct ctb_tt*) rpb_ctb;
-
- rpb->rpb_ctb_off = ((ul)rpb_ctb) - (ul)rpb;
- rpb->rpb_ctb_size = sizeof(struct rpb_ctb);
-
- bzero((char *)rpb_ctb, sizeof(struct ctb_tt));
-
-#ifdef original_xxm
- if (tga_slot == -1)
- rpb_ctb->rpb_type = CONS_DZ;
- else {
- rpb_ctb->rpb_type = CONS_GRPH;
- rpb_ctb->rpb_unit = (SLOTINFO_PCI << 16) | (0 << 8) | tga_slot;
- }
-#else
- rpb_ctb->rpb_type = CONS_DZ;
-#endif
-
- rpb_ctb->rpb_length = sizeof(ctb_tt)-sizeof(rpb_ctb);
-
- /*
- * uart initizliation
- */
- ctb_tt->ctb_csr = 0;
- ctb_tt->ctb_tivec = 0x6c0; /* matches tlaser pal code */
- ctb_tt->ctb_rivec = 0x680; /* matches tlaser pal code */
- ctb_tt->ctb_baud = 9600;
- ctb_tt->ctb_put_sts = 0;
- ctb_tt->ctb_get_sts = 0;
-
-
- rpb_crb = (struct rpb_crb *) (((ul)rpb_ctb) + sizeof(struct ctb_tt));
- rpb->rpb_crb_off = ((ul)rpb_crb) - (ul)rpb;
-
- bzero((char *)rpb_crb, sizeof(struct rpb_crb));
- /*
- * console callback stuff (simos)
- */
-
- rpb_crb->rpb_num = 1;
- rpb_crb->rpb_mapped_pages = HWRPB_PAGES;
- rpb_crb->rpb_map[0].rpb_virt = 0x10000000;
- rpb_crb->rpb_map[0].rpb_phys = KSEG_TO_PHYS(((ul)rpb) & ~0x1fff);
- rpb_crb->rpb_map[0].rpb_pgcount = HWRPB_PAGES;
-
-
- printf_lock("Console Callback at 0x%x, fixup at 0x%x, crb offset: 0x%x\n",
- rpb_crb->rpb_va_disp,
- rpb_crb->rpb_va_fixup,
- rpb->rpb_crb_off);
-
- rpb_mdt = (struct _xxm_rpb_mdt *) (((ul)rpb_crb) + sizeof(struct rpb_crb));
- rpb->rpb_mdt_off = (ul)rpb_mdt - (ul)rpb;
- bcopy((char *)&xxm_rpb_mdt, (char *)rpb_mdt, sizeof(struct _xxm_rpb_mdt));
-
-
- cl = 0;
-#ifdef undef
- /* Until Digital Unix can handle it, account all pages below the kernel
- * as "console" memory. */
- rpb_mdt->rpb_cluster[cl].rpb_pfncount = cons_pages;
-#endif
- rpb_mdt->rpb_cluster[cl].rpb_pfncount = kern_first_page;
- cl++;
-
- rpb_mdt->rpb_cluster[cl].rpb_pfn = kern_first_page;
- rpb_mdt->rpb_cluster[cl].rpb_pfncount = mem_pages - kern_first_page;
- rpb_mdt->rpb_cluster[cl].rpb_pfntested=rpb_mdt->rpb_cluster[cl].rpb_pfncount;
- rpb_mdt->rpb_cluster[cl].rpb_pa = KSEG_TO_PHYS(mdt_bitmap);
- rpb_mdt->rpb_cluster[cl].rpb_va = 0x10000000 + HWRPB_PAGES * 8192;
- cl++;
-
-#ifdef undef
- /* The stupid Unix kernel needs to have all mdt clusters in ascending
- * order, and the last cluster is used to compute the top of memory.
- * It can't make use of memory between the console and the kernel.
- */
- rpb_mdt->rpb_cluster[cl].rpb_pfn = cons_pages;
- rpb_mdt->rpb_cluster[cl].rpb_pfncount = kern_first_page - cons_pages;
- rpb_mdt->rpb_cluster[cl].rpb_pfntested=rpb_mdt->rpb_cluster[cl].rpb_pfncount;
- rpb_mdt->rpb_cluster[cl].rpb_pa = KSEG_TO_PHYS(mdt_bitmap);
- rpb_mdt->rpb_cluster[cl].rpb_va = 0x10000000 + HWRPB_PAGES * 8192;
- cl++;
-#endif
-
- rpb_mdt->rpb_numcl = cl;
-
- for (i = 0; i < cl; i++)
- printf_lock("Memory cluster %d [%d - %d]\n", i, rpb_mdt->rpb_cluster[i].rpb_pfn, rpb_mdt->rpb_cluster[i].rpb_pfncount);
-
-
-
- /* Checksum the rpb for good luck */
- sum = 0;
- lp1 = (long *)&rpb_mdt->rpb_impaddr;
- lp2 = (long *)&rpb_mdt->rpb_cluster[cl];
- while (lp1 < lp2) sum += *lp1++;
- rpb_mdt->rpb_checksum = sum;
-
- /* XXX should checksum the cluster descriptors */
-
- bzero((char *)mdt_bitmap, MDT_BITMAP_PAGES * 8192);
- for (i = 0; i < mem_pages/8; i++) ((unsigned char *)mdt_bitmap)[i] = 0xff;
-
- printf_lock("Initalizing mdt_bitmap addr 0x%x mem_pages %x \n",
- (long)mdt_bitmap,(long)mem_pages);
-
- xxm_rpb.rpb_config_off = 0;
- xxm_rpb.rpb_fru_off = 0;
-
- rpb_dsr = (struct rpb_dsr *) (((ul)rpb_mdt) + sizeof(struct _xxm_rpb_mdt));
- rpb->rpb_dsr_off = ((ul)rpb_dsr) - (ul)rpb;
- bzero((char *)rpb_dsr, sizeof(struct rpb_dsr));
- rpb_dsr->rpb_smm = 1578; /* Official XXM SMM number as per SRM */
- rpb_dsr->rpb_smm = 1089; /* Official Alcor SMM number as per SRM */
-
- rpb_lurt = (int *) ROUNDUP8(((ul)rpb_dsr) + sizeof(struct rpb_dsr));
- rpb_dsr->rpb_lurt_off = ((ul) rpb_lurt) - (ul) rpb_dsr;
- bcopy((char *)xxm_lurt, (char *)rpb_lurt, sizeof(xxm_lurt));
-
- rpb_name = (char *) ROUNDUP8(((ul)rpb_lurt) + sizeof(xxm_lurt));
- rpb_dsr->rpb_sysname_off = ((ul) rpb_name) - (ul) rpb_dsr;
+ /* Checksum the rpb for good luck */
+ sum = 0;
+ lp1 = (long *)&rpb_mdt->rpb_impaddr;
+ lp2 = (long *)&rpb_mdt->rpb_cluster[cl];
+ while (lp1 < lp2) sum += *lp1++;
+ rpb_mdt->rpb_checksum = sum;
+
+ /* XXX should checksum the cluster descriptors */
+ bzero((char *)mdt_bitmap, MDT_BITMAP_PAGES * PAGE_SIZE);
+ for (i = 0; i < mem_pages/8; i++)
+ ((unsigned char *)mdt_bitmap)[i] = 0xff;
+
+ printf_lock("Initalizing mdt_bitmap addr 0x%x mem_pages %x \n",
+ (long)mdt_bitmap,(long)mem_pages);
+
+ m5_rpb.rpb_config_off = 0;
+ m5_rpb.rpb_fru_off = 0;
+
+ rpb_dsr = (struct rpb_dsr *)((ulong)rpb_mdt + sizeof(struct _m5_rpb_mdt));
+ rpb->rpb_dsr_off = (ulong)rpb_dsr - (ulong)rpb;
+ bzero((char *)rpb_dsr, sizeof(struct rpb_dsr));
+ rpb_dsr->rpb_smm = 1578; /* Official XXM SMM number as per SRM */
+ rpb_dsr->rpb_smm = 1089; /* Official Alcor SMM number as per SRM */
+
+ rpb_lurt = (int *) ROUNDUP8((ulong)rpb_dsr + sizeof(struct rpb_dsr));
+ rpb_dsr->rpb_lurt_off = ((ulong) rpb_lurt) - (ulong) rpb_dsr;
+ bcopy((char *)m5_lurt, (char *)rpb_lurt, sizeof(m5_lurt));
+
+ rpb_name = (char *) ROUNDUP8(((ulong)rpb_lurt) + sizeof(m5_lurt));
+ rpb_dsr->rpb_sysname_off = ((ulong) rpb_name) - (ulong) rpb_dsr;
#define THENAME " M5/Alpha "
- sum = sizeof(THENAME);
- bcopy(THENAME, rpb_name, sum);
- *(ul *)rpb_name = sizeof(THENAME); /* put in length field */
-
- /* calculate size of rpb */
- rpb->rpb_size = ((ul) &rpb_name[sum]) - (ul)rpb;
-
- if (rpb->rpb_size > 8192*HWRPB_PAGES) {
- panic("HWRPB_PAGES=%d too small for HWRPB !!! \n");
- }
-
-
- {
- ul *ptr = (ul*)((char*)rpb_dsr + sizeof(struct rpb_dsr ));
- rpb_crb->rpb_pa_disp = KSEG_TO_PHYS(ptr);
- rpb_crb->rpb_va_disp = 0x10000000 + (((ul)ptr - (ul)rpb) & (0x2000*HWRPB_PAGES-1));
- printf_lock("ConsoleDispatch at virt %x phys %x val %x\n",
- rpb_crb->rpb_va_disp,
- rpb_crb->rpb_pa_disp,
- consoleCallback);
- *ptr++ = 0;
- *ptr++ = (ul) consoleCallback;
- rpb_crb->rpb_pa_fixup = KSEG_TO_PHYS(ptr);
- rpb_crb->rpb_va_fixup = 0x10000000 + (((ul)ptr - (ul)rpb) & (0x2000*HWRPB_PAGES-1));
- *ptr++ = 0;
-
- *ptr++ = (ul) consoleFixup;
- }
-
-
- /* Checksum the rpb for good luck */
- sum = 0;
- lp1 = (long *)rpb;
- lp2 = &rpb->rpb_checksum;
- while (lp1 < lp2)
- sum += *lp1++;
- *lp2 = sum;
-
+ sum = sizeof(THENAME);
+ bcopy(THENAME, rpb_name, sum);
+ *(ulong *)rpb_name = sizeof(THENAME); /* put in length field */
+
+ /* calculate size of rpb */
+ rpb->rpb_size = ((ulong) &rpb_name[sum]) - (ulong)rpb;
+
+ if (rpb->rpb_size > PAGE_SIZE * HWRPB_PAGES) {
+ panic("HWRPB_PAGES=%d too small for HWRPB !!! \n");
+ }
+
+ ulong *rpbptr = (ulong*)((char*)rpb_dsr + sizeof(struct rpb_dsr));
+ rpb_crb->rpb_pa_disp = KSEG_TO_PHYS(rpbptr);
+ rpb_crb->rpb_va_disp = 0x10000000 +
+ (((ulong)rpbptr - (ulong)rpb) & (0x2000 * HWRPB_PAGES - 1));
+ printf_lock("ConsoleDispatch at virt %x phys %x val %x\n",
+ rpb_crb->rpb_va_disp, rpb_crb->rpb_pa_disp, consoleCallback);
+ *rpbptr++ = 0;
+ *rpbptr++ = (ulong) consoleCallback;
+ rpb_crb->rpb_pa_fixup = KSEG_TO_PHYS(rpbptr);
+ rpb_crb->rpb_va_fixup = 0x10000000 +
+ (((ulong)rpbptr - (ulong)rpb) & (0x2000 * HWRPB_PAGES - 1));
+ *rpbptr++ = 0;
+
+ *rpbptr++ = (ulong) consoleFixup;
+
+ /* Checksum the rpb for good luck */
+ sum = 0;
+ lp1 = (long *)rpb;
+ lp2 = &rpb->rpb_checksum;
+ while (lp1 < lp2)
+ sum += *lp1++;
+ *lp2 = sum;
/*
* MP bootstrap
*/
-
- {
- int i;
- for (i=1;i<simosConf.numCPUs;i++) {
- volatile struct AlphaAccess *k1Conf = (volatile struct AlphaAccess *)
- (ALPHA_ACCESS_BASE);
- printf_lock("Bootstraping CPU %d with sp=0x%x \n",
- i,bootStrapImpure[i]);
+ for (i = 1; i < m5Conf.numCPUs; i++) {
+ volatile struct AlphaAccess *k1Conf;
+ k1Conf = (volatile struct AlphaAccess *)(ALPHA_ACCESS_BASE);
+ printf_lock("Bootstraping CPU %d with sp=0x%x\n",
+ i, bootStrapImpure[i]);
k1Conf->bootStrapImpure = bootStrapImpure[i];
k1Conf->bootStrapCPU = i;
- }
- }
-
- /*
- * Make sure that we are not stepping on the kernel
- */
- if ((ul)unix_boot_mem >= (ul)simosConf.kernStart) {
- panic("CONSOLE: too much memory. Smashing kernel \n");
- } else {
- printf_lock("unix_boot_mem ends at %x \n",unix_boot_mem);
- }
-
-
-#ifdef undef
-#define CSERVE_K_JTOKERN 0x18
- cServe(bootadr, (ul) rpb_percpu, CSERVE_K_JTOKERN, free_pfn);
-#endif
-
- if (go) JToKern(bootadr, rpb_percpu, free_pfn, kargc, kargv, NULL);
-}
-
-
-#if 0
-aoutfixup(char *p)
-{
- int i;
- unsigned long rem, len, off, dst;
-
-
- struct new_aouthdr *ao = (struct new_aouthdr *) &p[NEW_FILHSZ];
-#if 0
- struct scnhdr *s = (struct scnhdr *) &p[FILHSZ + AOUTHSZ];
- struct scnhdr *t, *d, *b;
- printf("aoutfixup: %d sections \n",fh->f_nscns);
-#endif
-
-
- aout_text_start = ((ul)ao->text_start_hi<<32) + ao->text_start;
- aout_data_addr = ((ul)ao->data_start_hi<<32) + ao->data_start;
- aout_bss_addr = ((ul)ao->bss_start_hi<<32) + ao->bss_start;
- aout_bss_size = ((ul)ao->bsize_hi<<32) + ao->bsize;
- aout_entry = ((ul)ao->entry_hi<<32) + ao->entry;
-
- printf("_text 0x%16x %8d @ %08d\n", aout_text_start, ao->tsize,0 /* t->s_scnptr*/);
- printf("_data 0x%16x %8d @ %08d\n", aout_data_addr, ao->dsize,0/* d->s_scnptr*/);
- printf("_bss 0x%16x %8d\n", aout_bss_addr, ao->bsize);
- printf("entry 0x%16x\n", aout_entry);
-#if 0
- for (i = 0; i < fh->f_nscns; i++) {
- printf("section %d %s \n",i,s[i].s_name);
- if (!strcmp(s[i].s_name, ".text")) t = &s[i];
- else if (!strcmp(s[i].s_name, ".data")) d = &s[i];
- else if (!strcmp(s[i].s_name, ".bss")) b = &s[i];
- }
- bcopy(&p[t->s_scnptr], (char *)ao->text_start, ao->tsize);
- bcopy(&p[d->s_scnptr], (char *)ao->data_start, ao->dsize);
-#endif
+ }
+
+ /*
+ * Make sure that we are not stepping on the kernel
+ */
+ if ((ulong)unix_boot_mem >= (ulong)m5Conf.kernStart) {
+ panic("CONSOLE: too much memory. Smashing kernel\n");
+ } else {
+ printf_lock("unix_boot_mem ends at %x \n", unix_boot_mem);
+ }
+
+ if (go)
+ JToKern((char *)bootadr, (ulong)rpb_percpu, free_pfn, kargc, kargv,
+ NULL);
}
-#endif
-extern ui palJToKern[];
-JToKern(bootadr, rpb_percpu, free_pfn, k_argc, k_argv, envp)
-char * bootadr;
-ul rpb_percpu;
-ul free_pfn;
-ul k_argc;
-char **k_argv;
-char **envp;
+void
+JToKern(char *bootadr, ulong rpb_percpu, ulong free_pfn, ulong k_argc,
+ char **k_argv, char **envp)
{
- struct _kernel_params *kernel_params = (struct _kernel_params *) KSEG;
- int i;
-
- printf_lock("k_argc = %d ", k_argc);
- for (i = 0; i < k_argc; i++) {
- printf_lock("'%s' ", k_argv[i]);
- }
- printf_lock("\n");
-
-/* rpb_percpu |= 0xfffffc0000000000;*/
- kernel_params->bootadr = bootadr;
- kernel_params->rpb_percpu = KSEG_TO_PHYS(rpb_percpu);
- kernel_params->free_pfn = free_pfn;
- kernel_params->argc = k_argc;
- kernel_params->argv = (ul)k_argv;
- kernel_params->envp = (ul)envp;
- printf_lock("jumping to kernel at 0x%x, (PCBB 0x%x pfn %d)\n", bootadr, rpb_percpu, free_pfn);
- jToPal(KSEG_TO_PHYS((ul)palJToKern));
- printf_lock("returned from jToPal. Looping\n");
- while(1) continue;
+ extern ulong palJToKern[];
+
+ struct _kernel_params *kernel_params = (struct _kernel_params *) KSEG;
+ int i;
+
+ printf_lock("k_argc = %d ", k_argc);
+ for (i = 0; i < k_argc; i++) {
+ printf_lock("'%s' ", k_argv[i]);
+ }
+ printf_lock("\n");
+
+ kernel_params->bootadr = bootadr;
+ kernel_params->rpb_percpu = KSEG_TO_PHYS(rpb_percpu);
+ kernel_params->free_pfn = free_pfn;
+ kernel_params->argc = k_argc;
+ kernel_params->argv = (ulong)k_argv;
+ kernel_params->envp = (ulong)envp;
+ printf_lock("jumping to kernel at 0x%x, (PCBB 0x%x pfn %d)\n",
+ bootadr, rpb_percpu, free_pfn);
+ JToPal(KSEG_TO_PHYS(palJToKern));
+ printf_lock("returned from JToPal. Looping\n");
+ while (1)
+ continue;
}
-
-void jToPal(ul bootadr)
+void
+JToPal(ulong bootadr)
{
- cServe(bootadr, 0, CSERVE_K_JTOPAL);
+ cServe(bootadr, 0, CSERVE_K_JTOPAL);
-/*
- * Make sure that floating point is enabled incase
- * it was disabled by the user program.
- */
- wrfen(1);
+ /*
+ * Make sure that floating point is enabled incase
+ * it was disabled by the user program.
+ */
+ wrfen(1);
}
-
-int strcpy(char *dst, char *src)
+int
+strcpy(char *dst, char *src)
{
- int i=0;
- while(*src) {
- *dst++ = *src++;
- i++;
- }
- return i;
+ int i = 0;
+ while (*src) {
+ *dst++ = *src++;
+ i++;
+ }
+ return i;
}
-
-
-
-/* *****************************************
+/*
* Console I/O
- * ******************************************/
+ *
+ */
int numOpenDevices = 11;
struct {
- char name[128];
+ char name[128];
} deviceState[32];
#define BOOTDEVICE_NAME "SCSI 1 0 0 1 100 0"
void
DeviceOperation(long op, long channel, long count, long address, long block)
{
- struct AlphaAccess *k1Conf = (struct AlphaAccess *)
- (ALPHA_ACCESS_BASE);
-
- long pAddr;
-
-#if 0
- printf("Console::DeviceRead count=0x%x address=0x%x block=0x%x\n",
- count,address,block);
-#endif
-
- if (strcmp(deviceState[channel].name, BOOTDEVICE_NAME )) {
- panic("DeviceRead: only implemented for root disk \n");
- }
- pAddr = KSEG_TO_PHYS(address);
- if (pAddr + count > simosConf.mem_size) {
- panic("DeviceRead: request out of range \n");
- }
-
- k1Conf->diskCount = count;
- k1Conf->diskPAddr = pAddr;
- k1Conf->diskBlock = block;
- k1Conf->diskOperation = op; /* launch */
+ struct AlphaAccess *k1Conf = (struct AlphaAccess *)(ALPHA_ACCESS_BASE);
+ long pAddr;
+
+ if (strcmp(deviceState[channel].name, BOOTDEVICE_NAME )) {
+ panic("DeviceRead: only implemented for root disk \n");
+ }
+ pAddr = KSEG_TO_PHYS(address);
+ if (pAddr + count > m5Conf.mem_size) {
+ panic("DeviceRead: request out of range \n");
+ }
+
+ k1Conf->diskCount = count;
+ k1Conf->diskPAddr = pAddr;
+ k1Conf->diskBlock = block;
+ k1Conf->diskOperation = op; /* launch */
}
-
-
-/* *************************************************************************
- * SimoS Console callbacks
- * **************************************************/
+/*
+ * M5 Console callbacks
+ *
+ */
/* AXP manual 2-31 */
#define CONSCB_GETC 0x1
#define MAX_ENVLEN 32
-char env_auto_action[MAX_ENVLEN] = "BOOT";
-char env_boot_dev[MAX_ENVLEN] = "";
-char env_bootdef_dev[MAX_ENVLEN] = "";
-char env_booted_dev[MAX_ENVLEN] = BOOTDEVICE_NAME;
-char env_boot_file[MAX_ENVLEN] = "";
-char env_booted_file[MAX_ENVLEN] = "";
-char env_boot_osflags[MAX_ENVLEN] = "";
-char env_booted_osflags[MAX_ENVLEN] = "";
-char env_boot_reset[MAX_ENVLEN] = "";
-char env_dump_dev[MAX_ENVLEN] = "";
-char env_enable_audit[MAX_ENVLEN] = "";
-char env_license[MAX_ENVLEN] = "";
-char env_char_set[MAX_ENVLEN] = "";
-char env_language[MAX_ENVLEN] = "";
-char env_tty_dev[MAX_ENVLEN] = "0";
-char env_scsiid[MAX_ENVLEN] = "";
-char env_scsifast[MAX_ENVLEN] = "";
-char env_com1_baud[MAX_ENVLEN] = "";
-char env_com1_modem[MAX_ENVLEN] = "";
-char env_com1_flow[MAX_ENVLEN] = "";
-char env_com1_misc[MAX_ENVLEN] = "";
-char env_com2_baud[MAX_ENVLEN] = "";
-char env_com2_modem[MAX_ENVLEN] = "";
-char env_com2_flow[MAX_ENVLEN] = "";
-char env_com2_misc[MAX_ENVLEN] = "";
-char env_password[MAX_ENVLEN] = "";
-char env_secure[MAX_ENVLEN] = "";
-char env_logfail[MAX_ENVLEN] = "";
-char env_srm2dev_id[MAX_ENVLEN] = "";
+char env_auto_action[MAX_ENVLEN] = "BOOT";
+char env_boot_dev[MAX_ENVLEN] = "";
+char env_bootdef_dev[MAX_ENVLEN] = "";
+char env_booted_dev[MAX_ENVLEN] = BOOTDEVICE_NAME;
+char env_boot_file[MAX_ENVLEN] = "";
+char env_booted_file[MAX_ENVLEN] = "";
+char env_boot_osflags[MAX_ENVLEN] = "";
+char env_booted_osflags[MAX_ENVLEN] = "";
+char env_boot_reset[MAX_ENVLEN] = "";
+char env_dump_dev[MAX_ENVLEN] = "";
+char env_enable_audit[MAX_ENVLEN] = "";
+char env_license[MAX_ENVLEN] = "";
+char env_char_set[MAX_ENVLEN] = "";
+char env_language[MAX_ENVLEN] = "";
+char env_tty_dev[MAX_ENVLEN] = "0";
+char env_scsiid[MAX_ENVLEN] = "";
+char env_scsifast[MAX_ENVLEN] = "";
+char env_com1_baud[MAX_ENVLEN] = "";
+char env_com1_modem[MAX_ENVLEN] = "";
+char env_com1_flow[MAX_ENVLEN] = "";
+char env_com1_misc[MAX_ENVLEN] = "";
+char env_com2_baud[MAX_ENVLEN] = "";
+char env_com2_modem[MAX_ENVLEN] = "";
+char env_com2_flow[MAX_ENVLEN] = "";
+char env_com2_misc[MAX_ENVLEN] = "";
+char env_password[MAX_ENVLEN] = "";
+char env_secure[MAX_ENVLEN] = "";
+char env_logfail[MAX_ENVLEN] = "";
+char env_srm2dev_id[MAX_ENVLEN] = "";
#define MAX_ENV_INDEX 100
-char *env_ptr[MAX_ENV_INDEX] =
-{
+char *envptr[MAX_ENV_INDEX] = {
0, /* 0x00 */
env_auto_action, /* 0x01 */
env_boot_dev, /* 0x02 */
long
CallBackDispatcher(long a0, long a1, long a2, long a3, long a4)
{
- long i;
- switch (a0) {
- case CONSCB_GETC:
- return GetChar();
-
- case CONSCB_PUTS:
- for(i = 0; i < a3; i++)
- PutChar(*((char *)a2+i));
- return a3;
-
- case CONSCB_GETENV:
- if (a1 >= 0 && a1 < MAX_ENV_INDEX && env_ptr[a1] != 0 && *env_ptr[a1]) {
- i = strcpy((char*)a2, env_ptr[a1]);
- } else {
- strcpy((char*)a2, "");
- i = (long)0xc000000000000000;
- if (a1 >= 0 && a1 < MAX_ENV_INDEX)
- printf_lock("GETENV unsupported option %d (0x%x)\n", a1, a1);
- else
- printf_lock("GETENV unsupported option %s\n", a1);
- }
-
- if (i > a3)
- panic("CONSCB_GETENV overwrote buffer\n");
- return i;
-
- case CONSCB_OPEN:
- bcopy((char*)a1,deviceState[numOpenDevices].name,a2);
- deviceState[numOpenDevices].name[a2] = '\0';
- printf_lock("CONSOLE OPEN : %s --> success \n",
- deviceState[numOpenDevices].name);
- return numOpenDevices++;
-
- case CONSCB_READ:
- DeviceOperation(a0,a1,a2,a3,a4);
- break;
-
- case CONSCB_CLOSE:
- break;
- case CONSCB_OPEN_CONSOLE:
- printf_lock("CONSOLE OPEN\n");
- return 0; /* success */
- break; /* not rearched */
- case CONSCB_CLOSE_CONSOLE:
- printf_lock("CONSOLE CLOSE\n");
- return 0; /* success */
- break; /* not reached */
-
- default:
- panic("cher (%x,%x,%x,%x)\n", a0, a1, a2, a3);
- }
-
- return 0;
+ long i;
+ switch (a0) {
+ case CONSCB_GETC:
+ return GetChar();
+
+ case CONSCB_PUTS:
+ for (i = 0; i < a3; i++)
+ PutChar(*((char *)a2 + i));
+ return a3;
+
+ case CONSCB_GETENV:
+ if (a1 >= 0 && a1 < MAX_ENV_INDEX && envptr[a1] != 0 && *envptr[a1]) {
+ i = strcpy((char*)a2, envptr[a1]);
+ } else {
+ strcpy((char*)a2, "");
+ i = (long)0xc000000000000000;
+ if (a1 >= 0 && a1 < MAX_ENV_INDEX)
+ printf_lock("GETENV unsupported option %d (0x%x)\n", a1, a1);
+ else
+ printf_lock("GETENV unsupported option %s\n", a1);
+ }
+
+ if (i > a3)
+ panic("CONSCB_GETENV overwrote buffer\n");
+ return i;
+
+ case CONSCB_OPEN:
+ bcopy((char*)a1, deviceState[numOpenDevices].name, a2);
+ deviceState[numOpenDevices].name[a2] = '\0';
+ printf_lock("CONSOLE OPEN : %s --> success \n",
+ deviceState[numOpenDevices].name);
+ return numOpenDevices++;
+
+ case CONSCB_READ:
+ DeviceOperation(a0, a1, a2, a3, a4);
+ break;
+
+ case CONSCB_CLOSE:
+ break;
+
+ case CONSCB_OPEN_CONSOLE:
+ printf_lock("CONSOLE OPEN\n");
+ return 0; /* success */
+ break; /* not reached */
+
+ case CONSCB_CLOSE_CONSOLE:
+ printf_lock("CONSOLE CLOSE\n");
+ return 0; /* success */
+ break; /* not reached */
+
+ default:
+ panic("CallBackDispatcher(%x,%x,%x,%x,%x)\n", a0, a1, a2, a3, a4);
+ }
+
+ return 0;
}
-long CallBackFixup(int a0, int a1, int a2)
+long
+CallBackFixup(int a0, int a1, int a2)
{
- long temp;
- /* Linux uses r8 for the current pointer (pointer to data structure
- contating info about currently running process). It is set when the
- kernel starts and is expected to remain there... Problem is that the
- unlike the kernel, the console does not prevent the assembler from
- using r8. So here is a work around. So far this has only been a problem
- in CallBackFixup() but any other call back functions could cause a problem
- at some point */
-
- /* save off the current pointer to a temp variable */
- asm("bis $8, $31, %0" : "=r" (temp));
-
- /* call original code */
- printf_lock("CallbackFixup %x %x, t7=%x\n",a0,a1,temp);
-
- /* restore the current pointer */
- asm("bis %0, $31, $8" : : "r" (temp) : "$8");
-
-#if 0
- if (first[FIRST(a1)]==0) {
- first[FIRST(a1)] = KPTE(PFN(reservedFixup));
- } else {
- panic("CallBakcfixup\n");
- }
- second[SECOND(a1)] = KPTE(PFN(third_rpb)); /* Region 0 */
- printf("Fixup: FISRT(a1)=0x%x SECOND(a1)=0x%x THIRD(a1)=0x%x\n",
- FIRST(a1),SECOND(a1),THIRD(a1));
-
-#endif
- return 0;
+ long temp;
+ /*
+ * Linux uses r8 for the current pointer (pointer to data
+ * structure contating info about currently running process). It
+ * is set when the kernel starts and is expected to remain
+ * there... Problem is that the unlike the kernel, the console
+ * does not prevent the assembler from using r8. So here is a work
+ * around. So far this has only been a problem in CallBackFixup()
+ * but any other call back functions couldd cause a problem at
+ * some point
+ */
+
+ /* save off the current pointer to a temp variable */
+ asm("bis $8, $31, %0" : "=r" (temp));
+
+ /* call original code */
+ printf_lock("CallbackFixup %x %x, t7=%x\n", a0, a1, temp);
+
+ /* restore the current pointer */
+ asm("bis %0, $31, $8" : : "r" (temp) : "$8");
+
+ return 0;
}
-
-
-
-
-void SlaveCmd(int cpu, struct rpb_percpu *my_rpb)
+void
+SlaveCmd(int cpu, struct rpb_percpu *my_rpb)
{
-/* extern void palJToSlave[]; */
- extern unsigned int palJToSlave[];
+ extern ulong palJToSlave[];
- printf_lock("Slave CPU %d console command %s", cpu,my_rpb->rpb_iccb.iccb_rxbuf);
+ printf_lock("Slave CPU %d console command %s", cpu,
+ my_rpb->rpb_iccb.iccb_rxbuf);
- my_rpb->rpb_state |= STATE_BIP;
- my_rpb->rpb_state &= ~STATE_RC;
+ my_rpb->rpb_state |= STATE_BIP;
+ my_rpb->rpb_state &= ~STATE_RC;
- printf_lock("SlaveCmd: restart %x %x vptb %x my_rpb %x my_rpb_phys %x\n",
- rpb->rpb_restart,
- rpb->rpb_restart_pv,
- rpb->rpb_vptb, my_rpb,
- KSEG_TO_PHYS(my_rpb));
+ printf_lock("SlaveCmd: restart %x %x vptb %x my_rpb %x my_rpb_phys %x\n",
+ rpb->rpb_restart, rpb->rpb_restart_pv, rpb->rpb_vptb, my_rpb,
+ KSEG_TO_PHYS(my_rpb));
- cServe(KSEG_TO_PHYS((ul)palJToSlave),
- (ul)rpb->rpb_restart,
- CSERVE_K_JTOPAL,
- rpb->rpb_restart_pv,
- rpb->rpb_vptb,
- KSEG_TO_PHYS(my_rpb));
+ cServe(KSEG_TO_PHYS(palJToSlave), (ulong)rpb->rpb_restart,
+ CSERVE_K_JTOPAL, rpb->rpb_restart_pv, rpb->rpb_vptb,
+ KSEG_TO_PHYS(my_rpb));
- panic("SlaveCmd returned \n");
+ panic("SlaveCmd returned \n");
}
-void SlaveLoop( int cpu)
+void
+SlaveLoop(int cpu)
{
- int size = ROUNDUP128(sizeof(struct rpb_percpu));
- struct rpb_percpu *my_rpb = (struct rpb_percpu*)
- ((ul)rpb_percpu + size*cpu);
-
- if (cpu==0) {
- panic("CPUÂ 0 entering slaveLoop. Reenetering the console. HOSED \n");
- } else {
- printf_lock("Entering slaveloop for cpu %d my_rpb=%x \n",cpu,my_rpb);
- }
-
- // swap the processors context to the one in the
- // rpb_percpu struct very carefully (i.e. no stack usage)
- // so that linux knows which processor ends up in __smp_callin
- // and we don't trash any data is the process
- SlaveSpin(cpu,my_rpb,&my_rpb->rpb_iccb.iccb_rxlen);
+ int size = ROUNDUP128(sizeof(struct rpb_percpu));
+ struct rpb_percpu *my_rpb = (struct rpb_percpu*)
+ ((ulong)rpb_percpu + size * cpu);
+
+ if (cpu == 0) {
+ panic("CPUÂ 0 entering slaveLoop. Reenetering the console. HOSED\n");
+ } else {
+ printf_lock("Entering slaveloop for cpu %d my_rpb=%x\n", cpu, my_rpb);
+ }
+
+ // swap the processors context to the one in the
+ // rpb_percpu struct very carefully (i.e. no stack usage)
+ // so that linux knows which processor ends up in __smp_callin
+ // and we don't trash any data is the process
+ SlaveSpin(cpu, my_rpb, &my_rpb->rpb_iccb.iccb_rxlen);
}
/*
-Copyright (c) 2003, 2004
-The Regents of The University of Michigan
-All Rights Reserved
-
-This code is part of the M5 simulator, developed by Nathan Binkert,
-Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
-from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
-Schultz.
-
-Permission is granted to use, copy, create derivative works and
-redistribute this software and such derivative works for any purpose,
-so long as the copyright notice above, this grant of permission, and
-the disclaimer below appear in all copies made; and so long as the
-name of The University of Michigan is not used in any advertising or
-publicity pertaining to the use or distribution of this software
-without specific, written prior authorization.
-
-THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
-WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
-IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
-THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
-INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
-DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
-WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
-ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-*/
+ * Copyright (c) 2003, 2004
+ * The Regents of The University of Michigan
+ * All Rights Reserved
+ *
+ * This code is part of the M5 simulator, developed by Nathan Binkert,
+ * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+ * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
+ * Schultz.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * redistribute this software and such derivative works for any purpose,
+ * so long as the copyright notice above, this grant of permission, and
+ * the disclaimer below appear in all copies made; and so long as the
+ * name of The University of Michigan is not used in any advertising or
+ * publicity pertaining to the use or distribution of this software
+ * without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
+ * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
+ * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
+ * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
+ * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ */
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-/* taken from ebfw/rom/dbmentry.s */
-
-#define EB164
-/*#ifndef LINT
-.data
-.asciiz "$Id: dbmentry.s,v 1.1.1.1 1997/10/30 23:27:12 verghese Exp $"
-.text
-#endif
-*/
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
/*
* Debug Monitor Entry code
*/
-
-#ifndef MAKEDEPEND
-#include "ev5_impure.h"
-#include "cserve.h"
#include "fromHudsonOsf.h"
-#endif
-
-//#include "paldefs.h"
-#include "regdefs.h"
-#include "eb164.h"
-//#include "ledcodes.h"
.text
/* return address and padding to octaword align */
#define STARTFRM 16
- .globl __start
- .ent __start, 0
-__start:
+ .globl _start
+ .ent _start, 0
+_start:
_entry:
br t0, 2f # get the current PC
2: ldgp gp, 0(t0) # init gp
-
-#ifdef original_xxm
- lda a2, CSERVE_K_RD_IMPURE
- call_pal PAL_CSERVE_ENTRY
- lda v0, CNS_Q_BASE(v0)
-
- # Add KSEG offset to the impure area
- subq zero, 1, t0
- sll t0, 42, t0
- addq t0, v0, v0
-
- lda t0, CNS_Q_SIGNATURE(v0)
- bic t0, 0x07, t0 # Clear bottom 3 bits to avoid
- # allignment errors if the
- # impure area is total rubbish
- ldq t0, 0x00(t0)
- srl t0, 16, t0 # Shift signature into bottom 16 bits.
- lda t6, 0xDECB(zero) # Load the expected valid signature.
- zap t6, 0xFC, t6 # Clear the upper bits.
- cmpeq t0, t6, t0 # Is this a valid signature?
- beq t0, 1f # Not valid, don't trust input params.
-
-/*
- * Init the stack at the first 8K boundary
- * below the top of memory.
- */
- lda t0, CNS_Q_MEM_SIZE(v0)
- ldq t0, 0x00(t0) # Load memory size.
- subq t0, 1, t0 # Last address in memory
- srl t0, 13, t0 # Align to first 8KB boundary
- sll t0, 13, sp # below the top of memory.
- br zero, 2f
-
-/*
- * If memory size was not passed in via the
- * PALcode impure data use the system specific
- * MINIMUM_SYSTEM_MEMORY definition.
- */
-1:
- lda sp, (MINIMUM_SYSTEM_MEMORY&0xffff)(zero)
- ldah sp, ((MINIMUM_SYSTEM_MEMORY+0x8000)>>16)(sp)
- lda t0, (8*1024)(zero) # Allow for 8KB guard page.
- subq sp, t0, sp
-
-2:
-
-#endif /* original_xxm */
-
-
/*
* SimOS. Stack pointer is start of a valid phys or KSEG page
*/
sll t0, 42, t0
bis t0, v0, sp
-#ifdef original_xxm
- # Add KSEG offset to the stack pointer
- subq zero, 1, t0
- sll t0, 42, t0
- addq t0, sp, sp
-#endif
-
lda sp, -STARTFRM(sp) # Create a stack frame
stq ra, 0(sp) # Place return address on the stack
ldgp gp, 0(ra)
bsr zero, _exit
-.end __start
+.end _start
/*
-Copyright (c) 2003, 2004
-The Regents of The University of Michigan
-All Rights Reserved
-
-This code is part of the M5 simulator, developed by Nathan Binkert,
-Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
-from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
-Schultz.
-
-Permission is granted to use, copy, create derivative works and
-redistribute this software and such derivative works for any purpose,
-so long as the copyright notice above, this grant of permission, and
-the disclaimer below appear in all copies made; and so long as the
-name of The University of Michigan is not used in any advertising or
-publicity pertaining to the use or distribution of this software
-without specific, written prior authorization.
-
-THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
-WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
-IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
-THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
-INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
-DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
-WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
-ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-*/
+ * Copyright (c) 2003, 2004
+ * The Regents of The University of Michigan
+ * All Rights Reserved
+ *
+ * This code is part of the M5 simulator, developed by Nathan Binkert,
+ * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+ * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
+ * Schultz.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * redistribute this software and such derivative works for any purpose,
+ * so long as the copyright notice above, this grant of permission, and
+ * the disclaimer below appear in all copies made; and so long as the
+ * name of The University of Michigan is not used in any advertising or
+ * publicity pertaining to the use or distribution of this software
+ * without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
+ * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
+ * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
+ * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
+ * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
#include "ev5_defs.h"
-#include "fromHudsonOsf.h" // OSF/1 specific definitions
-#include "fromHudsonMacros.h" // Global macro definitions
-#include "ev5_impure.h" // Scratch & logout area data structures
-#include "platform.h" // Platform specific definitions
+#include "fromHudsonOsf.h" // OSF/1 specific definitions
+#include "fromHudsonMacros.h" // Global macro definitions
- .global palJToKern
- .text 3
-palJToKern:
/* Jump to kernel
-args:
- Kernel address - a0
- PCBB - a1
- First free PFN - a3?
-
- Enable kseg addressing in ICSR
- Enable kseg addressing in MCSR
- Set VTBR -- Set to 1GB as per SRM, or maybe 8GB??
- Set PCBB -- pass pointer in arg
- Set PTBR -- get it out of PCB
- Set KSP -- get it out of PCB
-
- Jump to kernel address
-
- Kernel args-
- s0 first free PFN
- s1 ptbr
- s2 argc 0
- s3 argv NULL
- s5 osf_param (sysconfigtab) NULL
+ * args:
+ * Kernel address - a0
+ * PCBB - a1
+ * First free PFN - a3?
+ *
+ * Enable kseg addressing in ICSR
+ * Enable kseg addressing in MCSR
+ * Set VTBR -- Set to 1GB as per SRM, or maybe 8GB??
+ * Set PCBB -- pass pointer in arg
+ * Set PTBR -- get it out of PCB
+ * Set KSP -- get it out of PCB
+ *
+ * Jump to kernel address
+ *
+ * Kernel args-
+ * s0 first free PFN
+ * s1 ptbr
+ * s2 argc 0
+ * s3 argv NULL
+ * s5 osf_param (sysconfigtab) NULL
*/
+ .global palJToKern
+ .text 3
+palJToKern:
ALIGN_BRANCH
ldq_p a0, 0(zero)
ldq_p a1, 8(zero)
ldq_p a3, 16(zero)
-#ifdef undef
- LDLI(t0,0x200000000) // 8GB, like the Mikasa
- LDLI(t0,0x40000000) // 1GB, like the SRM
- STALL // don't dual issue the load with mtpr -pb
-#endif
/* Point the Vptbr at 8GB */
lda t0, 0x1(zero)
sll t0, 33, t0
/* Turn on superpage mapping in the mbox and icsr */
lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
STALL // don't dual issue the load with mtpr -pb
- mtpr t0, mcsr // Set the super page mode enable bit
+ mtpr t0, mcsr // Set the super page mode enable bit
STALL // don't dual issue the load with mtpr -pb
lda t0, 0(zero)
LDLI (t1,0x20000000)
STALL // don't dual issue the load with mtpr -pb
- mfpr t0, icsr // Enable superpage mapping
+ mfpr t0, icsr // Enable superpage mapping
STALL // don't dual issue the load with mtpr -pb
bis t0, t1, t0
mtpr t0, icsr
- STALL // Required stall to update chip ...
+ STALL // Required stall to update chip ...
STALL
STALL
STALL
STALL
ldq_p s0, PCB_Q_PTBR(a1)
- sll s0, VA_S_OFF, s0 // Shift PTBR into position
+ sll s0, VA_S_OFF, s0 // Shift PTBR into position
STALL // don't dual issue the load with mtpr -pb
- mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
+ mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
STALL // don't dual issue the load with mtpr -pb
ldq_p sp, PCB_Q_KSP(a1)
- mtpr a0, excAddr // Load the dispatch address.
+ mtpr a0, excAddr // Load the dispatch address.
STALL // don't dual issue the load with mtpr -pb
- bis a3, zero, a0 // first free PFN
- ldq_p a1, PCB_Q_PTBR(a1) // ptbr
- ldq_p a2, 24(zero) // argc
- ldq_p a3, 32(zero) // argv
- ldq_p a4, 40(zero) // environ
- lda a5, 0(zero) // osf_param
+ bis a3, zero, a0 // first free PFN
+ ldq_p a1, PCB_Q_PTBR(a1) // ptbr
+ ldq_p a2, 24(zero) // argc
+ ldq_p a3, 32(zero) // argv
+ ldq_p a4, 40(zero) // environ
+ lda a5, 0(zero) // osf_param
STALL // don't dual issue the load with mtpr -pb
- mtpr zero, dtbIa // Flush all D-stream TB entries
- mtpr zero, itbIa // Flush all I-stream TB entries
+ mtpr zero, dtbIa // Flush all D-stream TB entries
+ mtpr zero, itbIa // Flush all I-stream TB entries
br zero, 2f
ALIGN_BLOCK
-2: NOP
- mtpr zero, icFlush // Flush the icache.
+2: NOP
+ mtpr zero, icFlush // Flush the icache.
NOP
NOP
- NOP // Required NOPs ... 1-10
+ NOP // Required NOPs ... 1-10
NOP
NOP
NOP
NOP
NOP
- NOP // Required NOPs ... 11-20
+ NOP // Required NOPs ... 11-20
NOP
NOP
NOP
NOP
NOP
- NOP // Required NOPs ... 21-30
+ NOP // Required NOPs ... 21-30
NOP
NOP
NOP
NOP
NOP
- NOP // Required NOPs ... 31-40
+ NOP // Required NOPs ... 31-40
NOP
NOP
NOP
NOP
NOP
-
-
- NOP // Required NOPs ... 41-44
+ NOP // Required NOPs ... 41-44
NOP
NOP
NOP
- hw_rei_stall // Dispatch to kernel
-
-
+ hw_rei_stall // Dispatch to kernel
/*
-Copyright (c) 2003, 2004
-The Regents of The University of Michigan
-All Rights Reserved
-
-This code is part of the M5 simulator, developed by Nathan Binkert,
-Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
-from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
-Schultz.
-
-Permission is granted to use, copy, create derivative works and
-redistribute this software and such derivative works for any purpose,
-so long as the copyright notice above, this grant of permission, and
-the disclaimer below appear in all copies made; and so long as the
-name of The University of Michigan is not used in any advertising or
-publicity pertaining to the use or distribution of this software
-without specific, written prior authorization.
-
-THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
-WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
-IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
-THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
-INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
-DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
-WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
-ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-*/
+ * Copyright (c) 2003, 2004
+ * The Regents of The University of Michigan
+ * All Rights Reserved
+ *
+ * This code is part of the M5 simulator, developed by Nathan Binkert,
+ * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+ * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
+ * Schultz.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * redistribute this software and such derivative works for any purpose,
+ * so long as the copyright notice above, this grant of permission, and
+ * the disclaimer below appear in all copies made; and so long as the
+ * name of The University of Michigan is not used in any advertising or
+ * publicity pertaining to the use or distribution of this software
+ * without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
+ * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
+ * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
+ * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
+ * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
-#include "ev5_defs.h"
-#include "fromHudsonOsf.h" // OSF/1 specific definitions
-#include "fromHudsonMacros.h" // Global macro definitions
-#include "ev5_impure.h" // Scratch & logout area data structures
-#include "platform.h" // Platform specific definitions
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
+#include "ev5_defs.h"
+#include "fromHudsonOsf.h" // OSF/1 specific definitions
+#include "fromHudsonMacros.h" // Global macro definitions
+/*
+ * args:
+ * a0: here
+ * a1: boot location
+ * a2: CSERVE_J_KTOPAL
+ * a3: restrart_pv
+ * a4: vptb
+ * a5: my_rpb
+ *
+ * SRM Console Architecture III 3-26
+ */
.global palJToSlave
.text 3
-
- /*
- * args:
- a0: here
- a1: boot location
- a2: CSERVE_J_KTOPAL
- a3: restrart_pv
- a4: vptb
- a5: my_rpb
-
- */
palJToSlave:
- /*
- * SRM Console Architecture III 3-26
- */
-
ALIGN_BRANCH
bis a3, zero, pv
/* Turn on superpage mapping in the mbox and icsr */
lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
STALL // don't dual issue the load with mtpr -pb
- mtpr t0, mcsr // Set the super page mode enable bit
+ mtpr t0, mcsr // Set the super page mode enable bit
STALL // don't dual issue the load with mtpr -pb
lda t0, 0(zero)
LDLI (t1,0x20000000)
STALL // don't dual issue the load with mtpr -pb
- mfpr t0, icsr // Enable superpage mapping
+ mfpr t0, icsr // Enable superpage mapping
STALL // don't dual issue the load with mtpr -pb
bis t0, t1, t0
mtpr t0, icsr
- STALL // Required stall to update chip ...
+ STALL // Required stall to update chip ...
STALL
STALL
STALL
STALL
ldq_p s0, PCB_Q_PTBR(a5)
- sll s0, VA_S_OFF, s0 // Shift PTBR into position
+ sll s0, VA_S_OFF, s0 // Shift PTBR into position
STALL // don't dual issue the load with mtpr -pb
- mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
+ mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
STALL // don't dual issue the load with mtpr -pb
ldq_p sp, PCB_Q_KSP(a5)
- //mtpr a0, excAddr // Load the dispatch address.
- //STALL // don't dual issue the load with mtpr -pb
- //bis a3, zero, a0 // first free PFN
- // ldq_p a1, PCB_Q_PTBR(a5) // ptbr
+ mtpr zero, dtbIa // Flush all D-stream TB entries
+ mtpr zero, itbIa // Flush all I-stream TB entries
- //ldq_p a2, 24(zero) // argc
- //ldq_p a3, 32(zero) // argv
- //ldq_p a4, 40(zero) // environ
- //lda a5, 0(zero) // osf_param
- //STALL // don't dual issue the load with mtpr -pb
- mtpr zero, dtbIa // Flush all D-stream TB entries
- mtpr zero, itbIa // Flush all I-stream TB entries
-
-
- mtpr a1, excAddr // Load the dispatch address.
+ mtpr a1, excAddr // Load the dispatch address.
STALL // don't dual issue the load with mtpr -pb
STALL // don't dual issue the load with mtpr -pb
- mtpr zero, dtbIa // Flush all D-stream TB entries
- mtpr zero, itbIa // Flush all I-stream TB entries
+ mtpr zero, dtbIa // Flush all D-stream TB entries
+ mtpr zero, itbIa // Flush all I-stream TB entries
br zero, 2f
ALIGN_BLOCK
2: NOP
- mtpr zero, icFlush // Flush the icache.
+ mtpr zero, icFlush // Flush the icache.
NOP
NOP
- NOP // Required NOPs ... 1-10
+ NOP // Required NOPs ... 1-10
NOP
NOP
NOP
NOP
NOP
- NOP // Required NOPs ... 11-20
+ NOP // Required NOPs ... 11-20
NOP
NOP
NOP
NOP
NOP
- NOP // Required NOPs ... 21-30
+ NOP // Required NOPs ... 21-30
NOP
NOP
NOP
NOP
NOP
- NOP // Required NOPs ... 31-40
+ NOP // Required NOPs ... 31-40
NOP
NOP
NOP
NOP
NOP
-
-
- NOP // Required NOPs ... 41-44
+ NOP // Required NOPs ... 41-44
NOP
NOP
NOP
- hw_rei_stall // Dispatch to kernel
+ hw_rei_stall // Dispatch to kernel
/*
-Copyright 1993, 1994 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-#ifndef LINT
-static char *rcsid = "$Id: printf.c,v 1.1.1.1 1997/10/30 23:27:12 verghese Exp $";
-#endif
-
-/*
- * $Log: printf.c,v $
- * Revision 1.1.1.1 1997/10/30 23:27:12 verghese
- * current 10/29/97
- *
- * Revision 1.1 1995/06/26 21:09:35 berc
- * Initial revision
- *
- * Revision 1.8 1994/10/06 20:29:08 fdh
- * Corrected unsigned long declaration.
+ * Copyright (c) 2003, 2004
+ * The Regents of The University of Michigan
+ * All Rights Reserved
*
- * Revision 1.7 1994/08/05 20:16:23 fdh
- * Updated Copyright header and RCS $Id: identifier.
+ * This code is part of the M5 simulator, developed by Nathan Binkert,
+ * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+ * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
+ * Schultz.
*
- * Revision 1.6 1994/06/21 15:41:54 rusling
- * fixedup WNT compiler warnings
+ * Permission is granted to use, copy, create derivative works and
+ * redistribute this software and such derivative works for any purpose,
+ * so long as the copyright notice above, this grant of permission, and
+ * the disclaimer below appear in all copies made; and so long as the
+ * name of The University of Michigan is not used in any advertising or
+ * publicity pertaining to the use or distribution of this software
+ * without specific, written prior authorization.
*
- * Revision 1.5 1994/06/17 19:35:37 fdh
- * Clean-up...
- *
- * Revision 1.4 1994/01/19 10:40:08 rusling
- * Ported to Alpha Windows NT.
- *
- * Revision 1.3 1993/11/02 21:57:45 fdh
- * Fixed sign extension problem introduced in version 1.2
+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
+ * WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
+ * IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
+ * THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
+ * INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
+ * WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+ */
+
+/*
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
*
- * Revision 1.2 1993/10/13 15:29:02 rusling
- * Added floating point support in printf. This meant adding variable arguments to
- * it and FormatItem() and including stdarg.h.
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
*
- * Revision 1.1 1993/06/08 19:56:24 fdh
- * Initial revision
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
*
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*/
-
-
-/* printf.c
- L. S.
- Sun Feb 10 20:18:22 1985
- */
-
-//#include "system.h"
-#include "lib.h"
+#include <sys/types.h>
#include <stdarg.h>
-
-
-
-
/* The string s is terminated by a '\0' */
void
PutString(const char *s)
{
- while (*s) PutChar(*s++);
+ while (*s)
+ PutChar(*s++);
}
/* print c count times */
void
PutRepChar(char c, int count)
{
- while (count--) PutChar(c);
+ while (count--)
+ PutChar(c);
}
/* put string reverse */
void
PutStringReverse(const char *s, int index)
{
- while ((index--) > 0) PutChar(s[index]);
+ while (index-- > 0)
+ PutChar(s[index]);
}
-/* prints value in radix, in a field width width, with fill
- character fill
- if radix is negative, print as signed quantity
- if width is negative, left justify
- if width is 0, use whatever is needed
- if fill is 0, use ' '
+/*
+ * prints value in radix, in a field width width, with fill
+ * character fill
+ * if radix is negative, print as signed quantity
+ * if width is negative, left justify
+ * if width is 0, use whatever is needed
+ * if fill is 0, use ' '
*/
void
-PutNumber(sl value, int radix, int width, char fill)
+PutNumber(long value, int radix, int width, char fill)
{
- char buffer[40];
- ui bufferindex = 0;
- ul uvalue;
- uw digit;
- uw left = FALSE;
- uw negative = FALSE;
-
- if (fill == 0) fill = ' ';
-
- if (width < 0) {
- width = -width;
- left = TRUE;
- }
- if (width < 0 || width > 80) width = 0;
-
- if (radix < 0) {
- radix = -radix;
- if (value < 0) {
- negative = TRUE;
- value = -value;
- }
+ char buffer[40];
+ uint bufferindex = 0;
+ ulong uvalue;
+ ushort digit;
+ ushort left = 0;
+ ushort negative = 0;
+
+ if (fill == 0)
+ fill = ' ';
+
+ if (width < 0) {
+ width = -width;
+ left = 1;
}
- switch (radix) {
- case 8:
- case 10:
- case 16: break;
- default: {
- PutString("****");
- return;
- }
- }
- uvalue = value;
- do {
- if (radix != 16)
- {
- digit = (uw)(uvalue % radix);
- uvalue /= radix;
+
+ if (width < 0 || width > 80)
+ width = 0;
+
+ if (radix < 0) {
+ radix = -radix;
+ if (value < 0) {
+ negative = 1;
+ value = -value;
+ }
}
- else
- {
- digit = (uw)(uvalue & 0xf);
- uvalue = uvalue >> 4;
+
+ switch (radix) {
+ case 8:
+ case 10:
+ case 16:
+ break;
+
+ default:
+ PutString("****");
+ return;
}
- buffer[bufferindex] = digit + ((digit <= 9) ? '0' : ('A' - 10));
- bufferindex += 1;
+
+ uvalue = value;
+
+ do {
+ if (radix != 16) {
+ digit = (ushort)(uvalue % radix);
+ uvalue /= radix;
+ } else {
+ digit = (ushort)(uvalue & 0xf);
+ uvalue = uvalue >> 4;
+ }
+ buffer[bufferindex] = digit + ((digit <= 9) ? '0' : ('A' - 10));
+ bufferindex += 1;
} while (uvalue != 0);
+
/* fill # ' ' and negative cannot happen at once */
- if (negative) {
- buffer[bufferindex] = '-';
- bufferindex += 1;
+ if (negative) {
+ buffer[bufferindex] = '-';
+ bufferindex += 1;
}
- if ((ui)width <= bufferindex) PutStringReverse(buffer, bufferindex);
- else {
- width -= bufferindex;
- if (!left) PutRepChar(fill, width);
- PutStringReverse(buffer, bufferindex);
- if (left) PutRepChar(fill, width);
+
+ if ((uint)width <= bufferindex) {
+ PutStringReverse(buffer, bufferindex);
+ } else {
+ width -= bufferindex;
+ if (!left)
+ PutRepChar(fill, width);
+ PutStringReverse(buffer, bufferindex);
+ if (left)
+ PutRepChar(fill, width);
}
}
-ul power(long base, long n)
+ulong
+power(long base, long n)
{
- ul p;
+ ulong p;
- for (p = 1; n > 0; --n)
- p = p * base;
- return p;
+ for (p = 1; n > 0; --n)
+ p = p * base;
+ return p;
}
-void putFloat(double a, int fieldwidth, char fill)
+void
+putFloat(double a, int fieldwidth, char fill)
{
- int i;
- ul b;
-
-/*
- * Put out everything before the decimal place.
- */
- PutNumber(((ul) a), 10, fieldwidth, fill);
-/*
- * Output the decimal place.
- */
- PutChar('.' & 0x7f);
-/*
- * Output the n digits after the decimal place.
- */
- for (i = 1; i < 6; i++) {
- b = (ul)(power(10, i) * (double)(a - (ul) a));
- PutChar((char)(b % 10) + '0');
- }
+ int i;
+ ulong b;
+
+ /*
+ * Put out everything before the decimal place.
+ */
+ PutNumber(((ulong) a), 10, fieldwidth, fill);
+
+ /*
+ * Output the decimal place.
+ */
+ PutChar('.' & 0x7f);
+
+ /*
+ * Output the n digits after the decimal place.
+ */
+ for (i = 1; i < 6; i++) {
+ b = (ulong)(power(10, i) * (double)(a - (ulong) a));
+ PutChar((char)(b % 10) + '0');
+ }
}
+
const char *
FormatItem(const char *f, va_list *ap)
{
- char c;
- int fieldwidth = 0;
- int leftjust = FALSE;
- int radix = 0;
- char fill = ' ';
- if (*f == '0') fill = '0';
- while (c = *f++) {
- if (c >= '0' && c <= '9') {
- fieldwidth = (fieldwidth * 10) + (c - '0');
- }
- else switch (c) {
- case '\000': return(--f);
- case '%': PutChar('%');
- return(f);
- case '-': leftjust = TRUE;
- break;
- case 'c': {
- char a = va_arg(*ap, char *);
-
- if (leftjust) PutChar(a & 0x7f);
- if (fieldwidth > 0) PutRepChar(fill, fieldwidth - 1);
- if (!leftjust) PutChar(a & 0x7f);
- return(f);
- }
- case 's': {
- const char *a = va_arg(*ap, const char *);
-
- if (leftjust) PutString((const char *) a);
- if (fieldwidth > strlen((const char *) a))
- PutRepChar(fill, fieldwidth - strlen((const char *)a));
- if (!leftjust) PutString((const char *) a);
- return(f);
+ char c;
+ int fieldwidth = 0;
+ int leftjust = 0;
+ int radix = 0;
+ char fill = ' ';
+
+ if (*f == '0')
+ fill = '0';
+
+ while (c = *f++) {
+ if (c >= '0' && c <= '9') {
+ fieldwidth = (fieldwidth * 10) + (c - '0');
+ } else {
+ switch (c) {
+ case '\000':
+ return(--f);
+ case '%':
+ PutChar('%');
+ return(f);
+ case '-':
+ leftjust = 1;
+ break;
+ case 'c': {
+ char a = (char)va_arg(*ap, int);
+
+ if (leftjust)
+ PutChar(a & 0x7f);
+ if (fieldwidth > 0)
+ PutRepChar(fill, fieldwidth - 1);
+ if (!leftjust)
+ PutChar(a & 0x7f);
+ return(f);
+ }
+ case 's': {
+ const char *a = va_arg(*ap, const char *);
+
+ if (leftjust)
+ PutString((const char *) a);
+ if (fieldwidth > strlen((const char *) a))
+ PutRepChar(fill, fieldwidth - strlen((const char *)a));
+ if (!leftjust)
+ PutString((const char *) a);
+ return(f);
+ }
+ case 'd':
+ radix = -10;
+ break;
+ case 'u':
+ radix = 10;
+ break;
+ case 'x':
+ radix = 16;
+ break;
+ case 'X':
+ radix = 16;
+ break;
+ case 'o':
+ radix = 8;
+ break;
+ case 'f': {
+ double a = va_arg(*ap, double);
+
+ putFloat(a, fieldwidth, fill);
+ return(f);
+ }
+ default: /* unknown switch! */
+ radix = 3;
+ break;
+ }
}
- case 'd': radix = -10;
- break;
- case 'u': radix = 10;
- break;
- case 'x': radix = 16;
- break;
- case 'X': radix = 16;
- break;
- case 'o': radix = 8;
- break;
- case 'f': {
- double a = va_arg(*ap, double);
-
- putFloat(a, fieldwidth, fill);
- return(f);
- }
- default: /* unknown switch! */
- radix = 3;
- break;
- }
- if (radix) break;
+
+ if (radix)
+ break;
}
- if (leftjust) fieldwidth = -fieldwidth;
- {
- sl a = va_arg(*ap, sl);
- PutNumber(a, radix, fieldwidth, fill);
- }
- return(f);
+
+ if (leftjust)
+ fieldwidth = -fieldwidth;
+
+ long a = va_arg(*ap, long);
+ PutNumber(a, radix, fieldwidth, fill);
+
+ return(f);
}
int
printf(const char *f, ...)
{
- va_list ap;
+ va_list ap;
- va_start(ap, f);
+ va_start(ap, f);
- while (*f) {
- if (*f == '%') f = FormatItem(f + 1, &ap);
- else PutChar(*f++);
- }
+ while (*f) {
+ if (*f == '%')
+ f = FormatItem(f + 1, &ap);
+ else
+ PutChar(*f++);
+ }
- if (*(f-1)=='\n') {
- /* add a line-feed (SimOS console output goes to shell */
- PutChar('\r');
- }
+ if (*(f - 1) == '\n') {
+ /* add a line-feed (SimOS console output goes to shell */
+ PutChar('\r');
+ }
- va_end(ap); /* clean up */
- return 0;
+ va_end(ap); /* clean up */
+ return 0;
}
void
panic(const char *f, ...)
{
- va_list ap;
+ va_list ap;
- va_start(ap, f);
+ va_start(ap, f);
- printf("CONSOLE PANIC (looping): ");
- while (*f) {
- if (*f == '%') f = FormatItem(f + 1, &ap);
- else PutChar(*f++);
+ printf("CONSOLE PANIC (looping): ");
+ while (*f) {
+ if (*f == '%')
+ f = FormatItem(f + 1, &ap);
+ else
+ PutChar(*f++);
}
- va_end(ap); /* clean up */
- while(1);
+ va_end(ap); /* clean up */
+ while(1);
}
-
-
+++ /dev/null
-/*
-Copyright 1993, 1994, 1995 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-
-
-#ifndef __CIA_H_LOADED
-#define __CIA_H_LOADED
-
-/*
- * $Id: cia.h,v 1.1.1.1 1997/10/30 23:27:14 verghese Exp $;
- */
-
-/*
- * $Log: cia.h,v $
- * Revision 1.1.1.1 1997/10/30 23:27:14 verghese
- * current 10/29/97
- *
- * Revision 1.3 1995/04/20 16:37:22 cruz
- * Made some deletions and modifications.
- *
- * Revision 1.2 1994/12/19 18:33:02 cruz
- * Added some new constants.
- *
- * Revision 1.1 1994/11/23 19:49:39 cruz
- * Initial revision
- *
- *
- */
-
-/*
- ******************************** WARNING *******************************
- * BE EXTREMELY CAREFUL WHEN USING OFFSETS LARGER THAN 0x8000 WITH
- * AN "LDA" INSTRUCTION BECAUSE THEY WILL CAUSE AN UNWANTED SIGN
- * EXTENSION.
- ******************************** WARNING *******************************
-*/
-
-/* ======================================================================
- * = BASE ADDRESSES =
- * ======================================================================
- *
- * Define the base address for registers accessing the memory
- * controller
-*/
-#define MC_GCR_BASE 0x874 /* General Control Register */
-#define MC_GCR_BASE_SHIFT 28 /* Shift base by this # of bits */
-#define MC_DIAG_BASE 0x874 /* Diagnostic Registers */
-#define MC_DIAG_BASE_SHIFT 28
-#define MC_PERFMON_BASE 0x874 /* Performance monitoring regs */
-#define MC_PERFMON_BASE_SHIFT 28
-#define MC_ERROR_BASE 0x874 /* Error Registers */
-#define MC_ERROR_BASE_SHIFT 28
-#define MC_MCR_BASE 0x875 /* Memory Configuration Registers*/
-#define MC_MCR_BASE_SHIFT 28
-#define MC_PCI_BASE 0x876 /* PCI Configuration Registers */
-#define MC_PCI_BASE_SHIFT 28
-
-
-/* ======================================================================
- * = OFFSETS FOR THE GENERAL CONTROL REGISTERS (87.4000.0000) =
- * ======================================================================
-*/
-#define MC_PCI_REV 0x80 /* Revision of CIA ASIC. */
-#define MC_PCI_LAT 0xC0 /* PCI Master Latency Timer. */
-#define MC_CIA_CTRL 0x100 /* CIA Control Register. */
-#define MC_CIA_CNFG 0x200 /* CIA Configuration Register. */
-#define MC_HAE_MEM 0x400 /* HW Address Extension (Sparse)*/
-#define MC_HAE_IO 0x440 /* HW Addr. Ext. for sparse IO. */
-#define MC_CFG 0x480 /* Configuration reg for bridges*/
-#define MC_CACK_EN 0x600 /* Acknowledgement Control Reg. */
-
-
-/* ======================================================================
- * = OFFSETS FOR THE DIAGNOSTIC REGISTERS (87.4000.0000) =
- * ======================================================================
-*/
-#define MC_CIA_DIAG 0x2000 /* Diagnostic control register */
-#define MC_DIAG_CHECK 0x3000 /* Diagnostic check register */
-
-
-/* ======================================================================
- * = OFFSETS FOR THE PERFORMANCE MONITORING REGISTERS (87.4000.0000) =
- * ======================================================================
-*/
-#define MC_PERF_MONITOR 0x4000 /* Performance monitor register */
-#define MC_PERF_CONTROL 0x4040 /* Perf. Mon. Control register */
-
-
-/* ======================================================================
- * = OFFSETS FOR THE ERROR REGISTERS (87.4000.0000) =
- * ======================================================================
-*/
-#define MC_CPU_ERR0 0x8000 /* CPU Error Info Register 0. */
-#define MC_CPU_ERR1 0x8040 /* CPU Error Info Register 1. */
-#define MC_CIA_ERR 0x8200 /* CIA Error Register. */
-#define MC_CIA_STAT 0x8240 /* CIA Status Register. */
-#define MC_ERR_MASK 0x8280 /* CIA Error Mask Register. */
-#define MC_CIA_SYN 0x8300 /* CIA Syndrome Register. */
-#define MC_MEM_ERR0 0x8400 /* Memory Port Status Register 0*/
-#define MC_MEM_ERR1 0x8440 /* Memory Port Status Register 1*/
-#define MC_PCI_ERR0 0x8800 /* PCI Error Status Register 0. */
-#define MC_PCI_ERR1 0x8840 /* PCI Error Status Register 1. */
-
-
-/* ======================================================================
- * = OFFSETS FOR THE MEMORY CONFIGURATION REGISTERS (87.5000.0000) =
- * ======================================================================
-*/
-#define MC_MCR 0x0 /* Memory Configuration Register*/
-#define MC_MBA0 0x600 /* Memory Base Address Register */
-#define MC_MBA2 0x680 /* Memory Base Address Register */
-#define MC_MBA4 0x700 /* Memory Base Address Register */
-#define MC_MBA6 0x780 /* Memory Base Address Register */
-#define MC_MBA8 0x800 /* Memory Base Address Register */
-#define MC_MBAA 0x880 /* Memory Base Address Register */
-#define MC_MBAC 0x900 /* Memory Base Address Register */
-#define MC_MBAE 0x980 /* Memory Base Address Register */
-#define MC_TMG0 0xB00 /* Memory Timing Register */
-#define MC_TMG1 0xB40 /* Memory Timing Register */
-#define MC_TMG2 0xB80 /* Memory Timing Register */
-
-
-/* ======================================================================
- * = OFFSETS FOR THE PCI CONFIGURATION REGISTERS (87.6000.0000) =
- * ======================================================================
-*/
-#define MC_TBIA 0x100 /* S/G Translation Buffer Inval.*/
-#define MC_W0_BASE 0x400 /* Window Base 0. */
-#define MC_W0_MASK 0x440 /* Window Mask 0. */
-#define MC_T0_BASE 0x480 /* Translated Base 0. */
-#define MC_W1_BASE 0x500 /* Window Base 1. */
-#define MC_W1_MASK 0x540 /* Window Mask 1. */
-#define MC_T1_BASE 0x580 /* Translated Base 1. */
-#define MC_W2_BASE 0x600 /* Window Base 2. */
-#define MC_W2_MASK 0x640 /* Window Mask 2. */
-#define MC_T2_BASE 0x680 /* Translated Base 2. */
-#define MC_W3_BASE 0x700 /* Window Base 3. */
-#define MC_W3_MASK 0x740 /* Window Mask 3. */
-#define MC_T3_BASE 0x780 /* Translated Base 3. */
-#define MC_DAC 0x7C0 /* Window DAC Base. */
-#define MC_LTB_TAG0 0x800 /* Lockable Translation Buffer. */
-#define MC_LTB_TAG1 0x840 /* Lockable Translation Buffer. */
-#define MC_LTB_TAG2 0x880 /* Lockable Translation Buffer. */
-#define MC_LTB_TAG3 0x8C0 /* Lockable Translation Buffer. */
-#define MC_TB_TAG0 0x900 /* Translation Buffer Tag. */
-#define MC_TB_TAG1 0x940 /* Translation Buffer Tag. */
-#define MC_TB_TAG2 0x980 /* Translation Buffer Tag. */
-#define MC_TB_TAG3 0x9C0 /* Translation Buffer Tag. */
-#define MC_TB0_PAGE0 0x1000 /* Translation Buffer 0 Page. */
-#define MC_TB0_PAGE1 0x1040 /* Translation Buffer 0 Page. */
-#define MC_TB0_PAGE2 0x1080 /* Translation Buffer 0 Page. */
-#define MC_TB0_PAGE3 0x10C0 /* Translation Buffer 0 Page. */
-#define MC_TB1_PAGE0 0x1100 /* Translation Buffer 1 Page. */
-#define MC_TB1_PAGE1 0x1140 /* Translation Buffer 1 Page. */
-#define MC_TB1_PAGE2 0x1180 /* Translation Buffer 1 Page. */
-#define MC_TB1_PAGE3 0x11C0 /* Translation Buffer 1 Page. */
-#define MC_TB2_PAGE0 0x1200 /* Translation Buffer 2 Page. */
-#define MC_TB2_PAGE1 0x1240 /* Translation Buffer 2 Page. */
-#define MC_TB2_PAGE2 0x1280 /* Translation Buffer 2 Page. */
-#define MC_TB2_PAGE3 0x12C0 /* Translation Buffer 2 Page. */
-#define MC_TB3_PAGE0 0x1300 /* Translation Buffer 3 Page. */
-#define MC_TB3_PAGE1 0x1340 /* Translation Buffer 3 Page. */
-#define MC_TB3_PAGE2 0x1380 /* Translation Buffer 3 Page. */
-#define MC_TB3_PAGE3 0x13C0 /* Translation Buffer 3 Page. */
-#define MC_TB4_PAGE0 0x1400 /* Translation Buffer 4 Page. */
-#define MC_TB4_PAGE1 0x1440 /* Translation Buffer 4 Page. */
-#define MC_TB4_PAGE2 0x1480 /* Translation Buffer 4 Page. */
-#define MC_TB4_PAGE3 0x14C0 /* Translation Buffer 4 Page. */
-#define MC_TB5_PAGE0 0x1500 /* Translation Buffer 5 Page. */
-#define MC_TB5_PAGE1 0x1540 /* Translation Buffer 5 Page. */
-#define MC_TB5_PAGE2 0x1580 /* Translation Buffer 5 Page. */
-#define MC_TB5_PAGE3 0x15C0 /* Translation Buffer 5 Page. */
-#define MC_TB6_PAGE0 0x1600 /* Translation Buffer 6 Page. */
-#define MC_TB6_PAGE1 0x1640 /* Translation Buffer 6 Page. */
-#define MC_TB6_PAGE2 0x1680 /* Translation Buffer 6 Page. */
-#define MC_TB6_PAGE3 0x16C0 /* Translation Buffer 6 Page. */
-#define MC_TB7_PAGE0 0x1700 /* Translation Buffer 7 Page. */
-#define MC_TB7_PAGE1 0x1740 /* Translation Buffer 7 Page. */
-#define MC_TB7_PAGE2 0x1780 /* Translation Buffer 7 Page. */
-#define MC_TB7_PAGE3 0x17C0 /* Translation Buffer 7 Page. */
-
-
-/* ======================================================================
- * = BIT EXTENT FOR CIA_CTRL REGISTER (87.4000.0100) =
- * ======================================================================
-*/
-#define MC_CIA_CTRL_V_PCI_EN 0
-#define MC_CIA_CTRL_M_PCI_EN (1 << MC_CIA_CTRL_V_PCI_EN)
-#define MC_CIA_CTRL_V_PCI_LOCK_EN 1
-#define MC_CIA_CTRL_M_PCI_LOCK_EN (1 << MC_CIA_CTRL_V_PCI_LOCK_EN)
-#define MC_CIA_CTRL_V_PCI_LOOP_EN 2
-#define MC_CIA_CTRL_M_PCI_LOOP_EN (1 << MC_CIA_CTRL_V_PCI_LOOP_EN)
-#define MC_CIA_CTRL_V_FST_BB_EN 3
-#define MC_CIA_CTRL_M_FST_BB_EN (1 << MC_CIA_CTRL_V_FST_BB_EN)
-#define MC_CIA_CTRL_V_PCI_MST_EN 4
-#define MC_CIA_CTRL_M_PCI_MST_EN (1 << MC_CIA_CTRL_V_PCI_MST_EN)
-#define MC_CIA_CTRL_V_PCI_MEM_EN 5
-#define MC_CIA_CTRL_M_PCI_MEM_EN (1 << MC_CIA_CTRL_V_PCI_MEM_EN)
-#define MC_CIA_CTRL_V_PCI_REQ64_EN 6
-#define MC_CIA_CTRL_M_PCI_REQ64_EN (1 << MC_CIA_CTRL_V_PCI_REQ64_EN)
-#define MC_CIA_CTRL_V_PCI_ACK64_EN 7
-#define MC_CIA_CTRL_M_PCI_ACK64_EN (1 << MC_CIA_CTRL_V_PCI_ACK64_EN)
-#define MC_CIA_CTRL_V_ADDR_PE_EN 8
-#define MC_CIA_CTRL_M_ADDR_PE_EN (1 << MC_CIA_CTRL_V_ADDR_PE_EN)
-#define MC_CIA_CTRL_V_PERR_EN 9
-#define MC_CIA_CTRL_M_PERR_EN (1 << MC_CIA_CTRL_V_PERR_EN)
-#define MC_CIA_CTRL_V_FILLERR_EN 10
-#define MC_CIA_CTRL_M_FILLERR_EN (1 << MC_CIA_CTRL_V_FILLERR_EN)
-#define MC_CIA_CTRL_V_MCHKERR_EN 11
-#define MC_CIA_CTRL_M_MCHKERR_EN (1 << MC_CIA_CTRL_V_MCHKERR_EN)
-#define MC_CIA_CTRL_V_ECC_CHK_EN 12
-#define MC_CIA_CTRL_M_ECC_CHK_EN (1 << MC_CIA_CTRL_V_ECC_CHK_EN)
-#define MC_CIA_CTRL_V_ASSERT_IDLE_BC 13
-#define MC_CIA_CTRL_M_ASSERT_IDLE_BC (1 << MC_CIA_CTRL_V_ASSERT_IDLE_BC)
-#define MC_CIA_CTRL_V_CON_IDLE_BC 14
-#define MC_CIA_CTRL_M_CON_IDLE_BC (1 << MC_CIA_CTRL_V_CON_IDLE_BC)
-#define MC_CIA_CTRL_V_CSR_IOA_BYPASS 15
-#define MC_CIA_CTRL_M_CSR_IOA_BYPASS (1 << MC_CIA_CTRL_V_CSR_IOA_BYPASS )
-#define MC_CIA_CTRL_V_IO_FLUSHREQ_EN 16
-#define MC_CIA_CTRL_M_IO_FLUSHREQ_EN (1 << MC_CIA_CTRL_V_IO_FLUSHREQ_EN )
-#define MC_CIA_CTRL_V_CPU_FLUSHREQ_EN 17
-#define MC_CIA_CTRL_M_CPU_FLUSHREQ_EN (1 << MC_CIA_CTRL_V_CPU_FLUSHREQ_EN )
-#define MC_CIA_CTRL_V_ARB_EV5_EN 18
-#define MC_CIA_CTRL_M_ARB_EV5_EN (1 << MC_CIA_CTRL_V_ARB_EV5_EN)
-#define MC_CIA_CTRL_V_EN_ARB_LINK 19
-#define MC_CIA_CTRL_M_EN_ARB_LINK (1 << MC_CIA_CTRL_V_EN_ARB_LINK)
-#define MC_CIA_CTRL_V_RD_TYPE 20
-#define MC_CIA_CTRL_M_RD_TYPE (3 << MC_CIA_CTRL_V_RD_TYPE)
-#define MC_CIA_CTRL_V_RL_TYPE 24
-#define MC_CIA_CTRL_M_RL_TYPE (3 << MC_CIA_CTRL_V_RL_TYPE)
-#define MC_CIA_CTRL_V_RM_TYPE 28
-#define MC_CIA_CTRL_M_RM_TYPE (3 << MC_CIA_CTRL_V_RM_TYPE)
-
-
-/* ======================================================================
- * = BIT EXTENT FOR CACK_EN REGISTER (87.4000.0600) =
- * ======================================================================
-*/
-#define MC_CACK_EN_V_MEM_LOCK 0x0 /* Controls LOCK enable. */
-#define MC_CACK_EN_V_MB 0x1 /* Controls MB enable. */
-#define MC_CACK_EN_V_SET_DIRTY 0x2 /* Controls SET_DIRTY enable. */
-#define MC_CACK_EN_V_BC_VICTIM 0x3 /* Controls BC_VICTIM enable. */
-
-
-/* ======================================================================
- * = BIT SIZES FOR CACK_EN REGISTER (87.4000.0600) =
- * ======================================================================
-*/
-#define MC_CACK_EN_S_MEM_LOCK 1 /* Controls LOCK enable. */
-#define MC_CACK_EN_S_MB 1 /* Controls MB enable. */
-#define MC_CACK_EN_S_SET_DIRTY 1 /* Controls SET_DIRTY enable. */
-#define MC_CACK_EN_S_BC_VICTIM 1 /* Controls BC_VICTIM enable. */
-
-/* ======================================================================
- * = BIT MASKS FOR CACK_EN REGISTER (87.4000.0600) =
- * ======================================================================
-*/
-#define MC_CACK_EN_M_MEM_LOCK (((1<<MC_CACK_EN_S_MEM_LOCK)-1) << MC_CACK_EN_V_MEM_LOCK)
-#define MC_CACK_EN_M_MB (((1<<MC_CACK_EN_S_MB)-1) << MC_CACK_EN_V_MB)
-#define MC_CACK_EN_M_SET_DIRTY (((1<<MC_CACK_EN_S_SET_DIRTY)-1) << MC_CACK_EN_V_SET_DIRTY)
-#define MC_CACK_EN_M_BC_VICTIM (((1<<MC_CACK_EN_S_BC_VICTIM)-1) << MC_CACK_EN_V_BC_VICTIM)
-
-
-/* ======================================================================
- * = BIT EXTENT FOR MCR REGISTER (87.5000.0000) =
- * ======================================================================
-*/
-#define MC_MCR_V_MEM_SIZE 0x0 /* 1 = 256-bit data, 0 = 128-bit*/
-#define MC_MCR_V_CACHE_SIZE 0x4 /* Set to match CPU's cache size*/
-#define MC_MCR_V_REF_RATE 0x8 /* Refresh rate counter. */
-#define MC_MCR_V_REF_BURST 0x18 /* Refresh burst. */
-#define MC_MCR_V_TMG_R0 0x20 /* Row address setup. */
-#define MC_MCR_V_LONG_CBR_CAS 0x22 /* Refresh CAS pulse width. */
-#define MC_MCR_V_DLY_IDLE_BC 0x26 /* ??. */
-#define MC_MCR_V_EARLY_IDLE_BC 0x29 /* ??. */
-
-
-/* ======================================================================
- * = BIT SIZES FOR MCR REGISTER (87.5000.0000) =
- * ======================================================================
-*/
-#define MC_MCR_S_MEM_SIZE 1
-#define MC_MCR_S_CACHE_SIZE 3
-#define MC_MCR_S_REF_RATE 10
-#define MC_MCR_S_REF_BURST 2
-#define MC_MCR_S_TMG_R0 2
-#define MC_MCR_S_LONG_CBR_CAS 1
-#define MC_MCR_S_DLY_IDLE_BC 2
-#define MC_MCR_S_EARLY_IDLE_BC 1
-
-/* ======================================================================
- * = BIT MASKS FOR MCR REGISTER (87.5000.0000) =
- * ======================================================================
-*/
-#define MC_MCR_M_MEM_SIZE (((1<<MC_MCR_S_MEM_SIZE)-1) << MC_MCR_V_MEM_SIZE)
-#define MC_MCR_M_CACHE_SIZE (((1<<MC_MCR_S_CACHE_SIZE)-1) << MC_MCR_V_CACHE_SIZE)
-#define MC_MCR_M_REF_RATE (((1<<MC_MCR_S_REF_RATE)-1) << MC_MCR_V_REF_RATE)
-#define MC_MCR_M_REF_BURST (((1<<MC_MCR_S_REF_BURST)-1) << MC_MCR_V_REF_BURST)
-#define MC_MCR_M_TMG_R0 (((1<<MC_MCR_S_TMG_R0)-1) << MC_MCR_V_TMG_R0)
-#define MC_MCR_M_LONG_CBR_CAS (((1<<MC_MCR_S_LONG_CBR_CAS)-1) << MC_MCR_V_LONG_CBR_CAS)
-#define MC_MCR_M_DLY_IDLE_BC (((1<<MC_MCR_S_DLY_IDLE_BC)-1) << MC_MCR_V_DLY_IDLE_BC)
-#define MC_MCR_M_EARLY_IDLE_BC (((1<<MC_MCR_S_EARLY_IDLE_BC)-1) << MC_MCR_V_EARLY_IDLE_BC)
-
-/* ======================================================================
- * = BIT EXTENT FOR TIMING REGISTERS =
- * ======================================================================
-*/
-#define MC_TMG_V_R1 0 /* [1:0] row address hold */
-#define MC_TMG_V_R2 2 /* [3:2] row address hold */
-#define MC_TMG_V_R3 4 /* [5:4] read, cycle time */
-#define MC_TMG_V_R4 6 /* [7:6] read, delay from */
- /* MEM_RD_RDY to CAS assertion */
-#define MC_TMG_V_R5 8 /* [9:8] read, cas pulse width */
-#define MC_TMG_V_R6 10 /* [11:10] read, column address hold*/
-#define MC_TMG_V_W1 12 /* [13:12] writes, non-linked */
- /* victim, delay from start to MEM_WR */
-#define MC_TMG_V_W4 14 /*[16:14] writes, MEM_WR to CAS assert*/
-#define MC_TMG_V_PRE 17 /* [17] RAS Pre-charge delay */
- /* __0=no delay, 1=delay 30 ns */
-#define MC_TMG_V_V3 18 /* [19:18] write, cycle time */
-#define MC_TMG_V_V4 20 /* [22:20] linked victim, */
- /* MEM_WR to CAS assertion */
-#define MC_TMG_V_V5 24 /* [25:24] write, victim, CAS */
- /* pulse width */
-#define MC_TMG_V_V6 26 /* [27:26] victim/write, column*/
- /* address hold */
-#define MC_TMG_V_RV 28 /* [29:28] read-victim, delay */
- /* from MEM_RD_RDY de-assertion*/
- /* to MEM_WR */
-#define MC_TMG_V_RD_DLY 30 /* [31:30] select clk the dsw */
- /* will use to capture memory */
- /* data 0=CLK, 1=CLK2X */
-
-
-/* ======================================================================
- * = BIT EXTENT FOR MBA REGISTERS (87.5000.0600 + n*80) =
- * ======================================================================
-*/
-#define MC_MBA_V_S0_VALID 0 /* Side 0 for the bank is valid */
-#define MC_MBA_V_ROW_TYPE 1 /* Row and Column configuration */
-#define MC_MBA_V_MASK 4 /* Indicates size of mem SIMMs */
-#define MC_MBA_V_S1_VALID 15 /* Side 1 for the bank is valid */
-#define MC_MBA_V_PATTERN 16 /* Base address of the bank */
-#define MC_MBA_V_TMG_SEL 28 /* Select timing register. */
-
-/* ======================================================================
- * = BIT FIELD VALUES FOR MBA REGISTERS (87.5000.0600 + n*80) =
- * ======================================================================
-*/
-#define MC_MBA_V_ROW_TYPE_10X10 0 /* 10 row, 10 column */
-#define MC_MBA_V_ROW_TYPE_12X10 1 /* 12 row, 10 column */
-#define MC_MBA_V_ROW_TYPE_11X11 1 /* 11 row, 11 column */
-#define MC_MBA_V_ROW_TYPE_13X11 2 /* 13 row, 11 column */
-#define MC_MBA_V_ROW_TYPE_12X12 2 /* 12 row, 12 column */
-
-#define MC_MBA_V_TMG_SEL_TMG0 0 /* Select timing register 0. */
-#define MC_MBA_V_TMG_SEL_TMG1 1 /* Select timing register 1. */
-#define MC_MBA_V_TMG_SEL_TMG2 2 /* Select timing register 2. */
-
-
-/* ======================================================================
- * = BIT SIZES FOR MBA REGISTERS (87.5000.0600 + n*80) =
- * ======================================================================
-*/
-#define MC_MBA_S_S0_VALID 1
-#define MC_MBA_S_ROW_TYPE 2
-#define MC_MBA_S_MASK 5
-#define MC_MBA_S_S1_VALID 1
-#define MC_MBA_S_PATTERN 10
-#define MC_MBA_S_TMG_SEL 2
-
-/* ======================================================================
- * = BIT MASKS FOR MBA REGISTERS (87.5000.0600 + n*80) =
- * ======================================================================
-*/
-#define MC_MBA_M_S0_VALID (((1<<MC_MBA_S_S0_VALID)-1) << MC_MBA_V_S0_VALID)
-#define MC_MBA_M_ROW_TYPE (((1<<MC_MBA_S_ROW_TYPE)-1) << MC_MBA_V_ROW_TYPE)
-#define MC_MBA_M_MASK (((1<<MC_MBA_S_MASK)-1) << MC_MBA_V_MASK)
-#define MC_MBA_M_S1_VALID (((1<<MC_MBA_S_S1_VALID)-1) << MC_MBA_V_S1_VALID)
-#define MC_MBA_M_PATTERN (((1<<MC_MBA_S_PATTERN)-1) << MC_MBA_V_PATTERN)
-#define MC_MBA_M_TMG_SEL (((1<<MC_MBA_S_TMG_SEL)-1) << MC_MBA_V_TMG_SEL)
-
-
-
-#define cia_k_main_csr_base 0x0874 /* CIA General Control Register Base*/
-#define cia_v_main_csr_base 28 /* Shift base by this # of bits */
-
-/* Offsets from CIA control base register. */
-
-#define hae_mem 0x0400
-#define hae_io 0x0440
-
-#define cia_err 0x8200
-#define cia_err_mask 0x8280
-#define cia_err_v_rcvd_mas_abt 7
-#define cia_err_m_rcvd_mas_abt (1 << cia_err_v_rcvd_mas_abt)
-#define cia_err_mask_v_mas_abt 7
-#define cia_err_mask_m_mas_abt (1 << cia_err_mask_v_mas_abt)
-
-#define cia_k_addr_trans 0x876 /* CIA's PCI Address Translation Regs*/
-#define cia_v_addr_trans 28 /* Shift base by this # of bits */
-
-/* Offsets from PCI address translation base register. Must be < 0x8000 */
-/* if they are to be used with LDA instructions! */
-#define w_base0 0x0400
-#define w_mask0 0x0440
-#define t_base0 0x0480
-#define w_base1 0x0500
-#define w_mask1 0x0540
-#define t_base1 0x0580
-#define w_base2 0x0600
-#define w_mask2 0x0640
-#define t_base2 0x0680
-#define w_base3 0x0700
-#define w_mask3 0x0740
-#define t_base3 0x0780
-
-#define w_v_en 0x0
-#define w_m_en (1 << w_v_en)
-
-
-
-/* CIA Memory Control Register. */
-#define mcr 0
-#define mba 0x600
-#define mba_v_disp 0x7
-#define mba_k_disp 0x80 /* 1 << mba_v_disp */
-
-
-
-/* The following constants define which bits are provided by the HAE_MEM*/
-/* register for each of the three sparse regions. */
-#define hae_sp1_bits 0xE0000000
-#define hae_sp2_bits 0xF8000000
-#define hae_sp3_bits 0xFC000000
-
-#endif /* __CIA_H_LOADED */
/*
-Copyright 1993, 1994 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-
-/*
- * VID: [T1.2] PT: [Fri Apr 21 16:47:20 1995] SF: [cserve.h]
- * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*/
+
#define __CSERVE_LOADED 1
-/*
-*****************************************************************************
-**
-** FACILITY:
-**
-** DECchip 21164 OSF/1 PALcode
-**
-** MODULE:
-**
-** cserve.h
-**
-** MODULE DESCRIPTION:
-**
-** Platform specific cserve definitions.
-**
-** AUTHOR: ES
-**
-** CREATION DATE: 21-JUN-1994
-**
-** $Id: cserve.h,v 1.1.1.1 1997/10/30 23:27:18 verghese Exp $
-**
-** MODIFICATION HISTORY:
-**
-** $Log: cserve.h,v $
-** Revision 1.1.1.1 1997/10/30 23:27:18 verghese
-** current 10/29/97
-**
-** Revision 1.6 1995/04/03 17:29:52 samberg
-** Add rd_bccfg_off
-**
-** Revision 1.5 1995/02/02 19:31:34 samberg
-** Added WR_BCACHE, deleted WR_BCCFG and WR_BCCTL
-**
-** Revision 1.4 1994/12/08 17:13:34 samberg
-** Add CSERVE_K_WR_BCCTL and CSERVE_K_WR_BCCFG
-**
-** Revision 1.3 1994/11/30 15:59:30 samberg
-** Use c-style comments for c compiler use
-**
-** Revision 1.2 1994/11/22 19:02:46 samberg
-** Add constants for ev4 backward compatibility
-**
-** Revision 1.2 1994/11/22 19:02:46 samberg
-** Add constants for ev4 backward compatibility
-**
-** Revision 1.1 1994/07/08 17:01:40 samberg
-** Initial revision
-**
-**
-*/
/*
-** Console Service (cserve) sub-function codes:
-*/
+ * Console Service (cserve) sub-function codes:
+ */
#define CSERVE_K_LDQP 0x01
#define CSERVE_K_STQP 0x02
#define CSERVE_K_JTOPAL 0x09
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
#ifndef DC21164FROMGASSOURCES_INCLUDED
#define DC21164FROMGASSOURCES_INCLUDED 1
-/*
-**
-** FACILITY:
-**
-** DECchip 21164 PALcode
-**
-** MODULE:
-**
-** dc21164.h
-**
-** MODULE DESCRIPTION:
-**
-** DECchip 21164 specific definitions
-**
-** AUTHOR: ER
-**
-** CREATION DATE: 24-Nov-1993
-**
-** $Id: dc21164FromGasSources.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $
-**
-** MODIFICATION HISTORY:
-**
-** $Log: dc21164FromGasSources.h,v $
-** Revision 1.1.1.1 1997/10/30 23:27:19 verghese
-** current 10/29/97
-**
-** Revision 1.1 1995/11/18 01:45:46 boyle
-** Initial revision
-**
-** Revision 1.15 1995/04/21 02:06:30 fdh
-** Replaced C++ style comments with Standard C style comments.
-**
-** Revision 1.14 1995/03/20 14:55:23 samberg
-** Add flushIc to make Roger Cruz's life easier.
-**
-** Revision 1.13 1994/12/14 15:52:48 samberg
-** Add slXmit and slRcv bit definitions
-**
-** Revision 1.12 1994/09/07 15:43:49 samberg
-** Changes for Makefile.vpp, take out OSF definition
-**
-** Revision 1.11 1994/07/26 17:38:35 samberg
-** Changes for SD164.
-**
-** Revision 1.10 1994/07/08 17:02:12 samberg
-** Changes to support platform specific additions
-**
-** Revision 1.8 1994/05/31 15:49:21 ericr
-** Moved ptKdebug from pt10 to pt13; pt10 is used in MCHK flows
-**
-** Revision 1.7 1994/05/26 19:29:51 ericr
-** Added BC_CONFIG definitions
-**
-** Revision 1.6 1994/05/25 14:27:25 ericr
-** Added physical bit to ldq_lp and stq_cp macros
-**
-** Revision 1.5 1994/05/20 18:07:50 ericr
-** Changed line comments to C++ style comment character
-**
-** Revision 1.4 1994/01/17 21:46:54 ericr
-** Added floating point register definitions
-**
-** Revision 1.3 1994/01/03 19:31:49 ericr
-** Added cache parity error status register definitions
-**
-** Revision 1.2 1993/12/22 20:42:35 eric
-** Added ptTrap, ptMisc and flag definitions
-** Added PAL shadow regsiter definitions
-**
-** Revision 1.1 1993/12/16 21:55:05 eric
-** Initial revision
-**
-**
-**--
-*/
-
-
/*
**
** INTERNAL PROCESSOR REGISTER DEFINITIONS
+++ /dev/null
-/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-#ifndef __EB164_H_LOADED
-#define __EB164_H_LOADED
-
-/*
- * $Id: eb164.h,v 1.1.1.1 1997/10/30 23:27:14 verghese Exp $;
- */
-
-/*
- * $Log: eb164.h,v $
- * Revision 1.1.1.1 1997/10/30 23:27:14 verghese
- * current 10/29/97
- *
- * Revision 1.3 1995/02/10 02:21:36 fdh
- * Corrected EB164 banner.
- *
- * Revision 1.2 1994/12/07 21:24:58 cruz
- * Added constant defining the maximum size of the BCache
- *
- * Revision 1.1 1994/11/23 19:47:30 cruz
- * Initial revision
- *
- *
- */
-
-#ifdef EB164
-
-#define BANNER "DECchip 21164 Evaluation Board (EB164) Debug Monitor"
-#define PROMPT "EB164> "
-
-/****************************************************************************
- * Basic *
- ****************************************************************************/
-
-#define NEEDPCI
-#define NEEDDEBUGGER
-#define NEEDFLOPPY
-
-/****************************************************************************
- * CIA (Part of CIA) definitions *
- ****************************************************************************/
-#include "cia.h"
-
-/****************************************************************************
- * Plug in cards, what does it have? *
- ****************************************************************************/
-/*
- * The Allied Telesis card is an ISA card based on the am79c960
- * chip.
- */
-#define ALLIED_TELESIS_AT_1500T
-
-/*
- * The DEC Etherworks ISA card is a LANCE like device.
- */
-#define DEC_ETHERWORKS
-
-#define NEED21040
-
-/****************************************************************************
- * ISA Address Space *
- ****************************************************************************/
-
-#define RTCBASE 0x70
-#define LEDPORT 0x80 /* JDR Microdevices P.O.S.T. Diagnostics Card. */
-
-
-/*
- * Allied telesis is optional. We treat it like an optional
- * am79c960 as far as the driver is concerned, see /h/am79c960.h
- * for more definitions and /ether/am79c960_device.c for the device
- * driver.
- */
-#ifdef ALLIED_TELESIS_AT_1500T
-#define OPTIONAL_AM79C960 /* warning only define this once - kmc */
-#define NEEDAM79C960 /* same for this */
-#define OPTIONAL_AM79C960_BASE 0x360
-#define OPTIONAL_AM79C960_INT 9
-
-/*
- * This parameter determines the
- * DMA Mask for the DMA2 controller.
- * Mask Channel
- * ---- -------
- * 1 5
- * 2 6
- * 3 7
- * 4 8
- */
-#define OPTIONAL_AM79C960_DMA 1 /* Selects DMA Channel 5 */
-#endif
-
-#ifdef DEC_ETHERWORKS
-#define DEC_ETHERWORKS_BASE 0x300
-#endif
-
-#ifdef DEC_ETHERWORKS
-#define DEC_ETHERWORKS_BASE 0x300
-#endif
-
-
-/****************************************************************************
- * System Address Space *
- ****************************************************************************/
-
-#define MINIMUM_SYSTEM_MEMORY 0x1000000 /* 16MB */
-#define MAXIMUM_SYSTEM_CACHE 0x800000 /* 8MB */
-#define DMA_BUFF_BASE 0x100000
-
-
-/****************************************************************************
- * PCI I/O Address Space *
- ****************************************************************************/
-/*
- * Definitions for the windows mapping PCI addresses into
- * system addresses
- *
- * 16 megabyte window starting at CPU address = 0.
- */
-
-#define PCI_BASE_1_USED 1
-#define PCI_BASE_1 0x000100000
-#define PCI_MASK_1 0x000000000
-#define PCI_TBASE_1 0x000100000
-
-#define PCI_BASE_2_USED 0
-#define PCI_BASE_2 0x000000000
-#define PCI_MASK_2 0x000000000
-#define PCI_TBASE_2 0x000000000
-
-#define PCI_BASE_3_USED 0
-#define PCI_BASE_3 0x000000000
-#define PCI_MASK_3 0x000000000
-#define PCI_TBASE_3 0x000000000
-
-#define PCI_BASE_4_USED 0
-#define PCI_BASE_4 0x000000000
-#define PCI_MASK_4 0x00000000
-#define PCI_TBASE_4 0x000000000
-
-/*
- * Each mask translates to a number of these units. For
- * APECS this unit is 1Kbyte.
- */
-#define PCI_MASK_UNIT 0x100000
-
-/*
- * Where do we start allocating addresses from in PCI I/O space?
- */
-#define PCI_IO_BASE 0xB000
-
-/*
- * ROM definitions.
- */
-#define NEEDFLASHMEMORY
-#define INTEL_28F008SA
-#define ROMBASE 0xFFF80000
-#define ROMSIZE 0x100000
-#define ROMINC 0x1
-
-#endif /* EB164 */
-#endif /* __EB164_H_LOADED */
-
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
#ifndef EV5_ALPHA_DEFS_INCLUDED
#define EV5_ALPHA_DEFS_INCLUDED 1
// from ev5_alpha_defs.mar from Lance's fetch directory
// Lower-caseified and $ signs removed ... pb Nov/95
-// .MACRO _ALPHADEFS
-// ALPHADEF_VER == 6 ; Flag the version number of this file.
-// .ENDM
-// .MACRO _PSDEF,_GBL
-// _DEFINI PS,_GBL
-//;+
-//; PS Layout - PS
-//; Loc Size name function
-//; ------ ------ ______ -----------------------------------
-//; <31:29> 3 SA stack alignment
-//; <31:13> 24 RES Reserved MBZ
-//; <12:8> 5 IPL Priority level
-//; <7> 1 VMM Virtual Mach Monitor
-//; <6:5> 2 RES Reserved MBZ
-//; <4:3> 2 CM Current Mode
-//; <2> 1 IP Interrupt Pending
-//; <1:0> 2 SW Software bits
-//;-
+//
+// PS Layout - PS
+// Loc Size name function
+// ------ ------ ______ -----------------------------------
+// <31:29> 3 SA stack alignment
+// <31:13> 24 RES Reserved MBZ
+// <12:8> 5 IPL Priority level
+// <7> 1 VMM Virtual Mach Monitor
+// <6:5> 2 RES Reserved MBZ
+// <4:3> 2 CM Current Mode
+// <2> 1 IP Interrupt Pending
+// <1:0> 2 SW Software bits
+//
#define ps_v_sw 0
#define ps_m_sw (3<<ps_v_sw)
#define ps_c_ipl30 (0x1E00)
#define ps_c_ipl31 (0x1F00)
-// _DEFEND PS,_GBL,DEF
-// .ENDM
-//;+
-//; PTE layout - symbol prefix PTE_
-//;
-//; Loc Size name function
-//; ------ ------ ------ -----------------------------------
-//; <63:32> 32 PFN Page Frame Number
-//; <31:16> 16 SOFT Bits reserved for software use
-//; <15> 1 UWE User write enable
-//; <14> 1 SWE Super write enable
-//; <13> 1 EWE Exec write enable
-//; <12> 1 KWE Kernel write enable
-//; <11> 1 URE User read enable
-//; <10> 1 SRE Super read enable
-//; <9> 1 ERE Exec read enable
-//; <8> 1 KRE Kernel read enable
-//; <7:6> 2 RES Reserved SBZ
-//; <5> 1 HPF Huge Page Flag
-//; <4> 1 ASM Wild card address space number match
-//; <3> 1 FOE Fault On execute
-//; <2> 1 FOW Fault On Write
-//; <1> 1 FOR Fault On Read
-//; <0> 1 V valid bit
-//;-
-// .MACRO _PTEDEF,_GBL
-// _DEFINI PTE,_GBL
+//
+// PTE layout - symbol prefix PTE_
+//
+// Loc Size name function
+// ------ ------ ------ -----------------------------------
+// <63:32> 32 PFN Page Frame Number
+// <31:16> 16 SOFT Bits reserved for software use
+// <15> 1 UWE User write enable
+// <14> 1 SWE Super write enable
+// <13> 1 EWE Exec write enable
+// <12> 1 KWE Kernel write enable
+// <11> 1 URE User read enable
+// <10> 1 SRE Super read enable
+// <9> 1 ERE Exec read enable
+// <8> 1 KRE Kernel read enable
+// <7:6> 2 RES Reserved SBZ
+// <5> 1 HPF Huge Page Flag
+// <4> 1 ASM Wild card address space number match
+// <3> 1 FOE Fault On execute
+// <2> 1 FOW Fault On Write
+// <1> 1 FOR Fault On Read
+// <0> 1 V valid bit
+//
#define pte_v_pfn 32
#define pte_m_soft (0xFFFF0000)
#define pte_m_v (0x0001)
#define pte_v_v 0
-// _DEFEND PTE,_GBL,DEF
-// .ENDM
-//;+
-//; VA layout - symbol prefix VA_
-//;
-//; Loc Size name function
-//; ------ ------ ------- -----------------------------------
-//; <42:33> 10 SEG1 First seg table offset for mapping
-//; <32:23> 10 SEG2 Second seg table offset for mapping
-//; <22:13> 10 SEG3 Third seg table offset for mapping
-//; <12:0> 13 OFFSET Byte within page
-//;-
-// .MACRO _VADEF,_GBL
-// _DEFINI VA,_GBL
+//
+// VA layout - symbol prefix VA_
+//
+// Loc Size name function
+// ------ ------ ------- -----------------------------------
+// <42:33> 10 SEG1 First seg table offset for mapping
+// <32:23> 10 SEG2 Second seg table offset for mapping
+// <22:13> 10 SEG3 Third seg table offset for mapping
+// <12:0> 13 OFFSET Byte within page
+//
#define va_m_offset (0x000000001FFF)
#define va_v_offset 0
#define va_m_seg1 (0x7FE00000000)
#define va_v_seg1 33
-// _DEFEND VA,_GBL,DEF
-// .ENDM
-//;+
-//; PRIVILEGED CONTEXT BLOCK (PCB)
-//;-
-// .MACRO _PCBDEF,_GBL
-// _DEFINI PCB,_GBL
+//
+//PRIVILEGED CONTEXT BLOCK (PCB)
+//
#define pcb_q_ksp 0
#define pcb_q_esp 8
#define pcb_q_ssp 16
#define pcb_v_dat 63
#define pcb_v_pme 62
-// _DEFEND PCB,_GBL,DEF
-// .ENDM
-//;+
-//; SYSTEM CONTROL BLOCK (SCB)
-//;-
-// .MACRO _SCBDEF,_GBL
-// _DEFINI SCB,_GBL
+//
+// SYSTEM CONTROL BLOCK (SCB)
+//
#define scb_v_fen (0x0010)
#define scb_v_acv (0x0080)
#define scb_v_procmchk (0x0670)
#define scb_v_passive_rel (0x06F0)
-// _DEFEND SCB,_GBL,DEF
-// .ENDM
-//;+
-//; Stack frame (FRM)
-//;-
-// .MACRO _FRMDEF,_GBL
-// _DEFINI FRM,_GBL
+//
+// Stack frame (FRM)
+//
#define frm_v_r2 (0x0000)
#define frm_v_r3 (0x0008)
#define frm_v_pc (0x0030)
#define frm_v_ps (0x0038)
-// _DEFEND FRM,_GBL,DEF
-// .ENDM
-//;+
-//; Exeception summary register (EXS)
-//;-
-// .MACRO _EXSDEF,_GBL
-// _DEFINI EXS,_GBL
+//
+// Exeception summary register (EXS)
+//
// exs_v_swc <0> ; Software completion
// exs_v_inv <1> ; Ivalid operation
// exs_v_dze <2> ; Div by zero
#define exs_m_ine (1<<exs_v_ine)
#define exs_m_iov (1<<exs_v_iov)
-// _defend exs,_gbl,def
-// .endm
-//;+
-//; machine check error summary register (mces)
-//;-
-// .macro _mcesdef,_gbl
-// _defini mces,_gbl
+//
+// machine check error summary register (mces)
+//
// mces_v_mchk <0> ; machine check in progress
// mces_v_sce <1> ; system correctable error
// mces_v_pce <2> ; processor correctable error
#define mces_m_dpc (1<<mces_v_dpc)
#define mces_m_dsc (1<<mces_v_dsc)
#define mces_m_all ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) | (1<<mces_v_dsc))
-// _defend mces,_gbl,def
-// .endm
-
-
#endif
/*
-Copyright 1995 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1995 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
#ifndef EV5_DEFS_INCLUDED
#define EV5_DEFS_INCLUDED 1
// adapted from the version emailed to lance..pb Nov/95
-
-// ********************************************************************************************************************************
-// Created 25-JUL-1995 14:21:23 by VAX SDL V3.2-12 Source: 21-JUL-1995 11:03:08 EV5$:[EV5.DVT.SUP]EV5_DEFS.SDL;24
-// ********************************************************************************************************************************
-
-// .MACRO $EV5DEF,..EQU=<=>,..COL=<:>
-// EV5$K_REVISION'..equ'34
-// In the definitions below, registers are annotated with one of the following
-// symbols:
+// In the definitions below, registers are annotated with one of the
+// following symbols:
//
-// RW - The register may be read and written
+// RW - The register may be read and written
// RO - The register may only be read
// WO - The register may only be written
//
-// For RO and WO registers, all bits and fields within the register are also
-// read-only or write-only. For RW registers, each bit or field within
-// the register is annotated with one of the following:
+// For RO and WO registers, all bits and fields within the register
+// are also read-only or write-only. For RW registers, each bit or
+// field within the register is annotated with one of the following:
//
// RW - The bit/field may be read and written
// RO - The bit/field may be read; writes are ignored
-// WO - The bit/field may be written; reads return an UNPREDICTABLE result.
+// WO - The bit/field may be written; reads return an UNPREDICTABLE result
// WZ - The bit/field may be written; reads return a 0
// WC - The bit/field may be read; writes cause state to clear
-// RC - The bit/field may be read, which also causes state to clear; writes are ignored
+// RC - The bit/field may be read, which also causes state to clear;
+// writes are ignored
// Architecturally-defined (SRM) registers for EVMS
+
#define pt0 320
#define pt1 321
#define pt2 322
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
#ifndef EV5_IMPURE_INCLUDED
#define EV5_IMPURE_INCLUDED
-/*
// This uses the Hudson file format from "impure.h" but with the fields from
// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95
-//orig file: impure.sdl
-//orig
-//orig Abstract: PAL impure scratch area and logout area data structure definitions for
-//orig Alpha firmware.
-//orig
-//orig
-//orig module $pal_impure;
-//orig
-//orig Edit Date Who Description
-//orig ---- --------- --- ---------------------
-//orig 1 7-Jul-93 JEM Initial Entry
-//orig 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area
-//orig Delete mvptbr
-//orig Calculate pal$logout from end of impure area
-//orig 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions
-//orig 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, pmctr_ctl;
-//orig add ic_perr_stat, pmctr, dc_perr_stat, sc_stat, sc_addr, sc_ctl,
-//orig bc_tag_addr, ei_stat, ei_addr, fill_syn, ld_lock
-//orig 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be consistent with ev4
-//orig add cns$ipr_offset
-//orig 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again.
-//orig 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant to mchk logout frame
-//orig
-//orig
-//orig constant REVISION equals 7 prefix IMPURE$; // Revision number of this file
+// file: impure.sdl
+//
+// PAL impure scratch area and logout area data structure definitions for
+// Alpha firmware.
+//
+//
+// module $pal_impure;
+//
+// Edit Date Who Description
+// ---- --------- --- ---------------------
+// 1 7-Jul-93 JEM Initial Entry
+// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area
+// Delete mvptbr
+// Calculate pal$logout from end of impure area
+// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions
+// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl,
+// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat,
+// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat,
+// ei_addr, fill_syn, ld_lock
+// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be
+// consistent with ev4
+// add cns$ipr_offset
+// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again.
+// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant
+// to mchk logout frame
+//
+//
+// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file
//orig
+/*
** Macros for saving/restoring data to/from the PAL impure scratch
** area.
**
** macros will auto-magically adjust the offsets accordingly.
**
*/
-#if 0
-#define SAVE_GPR(reg,offset,base) \
- stq_p reg, ((offset-0x200)&0x3FF)(base)
-
-#define RESTORE_GPR(reg,offset,base) \
- ldq_p reg, ((offset-0x200)&0x3FF)(base)
-
-
-#define SAVE_FPR(reg,offset,base) \
- stt reg, ((offset-0x200)&0x3FF)(base)
-
-#define RESTORE_FPR(reg,offset,base) \
- ldt reg, ((offset-0x200)&0x3FF)(base)
-
-#define SAVE_IPR(reg,offset,base) \
- mfpr v0, reg; \
- stq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base)
-
-#define RESTORE_IPR(reg,offset,base) \
- ldq_p v0, ((offset-CNS_Q_IPR)&0x3FF)(base); \
- mtpr v0, reg
-
-#define SAVE_SHADOW(reg,offset,base) \
- stq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
-
-#define RESTORE_SHADOW(reg,offset,base)\
- ldq_p reg, ((offset-CNS_Q_IPR)&0x3FF)(base)
-#else
//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X))
#define SEXT10(X) ((X) & 0x3ff)
//#define SEXT10(X) (((X) << 55) >> 55)
#define RESTORE_SHADOW(reg,offset,base)\
ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base)
-#endif
-/* orig Structure of the processor-specific impure area */
-/* orig aggregate impure struct prefix "" tag "";
- * orig cns$flag quadword;
- * orig cns$hlt quadword;
-*/
+/* Structure of the processor-specific impure area */
+
+/* aggregate impure struct prefix "" tag "";
+ * cns$flag quadword;
+ * cns$hlt quadword;
+ */
/* Define base for debug monitor compatibility */
#define CNS_Q_BASE 0x000
#define CNS_Q_HALT 0x108
-/* orig constant (
- * orig cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7,
- * orig cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15,
- * orig cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23,
- * orig cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31
- * orig ) equals . increment 8 prefix "" tag "";
- * orig cns$gpr quadword dimension 32;
-*/
+/* constant (
+ * cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7,
+ * cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15,
+ * cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23,
+ * cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31
+ * ) equals . increment 8 prefix "" tag "";
+ * cns$gpr quadword dimension 32;
+ */
+
/* Offset to base of saved GPR area - 32 quadword */
#define CNS_Q_GPR 0x110
#define cns_gpr CNS_Q_GPR
-/* orig constant (
- * orig cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7,
- * orig cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15,
- * orig cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23,
- * orig cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31
- * orig ) equals . increment 8 prefix "" tag "";
- * orig cns$fpr quadword dimension 32;
-*/
+/* constant (
+ * cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7,
+ * cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15,
+ * cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23,
+ * cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31
+ * ) equals . increment 8 prefix "" tag "";
+ * cns$fpr quadword dimension 32;
+ */
+
/* Offset to base of saved FPR area - 32 quadwords */
#define CNS_Q_FPR 0x210
-/* orig #t=.;
- * orig cns$mchkflag quadword;
-*/
+/* #t=.;
+ * cns$mchkflag quadword;
+ */
#define CNS_Q_MCHK 0x310
-/* orig constant cns$pt_offset equals .;
- * orig constant (
- * orig cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6,
- * orig cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13,
- * orig cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20,
- * orig cns$pt21,cns$pt22,cns$pt23
- * orig ) equals . increment 8 prefix "" tag "";
- * orig cns$pt quadword dimension 24;
-*/
+/* constant cns$pt_offset equals .;
+ * constant (
+ * cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6,
+ * cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13,
+ * cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20,
+ * cns$pt21,cns$pt22,cns$pt23
+ * ) equals . increment 8 prefix "" tag "";
+ * cns$pt quadword dimension 24;
+ */
/* Offset to base of saved PALtemp area - 25 quadwords */
#define CNS_Q_PT 0x318
-/* orig cns$shadow8 quadword;
- * orig cns$shadow9 quadword;
- * orig cns$shadow10 quadword;
- * orig cns$shadow11 quadword;
- * orig cns$shadow12 quadword;
- * orig cns$shadow13 quadword;
- * orig cns$shadow14 quadword;
- * orig cns$shadow25 quadword;
-*/
+/* cns$shadow8 quadword;
+ * cns$shadow9 quadword;
+ * cns$shadow10 quadword;
+ * cns$shadow11 quadword;
+ * cns$shadow12 quadword;
+ * cns$shadow13 quadword;
+ * cns$shadow14 quadword;
+ * cns$shadow25 quadword;
+ */
/* Offset to base of saved PALshadow area - 8 quadwords */
#define CNS_Q_SHADOW 0x3D8
/* Offset to base of saved IPR area */
#define CNS_Q_IPR 0x418
-/* orig constant cns$ipr_offset equals .; */
-/* orig cns$exc_addr quadword; */
+/* constant cns$ipr_offset equals .; */
+/* cns$exc_addr quadword; */
#define CNS_Q_EXC_ADDR 0x418
-/* orig cns$pal_base quadword; */
+/* cns$pal_base quadword; */
#define CNS_Q_PAL_BASE 0x420
-/* orig cns$mm_stat quadword; */
+/* cns$mm_stat quadword; */
#define CNS_Q_MM_STAT 0x428
-/* orig cns$va quadword; */
+/* cns$va quadword; */
#define CNS_Q_VA 0x430
-/* orig cns$icsr quadword; */
+/* cns$icsr quadword; */
#define CNS_Q_ICSR 0x438
-/* orig cns$ipl quadword; */
+/* cns$ipl quadword; */
#define CNS_Q_IPL 0x440
-/* orig cns$ps quadword; // Ibox current mode */
+/* cns$ps quadword; // Ibox current mode */
#define CNS_Q_IPS 0x448
-/* orig cns$itb_asn quadword; */
+/* cns$itb_asn quadword; */
#define CNS_Q_ITB_ASN 0x450
-/* orig cns$aster quadword; */
+/* cns$aster quadword; */
#define CNS_Q_ASTER 0x458
-/* orig cns$astrr quadword; */
+/* cns$astrr quadword; */
#define CNS_Q_ASTRR 0x460
-/* orig cns$isr quadword; */
+/* cns$isr quadword; */
#define CNS_Q_ISR 0x468
-/* orig cns$ivptbr quadword; */
+/* cns$ivptbr quadword; */
#define CNS_Q_IVPTBR 0x470
-/* orig cns$mcsr quadword; */
+/* cns$mcsr quadword; */
#define CNS_Q_MCSR 0x478
-/* orig cns$dc_mode quadword; */
+/* cns$dc_mode quadword; */
#define CNS_Q_DC_MODE 0x480
-/* orig cns$maf_mode quadword; */
+/* cns$maf_mode quadword; */
#define CNS_Q_MAF_MODE 0x488
-/* orig cns$sirr quadword; */
+/* cns$sirr quadword; */
#define CNS_Q_SIRR 0x490
-/* orig cns$fpcsr quadword; */
+/* cns$fpcsr quadword; */
#define CNS_Q_FPCSR 0x498
-/* orig cns$icperr_stat quadword; */
+/* cns$icperr_stat quadword; */
#define CNS_Q_ICPERR_STAT 0x4A0
-/* orig cns$pmctr quadword; */
+/* cns$pmctr quadword; */
#define CNS_Q_PM_CTR 0x4A8
-/* orig cns$exc_sum quadword; */
+/* cns$exc_sum quadword; */
#define CNS_Q_EXC_SUM 0x4B0
-/* orig cns$exc_mask quadword; */
+/* cns$exc_mask quadword; */
#define CNS_Q_EXC_MASK 0x4B8
-/* orig cns$intid quadword; */
+/* cns$intid quadword; */
#define CNS_Q_INT_ID 0x4C0
-/* orig cns$dcperr_stat quadword; */
+/* cns$dcperr_stat quadword; */
#define CNS_Q_DCPERR_STAT 0x4C8
-/* orig cns$sc_stat quadword; */
+/* cns$sc_stat quadword; */
#define CNS_Q_SC_STAT 0x4D0
-/* orig cns$sc_addr quadword; */
+/* cns$sc_addr quadword; */
#define CNS_Q_SC_ADDR 0x4D8
-/* orig cns$sc_ctl quadword; */
+/* cns$sc_ctl quadword; */
#define CNS_Q_SC_CTL 0x4E0
-/* orig cns$bc_tag_addr quadword; */
+/* cns$bc_tag_addr quadword; */
#define CNS_Q_BC_TAG_ADDR 0x4E8
-/* orig cns$ei_stat quadword; */
+/* cns$ei_stat quadword; */
#define CNS_Q_EI_STAT 0x4F0
-/* orig cns$ei_addr quadword; */
+/* cns$ei_addr quadword; */
#define CNS_Q_EI_ADDR 0x4F8
-/* orig cns$fill_syn quadword; */
+/* cns$fill_syn quadword; */
#define CNS_Q_FILL_SYN 0x500
-/* orig cns$ld_lock quadword; */
+/* cns$ld_lock quadword; */
#define CNS_Q_LD_LOCK 0x508
-/* orig cns$bc_ctl quadword; // shadow of on chip bc_ctl */
+/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */
#define CNS_Q_BC_CTL 0x510
-/* orig cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */
+/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */
#define CNS_Q_PM_CTL 0x518
-/* orig cns$bc_config quadword; // shadow of on chip bc_config */
+/* cns$bc_config quadword; // shadow of on chip bc_config */
#define CNS_Q_BC_CFG 0x520
-/* orig constant cns$size equals .;
- * orig
- * orig constant pal$impure_common_size equals (%x0200 +7) & %xfff8;
- * orig constant pal$impure_specific_size equals (.+7) & %xfff8;
- * orig constant cns$mchksize equals (.+7-#t) & %xfff8;
- * orig constant pal$logout_area equals pal$impure_specific_size ;
- * orig end impure;
+/* constant cns$size equals .;
+ *
+ * constant pal$impure_common_size equals (%x0200 +7) & %xfff8;
+ * constant pal$impure_specific_size equals (.+7) & %xfff8;
+ * constant cns$mchksize equals (.+7-#t) & %xfff8;
+ * constant pal$logout_area equals pal$impure_specific_size ;
+ * end impure;
*/
/* This next set of stuff came from the old code ..pb */
-/* orig
- * orig aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$;
- * orig SPROCESS bitfield length 1 ;
- * orig FILL_0 bitfield length 3 fill tag $$;
- * orig FRQ2 bitfield length 2 ;
- * orig FRQ1 bitfield length 2 ;
- * orig FRQ0 bitfield length 2 ;
- * orig CTL2 bitfield length 2 ;
- * orig CTL1 bitfield length 2 ;
- * orig CTL0 bitfield length 2 ;
- * orig FILL_1 bitfield length 16 fill tag $$;
- * orig FILL_2 bitfield length 32 fill tag $$;
- * orig end EV5PMCTRCTL_BITS;
- * orig
- * orig end_module $pal_impure;
- * orig
- * orig module $pal_logout;
- * orig
- * orig //
- * orig // Start definition of Corrected Error Frame
- * orig //
+/*
+ * aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$;
+ * SPROCESS bitfield length 1 ;
+ * FILL_0 bitfield length 3 fill tag $$;
+ * FRQ2 bitfield length 2 ;
+ * FRQ1 bitfield length 2 ;
+ * FRQ0 bitfield length 2 ;
+ * CTL2 bitfield length 2 ;
+ * CTL1 bitfield length 2 ;
+ * CTL0 bitfield length 2 ;
+ * FILL_1 bitfield length 16 fill tag $$;
+ * FILL_2 bitfield length 32 fill tag $$;
+ * end EV5PMCTRCTL_BITS;
+ *
+ * end_module $pal_impure;
+ *
+ * module $pal_logout;
+ *
+ * //
+ * // Start definition of Corrected Error Frame
+ * //
*/
/*
- * orig aggregate crd_logout struct prefix "" tag "";
+ * aggregate crd_logout struct prefix "" tag "";
*/
-#ifdef SIMOS
#define pal_logout_area 0x600
#define mchk_crd_base 0
-#endif
-/* orig mchk$crd_flag quadword; */
+/* mchk$crd_flag quadword; */
#define mchk_crd_flag 0
-/* orig mchk$crd_offsets quadword; */
+/* mchk$crd_offsets quadword; */
#define mchk_crd_offsets 8
-/* orig
- * orig // Pal-specific information */
+/*
+ * // Pal-specific information */
#define mchk_crd_mchk_code 0x10
-/* orig mchk$crd_mchk_code quadword;
- * orig
- * orig // CPU-specific information
- * orig constant mchk$crd_cpu_base equals . ;
- * orig mchk$crd_ei_addr quadword; */
+/* mchk$crd_mchk_code quadword;
+ *
+ * // CPU-specific information
+ * constant mchk$crd_cpu_base equals . ;
+ * mchk$crd_ei_addr quadword; */
#define mchk_crd_ei_addr 0x18
-/* orig mchk$crd_fill_syn quadword; */
+/* mchk$crd_fill_syn quadword; */
#define mchk_crd_fill_syn 0x20
-/* orig mchk$crd_ei_stat quadword; */
+/* mchk$crd_ei_stat quadword; */
#define mchk_crd_ei_stat 0x28
-/* orig mchk$crd_isr quadword; */
+/* mchk$crd_isr quadword; */
#define mchk_crd_isr 0x30
/*
#define mchk_crd_rsvd 0x70
-#ifdef SIMOS
/*
* mchk area seems different for tlaser
*/
#define mchk_tlepmerr 0x18
-#endif
-
-
-/* orig
- * orig // System-specific information
- * orig constant mchk$crd_sys_base equals . ;
- * orig constant mchk$crd_size equals (.+7) & %xfff8;
- * orig
- * orig end crd_logout;
- * orig //
- * orig // Start definition of Machine check logout Frame
- * orig //
- * orig aggregate logout struct prefix "" tag "";
- * orig mchk$flag quadword; */
-/* orig mchk$offsets quadword; */
-/* orig
- * orig // Pal-specific information
- * orig mchk$mchk_code quadword; */
+/*
+ * // System-specific information
+ * constant mchk$crd_sys_base equals . ;
+ * constant mchk$crd_size equals (.+7) & %xfff8;
+ *
+ * end crd_logout;
+ * //
+ * // Start definition of Machine check logout Frame
+ * //
+ * aggregate logout struct prefix "" tag "";
+ * mchk$flag quadword; */
+/* mchk$offsets quadword; */
+/*
+ * // Pal-specific information
+ * mchk$mchk_code quadword; */
/*
- * orig mchk$pt quadword dimension 24;
- * orig
- * orig // CPU-specific information
- * orig constant mchk$cpu_base equals . ;
- * orig mchk$exc_addr quadword;
- * orig mchk$exc_sum quadword;
- * orig mchk$exc_mask quadword;
- * orig mchk$pal_base quadword;
- * orig mchk$isr quadword;
- * orig mchk$icsr quadword;
- * orig mchk$ic_perr_stat quadword;
- * orig mchk$dc_perr_stat quadword;
- * orig mchk$va quadword;
- * orig mchk$mm_stat quadword;
- * orig mchk$sc_addr quadword;
- * orig mchk$sc_stat quadword;
- * orig mchk$bc_tag_addr quadword;
- * orig mchk$ei_addr quadword;
- * orig mchk$fill_syn quadword;
- * orig mchk$ei_stat quadword;
- * orig mchk$ld_lock quadword;
- * orig
- * orig // System-specific information
- * orig
- * orig constant mchk$sys_base equals . ;
- * orig mchk$sys_ipr1 quadword ; // Holder for system-specific stuff
- * orig
- * orig constant mchk$size equals (.+7) & %xfff8;
- * orig
- * orig
- * orig constant mchk$crd_base equals 0 ;
- * orig constant mchk$mchk_base equals mchk$crd_size ;
- * orig
- * orig
- * orig end logout;
- * orig
- * orig end_module $pal_logout;
+ * mchk$pt quadword dimension 24;
+ *
+ * // CPU-specific information
+ * constant mchk$cpu_base equals . ;
+ * mchk$exc_addr quadword;
+ * mchk$exc_sum quadword;
+ * mchk$exc_mask quadword;
+ * mchk$pal_base quadword;
+ * mchk$isr quadword;
+ * mchk$icsr quadword;
+ * mchk$ic_perr_stat quadword;
+ * mchk$dc_perr_stat quadword;
+ * mchk$va quadword;
+ * mchk$mm_stat quadword;
+ * mchk$sc_addr quadword;
+ * mchk$sc_stat quadword;
+ * mchk$bc_tag_addr quadword;
+ * mchk$ei_addr quadword;
+ * mchk$fill_syn quadword;
+ * mchk$ei_stat quadword;
+ * mchk$ld_lock quadword;
+ *
+ * // System-specific information
+ *
+ * constant mchk$sys_base equals . ;
+ * mchk$sys_ipr1 quadword ; // Holder for system-specific stuff
+ *
+ * constant mchk$size equals (.+7) & %xfff8;
+ *
+ *
+ * constant mchk$crd_base equals 0 ;
+ * constant mchk$mchk_base equals mchk$crd_size ;
+ *
+ *
+ * end logout;
+ *
+ * end_module $pal_logout;
*/
-
-
-
-/* this is lingering in the old ladbx code but looks like it was from ev4 days.
- * This was 0x160 in the old days..pb
-*/
+/*
+ * this is lingering in the old ladbx code but looks like it was from
+ * ev4 days. This was 0x160 in the old days..pb
+ */
#define LAF_K_SIZE MACHINE_CHECK_SIZE
#endif
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
#ifndef EV5_OSFALPHA_DEFS_INCLUDED
#define EV5_OSFALPHA_DEFS_INCLUDED 1
-
// from ev5_osfalpha_defs.mar from Lance's fetch directory
// lowercaseified and $ changed to _ and reformatting for gas...pb Nov/95
-//orig .MACRO $OSF_ALPHADEFS
-//orig OSF_ALPHADEF_VER == 5 ; Flag the version number of this file.
-//orig .ENDM
-//orig .MACRO $OSF_PSDEF,$GBL
-//orig $DEFINI OSFPS,$GBL
-//orig;+
-//orig; PS Layout - PS
-//orig; Loc Size name function
-//orig; ------ ------ ----- -----------------------------------
-//orig; <0:2> 3 IPL Prio level
-//orig; <3> 1 CM Current Mode
-//orig;-
+//
+// PS Layout - PS
+// Loc Size name function
+// ------ ------ ----- -----------------------------------
+// <0:2> 3 IPL Prio level
+// <3> 1 CM Current Mode
+//
#define osfps_v_mode 3
#define osfps_m_mode (1<<osfps_v_mode)
#define osfint_c_perf 4
#define osfint_c_passrel 5
-//orig _DEFEND OSFPS,_GBL,DEF
-//orig .ENDM
-
-//orig;+
-//orig; PTE layout - symbol prefix osfpte_
-//orig;
-//orig; Loc Size name function
-//orig; ------ ------ ------ -----------------------------------
-//orig; <63:32> 32 PFN Page Frame Number
-//orig; <31:16> 16 SOFT Bits reserved for software use
-//orig; <15:14> 2
-//orig; <13> 1 UWE User write enable
-//orig; <12> 1 KWE Kernel write enable
-//orig; <11:10> 2
-//orig; <9> 1 URE User read enable
-//orig; <8> 1 KRE Kernel read enable
-//orig; <7:6> 2 RES Reserved SBZ
-//orig; <5> 1 HPF Huge Page Flag
-//orig; <4> 1 ASM Wild card address space number match
-//orig; <3> 1 FOE Fault On execute
-//orig; <2> 1 FOW Fault On Write
-//orig; <1> 1 FOR Fault On Read
-//orig; <0> 1 V valid bit
-//orig;-
-
-//orig .MACRO _OSF_PTEDEF,_GBL
-//orig _DEFINI OSFPTE,_GBL
+//
+// PTE layout - symbol prefix osfpte_
+//
+// Loc Size name function
+// ------ ------ ------ -----------------------------------
+// <63:32> 32 PFN Page Frame Number
+// <31:16> 16 SOFT Bits reserved for software use
+// <15:14> 2
+// <13> 1 UWE User write enable
+// <12> 1 KWE Kernel write enable
+// <11:10> 2
+// <9> 1 URE User read enable
+// <8> 1 KRE Kernel read enable
+// <7:6> 2 RES Reserved SBZ
+// <5> 1 HPF Huge Page Flag
+// <4> 1 ASM Wild card address space number match
+// <3> 1 FOE Fault On execute
+// <2> 1 FOW Fault On Write
+// <1> 1 FOR Fault On Read
+// <0> 1 V valid bit
+//
#define osfpte_v_pfn 32
#define osfpte_m_soft (0xFFFF0000)
#define osfpte_m_ksegbits (osfpte_m_kre | osfpte_m_kwe | osfpte_m_v | osfpte_m_asm)
#define osfpte_m_prot (osfpte_m_ure+osfpte_m_uwe | osfpte_m_kre | osfpte_m_kwe)
-//orig _DEFEND OSFPTE,_GBL,DEF
-//orig .ENDM
-
-//orig;+
-//orig; VA layout - symbol prefix VA_
-//orig;
-//orig; Loc Size name function
-//orig; ------ ------ ------- -----------------------------------
-//orig; <42:33> 10 SEG1 First seg table offset for mapping
-//orig; <32:23> 10 SEG2 Second seg table offset for mapping
-//orig; <22:13> 10 SEG3 Third seg table offset for mapping
-//orig; <12:0> 13 OFFSET Byte within page
-//orig;-
-//orig .MACRO _OSF_VADEF,_GBL
-//orig _DEFINI OSFVA,_GBL
+//
+// VA layout - symbol prefix VA_
+//
+// Loc Size name function
+// ------ ------ ------- -----------------------------------
+// <42:33> 10 SEG1 First seg table offset for mapping
+// <32:23> 10 SEG2 Second seg table offset for mapping
+// <22:13> 10 SEG3 Third seg table offset for mapping
+// <12:0> 13 OFFSET Byte within page
+//
#define osfva_m_offset (0x000000001FFF)
#define osfva_v_offset 0
#define osfva_m_seg1 (0x7FE00000000)
#define osfva_v_seg1 33
-//orig _DEFEND OSFVA,_GBL,DEF
-//orig .ENDM
-//orig;+
-//orig; PRIVILEGED CONTEXT BLOCK (PCB)
-//orig;-
-//orig .MACRO _OSF_PCBDEF,_GBL
-//orig _DEFINI OSFPCB,_GBL
-
#define osfpcb_q_ksp (0x0000)
#define osfpcb_q_usp (0x0008)
#define osfpcb_q_Usp (0x0008)
#define osfpcb_q_fen (0x0028)
#define osfpcb_v_pme 62
-//orig _DEFEND OSFPCB,_GBL,DEF
-//orig .ENDM
-//orig;+
-//orig; Stack Frame
-//orig;-
-//orig .MACRO _OSF_SFDEF,_GBL
-//orig _DEFINI OSFSF,_GBL
-
#define osfsf_ps (0x00)
#define osfsf_pc (0x08)
#define osfsf_gp (0x10)
#define osfsf_a2 (0x28)
#define osfsf_c_size (0x30)
-//orig _DEFEND OSFSF,_GBL,DEF
-//orig .ENDM
-
#endif
/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
#ifndef EV5_PALDEF_INCLUDED
#define EV5_PALDEF_INCLUDED 1
// from ev5_paldef.mar from Lance's fetch directory...pb Nov/95
// some entries have been superceeded by the more recent evt_defs.h
-// These are lower-caseified and have the $ signs (unnecessarily we now discover) removed.
+// These are lower-caseified and have the $ signs (unnecessarily we
+// now discover) removed.
// Note that at the bottom of this file is the version of ev5_defs.mar
-// which is more recent than the top part of the file and contains overlapping information...pb Nov/95
-
-// .MACRO PALDEFS
-// PALDEF_VER == 1 ; Flag the version number of this file.
-// .ENDM
-//
-//
-// .MACRO _HALT_CODES,_GBL
-// _DEFINI HALT_CODES,_GBL
+// which is more recent than the top part of the file and contains
+// overlapping information...pb Nov/95
#define hlt_c_reset 0
#define hlt_c_hw_halt 1
#define hlt_c_mpstart 34
#define hlt_c_lfu_start 35
-// halt codes above 255 reserved for platform specific errors
-// _DEFEND HALT_CODES,_GBL,DEF
-// .ENDM
-// .MACRO _MCHK_CODES,_GBL
-// _DEFINI MCHK_CODES,_GBL
-
#define mchk_c_tperr (64<<1)
#define mchk_c_tcperr (65<<1)
#define mchk_c_herr (66<<1)
#define mchk_c_sys_hrd_error (257<<1)
#define mchk_c_sys_ecc (258<<1)
-// _DEFEND MCHK_CODES,_GBL,DEF
-// .ENDM
-
-// .MACRO _EV5_MM,_GBL
-// _DEFINI _EV5_MM,_GBL
-
#define page_seg_size_bits 10
#define page_offset_size_bits 13
#define page_size_bytes 8192
#define va_size_bits 43
#define pa_size_bits 45
-// _DEFEND _EV5_MM,_GBL,DEF
-// .ENDM
-
-// .MACRO _PALTEMP,_GBL
-// _DEFINI _PALTEMP,_GBL
-
// replaced by ev5_defs.h #define pt0 (0x140)
// replaced by ev5_defs.h #define pt1 (0x141)
// replaced by ev5_defs.h #define pt2 (0x142)
#define pt_misc_v_switch 48
#define pt_misc_v_cm 56
-// _DEFEND _PALTEMP,_GBL,DEF
-// .ENDM
-
-// .MACRO _OSF_MMCSR_DEF,_GBL
-// _DEFINI OSFMMCSR,_GBL
-
#define mmcsr_c_tnv 0
#define mmcsr_c_acv 1
#define mmcsr_c_for 2
#define mmcsr_c_foe 3
#define mmcsr_c_fow 4
-// _DEFEND OSFMMCSR,_GBL,DEF
-// .ENDM
-
-// .MACRO _MM_STAT_DEF,_GBL
-// _DEFINI MMSTATDEF,_GBL
-
#define mm_stat_m_opcode (0x3F)
#define mm_stat_m_ra (0x1F)
#define evx_opc_sync (0x18)
#define EVX_OPC_SYNC (0x18)
#define evx_opc_hw_ld (0x1B)
-// _DEFEND MMSTATDEF,_GBL,DEF
-// .ENDM
-
-// .MACRO _OSF_A0_DEF,_GBL
-// _DEFINI OSFA0DEF,_GBL
-
#define osf_a0_bpt (0x0)
#define osf_a0_bugchk (0x1)
#define osf_a0_gentrap (0x2)
#define osf_a0_fen (0x3)
#define osf_a0_opdec (0x4)
-// _DEFEND OSFA0DEF,_GBL,DEF
-// .ENDM
-
-// .MACRO _EV5_IPLDEF,_GBL
-// _DEFINI EV5_IPLDEF,_GBL
-
#define ipl_machine_check 31
#define ipl_powerfail 30
#define ipl_perf_count 29
#define ipl_clock 22
#define ipl_interprocessor 22
-// _DEFEND EV5_IPLDEF,_GBL,DEF
-// .ENDM
-
#endif
/*
-Copyright 1993, 1994 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1993, 1994 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
#ifndef HUDSON_MACROS_LOADED
#define HUDSON_MACROS_LOADED 1
-/*
- * VID: [T1.2] PT: [Fri Apr 21 16:47:16 1995] SF: [macros.h]
- * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
- */
-/*
-**
-** FACILITY:
-**
-** DECchip 21164 PALcode
-**
-** MODULE:
-**
-** macros.h
-**
-** MODULE DESCRIPTION:
-**
-** DECchip 21164 PALcode macro definitions
-**
-** AUTHOR: ER
-**
-** CREATION DATE: 29-Nov-1993
-**
-** $Id: fromHudsonMacros.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $
-**
-** MODIFICATION HISTORY:
-**
-** $Log: fromHudsonMacros.h,v $
-** Revision 1.1.1.1 1997/10/30 23:27:19 verghese
-** current 10/29/97
-**
-** Revision 1.1 1995/11/18 01:46:23 boyle
-** Initial revision
-**
-** Revision 1.5 1994/07/08 17:03:12 samberg
-** Changes to support platform specific additions
-**
-** Revision 1.4 1994/05/20 19:24:19 ericr
-** Moved STALL macro from osfpal.s to here
-** Added LDLI macro
-**
-** Revision 1.3 1994/05/20 18:08:14 ericr
-** Changed line comments to C++ style comment character
-**
-** Revision 1.2 1994/02/28 18:45:51 ericr
-** Fixed EGORE related bugs
-**
-** Revision 1.1 1993/12/16 21:55:05 eric
-** Initial revision
-**
-**
-**--
-*/
-
#define STALL \
mfpr r31, pt0
ldah reg, ((val+0x8000) >> 16)(zero); \
lda reg, (val&0xffff)(reg)
-
-
#endif
/*
-Copyright 1993, 1994 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1993, 1994 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
#ifndef FROMHUDSONOSF_INCLUDED
#define FROMHUDSONOSF_INCLUDED 1
-/*
- * VID: [T1.2] PT: [Fri Apr 21 16:47:14 1995] SF: [osf.h]
- * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
- */
-#define __OSF_LOADED 1
-/*
-**
-** FACILITY:
-**
-** DECchip 21164 PALcode
-**
-** MODULE:
-**
-** osf.h
-**
-** MODULE DESCRIPTION:
-**
-** OSF/1 specific definitions
-**
-** AUTHOR: ER
-**
-** CREATION DATE: 24-Nov-1993
-**
-** $Id: fromHudsonOsf.h,v 1.1.1.1 1997/10/30 23:27:19 verghese Exp $
-**
-** MODIFICATION HISTORY:
-**
-** $Log: fromHudsonOsf.h,v $
-** Revision 1.1.1.1 1997/10/30 23:27:19 verghese
-** current 10/29/97
-**
-** Revision 1.1 1995/11/18 01:46:31 boyle
-** Initial revision
-**
-** Revision 1.11 1995/04/21 02:06:30 fdh
-** Replaced C++ style comments with Standard C style comments.
-**
-** Revision 1.10 1994/09/26 14:17:47 samberg
-** Complete VICE work and EB164/SD164 breakout.
-**
-** Revision 1.9 1994/07/26 17:39:10 samberg
-** Changes for SD164.
-**
-** Revision 1.8 1994/07/08 17:03:48 samberg
-** Changes to support platform specific additions
-**
-** Revision 1.7 1994/05/20 19:23:51 ericr
-** Moved STACK_FRAME macro from osfpal.s to here
-**
-** Revision 1.6 1994/05/20 18:08:19 ericr
-** Changed line comments to C++ style comment character
-**
-** Revision 1.5 1994/01/11 18:43:33 ericr
-** Removed PAL version/revision and size constants
-**
-** Revision 1.4 1994/01/05 16:22:32 ericr
-** Added more SCB vector offsets and MCHK error code
-**
-** Revision 1.3 1994/01/03 19:35:40 ericr
-** Derive mask definitions from field constants
-**
-** Revision 1.2 1993/12/22 20:43:01 eric
-** Added mask definitions for MCES bits
-**
-** Revision 1.1 1993/12/16 21:55:05 eric
-** Initial revision
-**
-**
-**--
-*/
+#define __OSF_LOADED 1
/*
** Seg0 and Seg1 Virtual Address (VA) Format
**
+++ /dev/null
-/*
-Copyright 1993, 1994Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-
-#ifndef __LIB_H_LOADED
-#define __LIB_H_LOADED
-
-/*
- * $Id: lib.h,v 1.1.1.1 1997/10/30 23:27:16 verghese Exp $;
- */
-
-/*
- * $Log: lib.h,v $
- * Revision 1.1.1.1 1997/10/30 23:27:16 verghese
- * current 10/29/97
- *
- * Revision 1.1 1995/06/23 00:18:57 berc
- * Initial revision
- *
- * Revision 1.29 1995/04/05 21:46:10 cruz
- * Added EB164 prototype for wr_bcache().
- *
- * Revision 1.28 1995/04/03 18:35:32 cruz
- * Extended the prototype definition of cserv.
- *
- * Revision 1.27 1995/03/05 04:17:23 fdh
- * Corrected prototype for inrom().
- *
- * Revision 1.26 1995/02/28 03:05:53 fdh
- * Moved rom.c prototypes to rom.h
- *
- * Revision 1.25 1995/02/27 19:21:27 fdh
- * Added prototypes for Ctype routines.
- *
- * Revision 1.24 1995/02/23 21:48:31 fdh
- * Added prototypes for set_haxr() and atoi().
- *
- * Revision 1.23 1995/02/22 22:01:10 fdh
- * Changed types for tolower() and toupper().
- *
- * Revision 1.22 1995/02/19 17:46:01 fdh
- * Changed one of the arguments to read_rom().
- *
- * Revision 1.21 1995/02/10 02:23:20 fdh
- * Added prototype for set_romboot().
- *
- * Revision 1.20 1994/11/19 03:30:51 fdh
- * Added support for romlist command.
- *
- * Revision 1.19 1994/11/18 19:05:31 fdh
- * swpipl returns the current ipl.
- *
- * Revision 1.18 1994/11/08 21:39:20 fdh
- * Added declaration for the flash routine.
- *
- * Revision 1.17 1994/11/01 11:30:01 rusling
- * Changed following PCI-PCI bridge support.
- *
- * Revision 1.16 1994/08/05 20:13:47 fdh
- * Updated Copyright header and RCS $Id: identifier.
- *
- * Revision 1.15 1994/08/03 19:44:23 fdh
- * Fixups around the linker defined symbols _edata and _end.
- * Protect time_t definition with #ifndef _TIME_T.
- *
- * Revision 1.14 1994/07/22 21:02:46 fdh
- * Added extern void rtcBaseInit(void); for EB64 builds.
- *
- * Revision 1.13 1994/07/21 18:10:06 fdh
- * >> Added EnableBCache(), DisableBCache(), and CleanBCache().
- *
- * Revision 1.12 1994/07/13 14:17:07 fdh
- * Added data structure for holding pointers to SROM interface
- * parameters.
- *
- * Revision 1.11 1994/06/28 20:08:21 fdh
- * Modified filenames and build precedure to fit into a FAT filesystem.
- *
- * Revision 1.10 1994/06/22 15:10:34 rusling
- * Fixed up WNT compile warnings.
- *
- * Revision 1.9 1994/06/21 15:27:47 rusling
- * Removed putFloat() prototype.
- *
- * Revision 1.8 1994/06/21 14:18:05 rusling
- * changed definition of loadHeader() in rom.c
- *
- * Revision 1.7 1994/06/21 10:38:53 rusling
- * Added strncmp() for WNT.
- *
- * Revision 1.5 1994/06/20 14:18:59 fdh
- * Fixup header file preprocessor #include conditionals.
- *
- * Revision 1.4 1994/06/17 19:34:01 fdh
- * Clean-up...
- *
- * Revision 1.3 1994/06/13 15:54:35 fdh
- * Added definitions of unsigned amounts as defined in system.h
- * Definitions are also placed here to make the lib subdirectory
- * free-standing from the rest of the source tree.
- *
- * Revision 1.2 1994/06/03 20:18:38 fdh
- * Added protypes for all routines in /lib.
- *
- * Revision 1.1 1994/01/19 10:33:21 rusling
- * Initial revision
- *
- * Revision 1.1 1993/06/08 19:56:14 fdh
- * Initial revision
- *
- */
-
-#include <stddef.h>
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-/*
- * Definitions of unsigned amounts
- */
-#define ub unsigned char
-#define uw unsigned short int
-
-#ifdef _WIN32
-#define ul unsigned __int64
-#define sl __int64
-#define ui unsigned int
-#else
-#define ul unsigned long
-#define sl long
-#define ui unsigned int
-#endif
-
-typedef struct {
- ul *abox_ctl;
-#ifdef DC21064
- ul *biu_ctl;
-#endif /* DC21064 */
-#ifdef DC21066
- ui *bcr0;
- ui *bcr1;
- ui *bcr2;
- ui *bcr3;
- ui *bmr0;
- ui *bmr1;
- ui *bmr2;
- ui *bmr3;
-#endif /* DC21066 */
- ul *srom_rev;
- ul *proc_id;
- ul *mem_size;
- ul *cycle_cnt;
- ul *signature;
- ul *proc_mask;
- ul *sysctx;
- int valid;
-} sysdata_t;
-
-#ifdef _WIN32
-extern ul end;
-extern ul edata;
-#define _END end
-#define _EDATA edata
-#else
-extern ul _end;
-extern ul _edata;
-#define _END _end
-#define _EDATA _edata
-#endif
-
-#ifndef _TIME_T
-#define _TIME_T
-typedef int time_t;
-/* typedef ui time_t; */
-#endif
-
-/*::::::::::::::
-rw.c
-::::::::::::::*/
-/* Here B = 8 bits, W = 16 bits, L = 32 bits, Q = 64 bits */
-extern ub ReadB(ub * adr);
-extern uw ReadW(uw * adr);
-extern void WriteB(ub * adr , ub data);
-extern void WriteW(uw * adr , uw data);
-
-/*::::::::::::::
-beep.c
-::::::::::::::*/
-extern void tone(int period , int time);
-extern void dummy(int x);
-extern void Beep(int msec , int freq);
-extern void msleep(int ms);
-
-/*::::::::::::::
-c8514.c
-::::::::::::::*/
-extern int c8514init(void);
-extern void c8514erase(void);
-extern void c8514putc(char c);
-extern void c8514show(void);
-extern void c8514hide(void);
-extern void c8514insfontchar(int code , ub * s);
-extern void initfont(void);
-
-/*::::::::::::::
-date.c
-::::::::::::::*/
-extern void printDate(void);
-extern void setDate(ub * date);
-extern ui gettime(void);
-//extern time_t time(void);
-extern void CheckDate(void);
-
-/*::::::::::::::
-initdata.c
-::::::::::::::*/
-extern void doinitdata(void );
-
-/*::::::::::::::
-ebxx_io.c
-::::::::::::::*/
-extern void outportb(ul p , ui d);
-extern void outportw(ul p , ui d);
-extern void outportt(ul p , ui d);
-extern void outportl(ul p , ui d);
-extern void outportbxt(ul p , ui d);
-extern void outport(ul p , ui d);
-extern void outcfgb(ui bus, ui dev, ui reg, ui data);
-extern void outcfgw(ui bus, ui dev, ui reg, ui data);
-extern void outcfgl(ui bus, ui dev, ui reg, ui data);
-extern void outmembxt(ul p , ui d);
-extern void outmemwat(ul p , ui d);
-extern ui inportb(ul p);
-extern ui inportw(ul p);
-extern ui inportt(ul p);
-extern ui inportl(ul p);
-extern ui inportwat(ul p);
-extern ui inportbxt(ul p);
-extern ui inport(ul p);
-extern ui incfgb(ui bus, ui dev, ui reg);
-extern ui incfgw(ui bus, ui dev, ui reg);
-extern ui incfgl(ui bus, ui dev, ui reg);
-extern ui inmembat(ul p);
-extern ui inmembxt(ul p);
-extern void IOBusInit(void);
-extern ul IOPCIClearNODEV(void);
-extern void outLed(ui d);
-extern void out_ioc_csr(ui p , ul d);
-extern ul in_ioc_csr(ui p);
-extern void outmemb(ul p , ui d);
-extern void outmemw(ul p , ui d);
-extern void outmemt(ul p , ui d);
-extern void outmeml(ul p , ui d);
-extern void outmem(ul p , ui d);
-extern ui inmemb(ul p);
-extern ui inmemw(ul p);
-extern ui inmemt(ul p);
-extern ul inmeml(ul p);
-extern ui inmemwat(ul p);
-extern ui inmem(ul p);
-extern void set_haxr(unsigned int addr);
-extern void outVti(ul p , ui d);
-extern ui inVti(ul p);
-extern ub inrom(ul p);
-extern ui insctl(void);
-extern void outsctl(ui d);
-extern ui inIack(void);
-#ifdef EB64
-extern void rtcBaseInit(void);
-#endif
-
-/*::::::::::::::
-ebxx_mem.c
-::::::::::::::*/
-extern void memdetect(void);
-extern int check_mem_esr(int silent);
-#ifdef EB66
-extern void out_mem_csr(ul p , ul d);
-extern ul in_mem_csr(ui p);
-#elif EB64P
-extern void out_mem_csr(ui p , ui d);
-extern ui in_mem_csr(ui p);
-#endif
-
-extern void EnableBCache(void);
-extern void DisableBCache(void);
-
-#ifdef EB164
-void wr_bcache (ui argc, ul arg1, ul arg2, ui select);
-#endif
-
-/*::::::::::::::
-ffcsubs.c
-::::::::::::::*/
-extern size_t strlen(const char *s);
-#if 0
-extern void bzero(void *s, int count);
-extern void bcopy(void *from, void *to, int count);
-#endif
-extern int tolower(int c);
-extern int toupper(int c);
-extern int IsAlpha(char c);
-extern int IsDigit(char c);
-
-/*::::::::::::::
-fftty.c
-::::::::::::::*/
-extern void UnGetChar(char c);
-extern char MonGetChar(void);
-extern void FlushLine(void);
-extern ul ReadHex(void);
-extern void ReadString(char * s);
-extern char RawMonGetChar(void);
-extern int kbdcontinue(void );
-
-/*::::::::::::::
-floppy.c
-::::::::::::::*/
-extern int floppyRead(int loadtype , char * file2load);
-
-/*::::::::::::::
-gpchar.c
-::::::::::::::*/
-extern void PutChar(char c);
-extern char GetChar(void);
-extern int CharAv(void);
-extern void WaitUs(int usecs);
-
-/*::::::::::::::
-ident.c
-::::::::::::::*/
-extern int ident(ul first , ul last);
-
-/*::::::::::::::
-int.c
-::::::::::::::*/
-extern void intr_enable(int int_level);
-
-/*::::::::::::::
-kbd.c
-::::::::::::::*/
-extern void kbd_error(char * error_msg , int s1);
-extern int kbd_init(void);
-extern void kbd_reset_state(void);
-extern int kbd_charav(void);
-extern int kbd_getc(void);
-
-/*::::::::::::::
-leds.c
-::::::::::::::*/
-extern void sethdled(int v);
-extern int isturbo(void);
-extern int kbd_locked(void);
-
-/*::::::::::::::
-memtest.c
-::::::::::::::*/
-extern ul do_memtest(char * llim , char * hlim , int inc);
-extern void memtest1(char * llim , char * hlim , int inc , int pattern);
-extern void memtest2(char * llim , char * hlim , int inc , int seed);
-extern void memtest3(char * llim , char * hlim , int inc);
-extern void memtest(char * min , char * max , int inc);
-
-/*::::::::::::::
-p8514.c
-::::::::::::::*/
-extern void pwgaFillSolid(ui fg , ui alu , ui planemask , int xDst , int yDst , int wDst , int hDst);
-extern void pwgaDrawColorImage(int xDst , int yDst , int wDst , int hDst , ub * pSrc , int widthSrc , ui alu , ui planemask);
-extern void pwgaBlit(int xSrc , int ySrc , int wSrc , int hSrc , int xDst , int yDst , ui alu , ui planemask);
-extern int DisplayOpen(int mode1024);
-extern void DisplayClose(void);
-extern void byteoutport(int p , int d);
-extern void short_delay(void);
-extern void InitLUT(void);
-extern int pwgaExists(void);
-extern ui pwgaHWInit(int mode1024);
-extern void outwords(short * wSrc , int wcount);
-extern void outwblock(ub * pSrc , int w , int h , int widthSrc);
-
-/*::::::::::::::
-pr.c
-::::::::::::::*/
-extern void PQ(ul x);
-extern void PL(ui x);
-extern void PW(uw x);
-extern void PB(ub x);
-extern void PutSpace(void);
-extern void PutCR(void);
-
-/*::::::::::::::
-printf.c
-::::::::::::::*/
-extern void PutString(const char * s);
-extern int printf(const char *f, ...);
-
-/*::::::::::::::
-search.c
-::::::::::::::*/
-extern int search(ul first , ul last , int size , char * valstr , int inverse);
-extern void ParseVal(char * s , ul * val , ul * mask , int size);
-
-/*::::::::::::::
-sniff.c
-::::::::::::::*/
-extern int find_first(int map);
-extern int sniff_eisa(int id , int mask , int num_slots);
-
-/*::::::::::::::
-uart.c
-::::::::::::::*/
-extern int uart_charav(int port);
-extern char uart_getchar(int port);
-extern void uart_putchar(int port , char c);
-extern void putcLpt(int c);
-extern void uart_init_line(int line , int baud);
-extern int uart_init(void);
-
-/*::::::::::::::
-vga.c
-::::::::::::::*/
-extern void vgaerase(void);
-extern void vgalcgen(void);
-extern void vgasetloc(void);
-extern void vgaputc(register int c);
-extern void vgastl(ul a , int d);
-extern int vgaldl(ul a);
-extern ub readreg(ui sel , ui off);
-extern void writereg(ui sel , ui off , ub dat);
-extern void dumpvga(void);
-extern void vgainit(void);
-
-/*::::::::::::::
-libc.c
-::::::::::::::*/
-extern int memcmp(const void * pcs , const void * pct , size_t n);
-extern void * memset(void * ps , char c , size_t n);
-extern void * memmove(void * ps , const void * pct , size_t n);
-extern void * memcpy(void * ps , const void * pct , size_t n);
-extern int atoi(const char *nptr);
-extern int isalnum(int c);
-extern int isalpha(int c);
-extern int isascii(int c);
-extern int iscntrl(int c);
-extern int isdigit(int c);
-extern int isgraph(int c);
-extern int islower(int c);
-extern int isprint(int c);
-extern int ispunct(int c);
-extern int isspace(int c);
-extern int isupper(int c);
-extern int isxdigit(int c);
-
-/*::::::::::::::
-flash.c
-::::::::::::::*/
-extern int flash_main(ui src , ui segnum, ui segcnt);
-/*::::::::::::::
-asmstuff.s
-::::::::::::::*/
-extern void mb(void);
-extern ul GetSP(void);
-extern ul cServe(ul, ul, ul, ...);
-extern void wrfen(ui);
-extern void swppal(ul, ul, ul, ul);
-extern void halt(void);
-extern void wait_cycles(ui cycles);
-extern int swpipl(ui);
-extern void CleanBCache(ul);
-/* Here B = 8 bits, W = 16 bits, L = 32 bits, Q = 64 bits */
-#ifdef _WIN32
-extern ui ReadL(ul);
-extern void WriteL(ul, ui);
-extern ul ReadQ(ul);
-extern void WriteQ(ul, ul);
-#else
-#define WriteL(address,value) (*(ui *)(address)=(ui)(value))
-#define ReadL(address) (*(ui *)(address))
-#define WriteQ(address,value) (*(ul *)(address)=(ul)(value))
-#define ReadQ(address) (*(ul *)(address))
-#endif
-
-/*::::::::::::::::
-host specific library definitions
-::::::::::::::::*/
-#ifdef _WIN32
-extern int strcmp(char *cs, char *ct);
-extern char *strcpy(char *s, char *ct);
-extern int strncmp(char *cs, char *ct, int n);
-extern char *strncpy(char *s, char *ct, int n);
-extern int rand(void);
-#endif
-
-#endif /* __LIB_H_LOADED */
+++ /dev/null
-/*
-Copyright 1993, 1994 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-
-/*
- * VID: [T1.2] PT: [Fri Apr 21 16:47:18 1995] SF: [platform.h]
- * TI: [/sae_users/cruz/bin/vice -iplatform.s -l// -p# -DEB164 -h -m -aeb164 ]
- */
-#define __PLATFORM_LOADED 1
-/*
-**
-** FACILITY:
-**
-** DECchip 21164 OSF/1 PALcode
-**
-** MODULE:
-**
-** platform.h
-**
-** MODULE DESCRIPTION:
-**
-** Platform specific definitions.
-**
-** AUTHOR: Lance Berc (taken from EB164 code)
-**
-** CREATION DATE: 14-Jun-1995
-**
-** $Id: platform.h,v 1.1.1.1 1997/10/30 23:27:20 verghese Exp $
-**
-** MODIFICATION HISTORY:
-**
-** $Log: platform.h,v $
-** Revision 1.1.1.1 1997/10/30 23:27:20 verghese
-** current 10/29/97
-**
- * Revision 1.1 1995/06/14 18:50:42 berc
- * Initial revision
- *
-*/
-
-#if !defined(CONSOLE_ENTRY)
-#define CONSOLE_ENTRY 0x10000
-#endif /* CONSOLE_ENTRY */
-
-#define DEBUGDEATH(c) \
- lda a0, c(zero) ; \
- br DebugDeath
-
-#define DEBUGSTORE(c) \
- stq_p t0,0(zero) ; \
- stq_p t1,8(zero) ; \
- lda t0, 0x400(zero) ; \
- sll t0, 29, t0 ; \
- ldah t0, 0x280(t0) ; \
-9: lda t1, 0x140(t0) ; \
- ldl_p t1, 0(t1) ; \
- srl t1, 16, t1 ; \
- and t1, 0x20, t1 ; \
- beq t1, 9b ; \
- lda t1, c(zero) ; \
- stl_p t1, 0(t0) ; \
- mb ; \
- ldq_p t1, 8(zero) ; \
- ldq_p t0, 0(zero)
-
-
-/*
-** IPL translation table definitions:
-**
-** EB164 specific IRQ pins are
-**
-** Line IPL Source OSF/1 IPL
-** ---- --- ------ ---------
-** IRQ0 20 Corrected ECC error 7
-** IRQ1 21 PCI/ISA 3
-** IRQ2 22 Real Time Clock 5
-** IRQ3 23 SIO NMI, CIA errors 7
-**
-** The mask contains one byte for each IPL level, with IPL0 in the
-** least significant (right-most) byte and IPL7 in the most
-** significant (left-most) byte. Each byte in the mask maps the
-** OSF/1 IPL to the DC21164 IPL.
-**
-** OSF/1 IPL IPL
-** --------- ---
-** 0 0
-** 1 1
-** 2 2
-** 3 21 (to account for PCI/ISA at IPL 21)
-** 4 21
-** 5 22 (to account for clock at IPL 21)
-** 6 30 (to account for powerfail)
-** 7 31
-*/
-
-#define INT_K_MASK_HIGH 0x1F1E1615
-#define INT_K_MASK_LOW 0x15020100
-
-#define BYTE_ENABLE_SHIFT 5
-
-/*
-** Dallas DS1287A Real-Time Clock (RTC) Definitions:
-*/
-#define RTCADD 0x160000
-#define RTCDAT 0x170000
-
-
-/*
-** Serial Port (COM) Definitions:
-*/
-
-#define DLA_K_BRG 12 /* Baud Rate Divisor = 9600 */
-
-#define LSR_V_THRE 5 /* Xmit Holding Register Empty Bit */
-
-#define LCR_M_WLS 3 /* Word Length Select Mask */
-#define LCR_M_STB 4 /* Number Of Stop Bits Mask */
-#define LCR_M_PEN 8 /* Parity Enable Mask */
-#define LCR_M_DLAB 128 /* Divisor Latch Access Bit Mask */
-
-#define LCR_K_INIT (LCR_M_WLS | LCR_M_STB)
-
-#define MCR_M_DTR 1 /* Data Terminal Ready Mask */
-#define MCR_M_RTS 2 /* Request To Send Mask */
-#define MCR_M_OUT1 4 /* Output 1 Control Mask */
-#define MCR_M_OUT2 8 /* UART Interrupt Mask Enable */
-
-#define MCR_K_INIT (MCR_M_DTR | \
- MCR_M_RTS | \
- MCR_M_OUT1 | \
- MCR_M_OUT2)
-
-/* CPU Adr[39:29]=0x500 select PCI Mem. */
-#define PCI_MEM 0x400
-#define SLOT_D_COM1 (0x140000)
-#define SLOT_D_COM2 (0x150000)
-
-#define COM1_RBR (SLOT_D_COM1 | (0x0 << 1)) /* Receive Buffer Register Offset */
-#define COM1_THR (SLOT_D_COM1 | (0x0 << 1)) /* Xmit Holding Register Offset */
-#define COM1_IER (SLOT_D_COM1 | (0x1 << 1)) /* Interrupt Enable Register Offset */
-#define COM1_IIR (SLOT_D_COM1 | (0x2 << 1)) /* Interrupt ID Register Offset */
-#define COM1_LCR (SLOT_D_COM1 | (0x3 << 1)) /* Line Control Register Offset */
-#define COM1_MCR (SLOT_D_COM1 | (0x4 << 1)) /* Modem Control Register Offset */
-#define COM1_LSR (SLOT_D_COM1 | (0x5 << 1)) /* Line Status Register Offset */
-#define COM1_MSR (SLOT_D_COM1 | (0x6 << 1)) /* Modem Status Register Offset */
-#define COM1_SCR (SLOT_D_COM1 | (0x7 << 1)) /* Scratch Register Offset */
-#define COM1_DLL (SLOT_D_COM1 | (0x8 << 1)) /* Divisor Latch (LS) Offset */
-#define COM1_DLH (SLOT_D_COM1 | (0x9 << 1)) /* Divisor Latch (MS) Offset */
-
-#define COM2_RBR (SLOT_D_COM2 | (0x0 << 1))
-#define COM2_THR (SLOT_D_COM2 | (0x0 << 1))
-#define COM2_IER (SLOT_D_COM2 | (0x1 << 1))
-#define COM2_IIR (SLOT_D_COM2 | (0x2 << 1))
-#define COM2_LCR (SLOT_D_COM2 | (0x3 << 1))
-#define COM2_MCR (SLOT_D_COM2 | (0x4 << 1))
-#define COM2_LSR (SLOT_D_COM2 | (0x5 << 1))
-#define COM2_MSR (SLOT_D_COM2 | (0x6 << 1))
-#define COM2_SCR (SLOT_D_COM2 | (0x7 << 1))
-#define COM2_DLL (SLOT_D_COM2 | (0x8 << 1))
-#define COM2_DLH (SLOT_D_COM2 | (0x9 << 1))
-
-
-/*
-** Macro to define a port address
-*/
-#define IO_MASK 0x7FFFFFF
-
-/* NOTE ON ADDITIONAL PORT DEFINITION:
-**
-** We also need to set bit 39! Since the span between bit 39
-** and the byte enable field is more than 32, we set bit 39 in the
-** port macros.
-*/
-
-/*
-** Macro to write a byte literal to a specified port
-*/
-#define OutPortByte(port,val,tmp0,tmp1) \
- LDLI (tmp0, port); \
- sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
- lda tmp1, PCI_MEM(zero); \
- sll tmp1, 29, tmp1; \
- bis tmp0, tmp1, tmp0; \
- lda tmp1, (val)(zero); \
- sll tmp1, 8*(port & 3), tmp1; \
- stl_p tmp1, 0x00(tmp0); \
- mb
-
-/*
-** Macro to write a byte from a register to a specified port
-*/
-#define OutPortByteReg(port,reg,tmp0,tmp1) \
- LDLI (tmp0, port); \
- sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
- lda tmp1, PCI_MEM(zero); \
- sll tmp1, 29, tmp1; \
- bis tmp0, tmp1, tmp0; \
- sll reg, 8*(port & 3), tmp1; \
- stl_p tmp1, 0x00(tmp0); \
- mb
-
-/*
-** Macro to write a longword from a register to a specified port
-*/
-#define OutPortLongReg(port,reg,tmp0,tmp1) \
- LDLI (tmp0, port); \
- sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
- lda tmp1, PCI_MEM(zero); \
- sll tmp1, 29, tmp1; \
- bis tmp0, tmp1, tmp0; \
- stl_p tmp1, 0x18(tmp0); \
- mb
-
-/*
-** Macro to read a byte from a specified port
-*/
-#define InPortByte(port,tmp0,tmp1) \
- LDLI (tmp0, port); \
- sll tmp0, BYTE_ENABLE_SHIFT, tmp0; \
- lda tmp1, PCI_MEM(zero); \
- sll tmp1, 29, tmp1; \
- bis tmp0, tmp1, tmp0; \
- ldl_p tmp0, 0x00(tmp0); \
- srl tmp0, (8 * (port & 3)), tmp0; \
- zap tmp0, 0xfe, tmp0
+++ /dev/null
-/*
-Copyright 1993Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-
-#ifndef __REGDEFS_H_LOADED
-#define __REGDEFS_H_LOADED
-
-/*
- * $Id: regdefs.h,v 1.1.1.1 1997/10/30 23:27:17 verghese Exp $;
- */
-
-/*
- * $Log: regdefs.h,v $
- * Revision 1.1.1.1 1997/10/30 23:27:17 verghese
- * current 10/29/97
- *
- * Revision 1.2 1995/02/24 16:00:18 fdh
- * Conditional around #define AT.
- *
- * Revision 1.1 1995/02/24 15:54:26 fdh
- * Initial revision
- *
- */
-
-#define v0 $0
-#define t0 $1
-#define t1 $2
-#define t2 $3
-#define t3 $4
-#define t4 $5
-#define t5 $6
-#define t6 $7
-#define t7 $8
-#define s0 $9
-#define s1 $10
-#define s2 $11
-#define s3 $12
-#define s4 $13
-#define s5 $14
-#define s6 $15
-#define fp $15 /* fp & s6 are the same */
-#define a0 $16
-#define a1 $17
-#define a2 $18
-#define a3 $19
-#define a4 $20
-#define a5 $21
-#define t8 $22
-#define t9 $23
-#define t10 $24
-#define t11 $25
-#define ra $26
-#define pv $27 /* pv and t5 are the same */
-#define t12 $27
-#ifndef AT
-#define AT $at
-#endif
-#define gp $29
-#define sp $30
-#define zero $31
-
-#endif /* __REGDEFS_H_LOADED */
/*
-Copyright 1990 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-/*
- * "@(#)rpb.h 9.2 (ULTRIX/OSF) 10/30/91"
+ * Copyright 1990 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
*/
+
/*
* Defines for the architected startup addresses.
*/
-
#define HWRPB_ADDR 0x10000000 /* 256 MB */
#define BOOT_ADDR 0x20000000 /* 512 MB */
#define PGTBL_ADDR 0x40000000 /* 1 GB */
#define SV_PF_RSVD 0x00000000 /* RESERVED */
-#define SV_RESERVED 0x00000000 /* All STS bits; zero for backward compat. */
+#define SV_RESERVED 0x00000000 /* All STS bits; 0 for back compat */
#define SV_MPCAP 0x00000001 /* MP capable */
#define SV_PF_UNITED 0x00000020 /* United */
#define SV_PF_SEPARATE 0x00000040 /* Separate */
#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */
-#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */
-#define SV_SANDPIPER 0x00000400 /* others define system platforms. */
+#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */
+#define SV_SANDPIPER 0x00000400 /* others define system platforms */
#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */
#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */
#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */
#define CONS_NONE 0 /* no console present */
#define CONS_SRVC 1 /* console is service processor */
#define CONS_DZ 2 /* console is dz/dl VT device */
-#define CONS_GRPH 3 /* cons is graphics dev w/ dz/dl keybd*/
+#define CONS_GRPH 3 /* cons is gfx dev w/ dz/dl keybd*/
#define CONS_REM 4 /* cons is remote, protocal enet/MOP */
/*
#define PALvar_OpenVMS 1
#define PALvar_OSF1 2
-#include <sys/types.h>
/*
* The Alpha restart parameter block, which is a page or 2 in low memory
*/
struct rpb {
struct rpb *rpb_selfref; /* 000: physical self-reference */
- long rpb_string; /* 008: contains string "HWRPB" */
- long rpb_vers; /* 010: HWRPB version number */
- u_long rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */
- u_long rpb_cpuid; /* 020: primary cpu id */
- u_long rpb_pagesize; /* 028: page size in bytes */
- u_long rpb_addrbits; /* 030: number of phys addr bits */
- u_long rpb_maxasn; /* 038: max valid ASN */
- char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */
- u_long rpb_systype; /* 050: system type */
- long rpb_sysvar; /* 058: system variation */
- long rpb_sysrev; /* 060: system revision */
- u_long rpb_clock; /* 068: scaled interval clock intr freq */
- u_long rpb_counter; /* 070: cycle counter frequency */
- u_long rpb_vptb; /* 078: virtual page table base */
- long rpb_res1; /* 080: reserved */
- u_long rpb_trans_off; /* 088: offset to translation buffer hint */
- u_long rpb_numprocs; /* 090: number of processor slots */
- u_long rpb_slotsize; /* 098: per-cpu slot size */
- u_long rpb_percpu_off; /* 0A0: offset to per_cpu slots */
- u_long rpb_num_ctb; /* 0A8: number of CTBs */
- u_long rpb_ctb_size; /* 0B0: bytes in largest CTB */
- u_long rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */
- u_long rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */
- u_long rpb_mdt_off; /* 0C8: offset to memory descriptor table */
- u_long rpb_config_off; /* 0D0: offset to config data block */
- u_long rpb_fru_off; /* 0D8: offset to FRU table */
- void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */
- long rpb_saveterm_pv; /* 0E8: proc value for save term routine */
- void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */
- long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */
- void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */
- long rpb_restart_pv; /* 108: proc value for CPU restart routine */
- long rpb_software; /* 110: used to determine presence of kdebug */
- long rpb_hardware; /* 118: reserved for hardware */
- long rpb_checksum; /* 120: checksum of prior entries in rpb */
- long rpb_rxrdy; /* 128: receive ready bitmask */
- long rpb_txrdy; /* 130: transmit ready bitmask */
- u_long rpb_dsr_off; /* 138: Dynamic System Recog. offset */
+ long rpb_string; /* 008: contains string "HWRPB" */
+ long rpb_vers; /* 010: HWRPB version number */
+ ulong rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */
+ ulong rpb_cpuid; /* 020: primary cpu id */
+ ulong rpb_pagesize; /* 028: page size in bytes */
+ ulong rpb_addrbits; /* 030: number of phys addr bits */
+ ulong rpb_maxasn; /* 038: max valid ASN */
+ char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */
+ ulong grpb_systype; /* 050: system type */
+ long rpb_sysvar; /* 058: system variation */
+ long rpb_sysrev; /* 060: system revision */
+ ulong rpb_clock; /* 068: scaled interval clock intr freq */
+ ulong rpb_counter; /* 070: cycle counter frequency */
+ ulong rpb_vptb; /* 078: virtual page table base */
+ long rpb_res1; /* 080: reserved */
+ ulong rpb_trans_off; /* 088: offset to translation buffer hint */
+ ulong rpb_numprocs; /* 090: number of processor slots */
+ ulong rpb_slotsize; /* 098: per-cpu slot size */
+ ulong rpb_percpu_off; /* 0A0: offset to per_cpu slots */
+ ulong rpb_num_ctb; /* 0A8: number of CTBs */
+ ulong rpb_ctb_size; /* 0B0: bytes in largest CTB */
+ ulong rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */
+ ulong rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */
+ ulong rpb_mdt_off; /* 0C8: offset to memory descriptor table */
+ ulong rpb_config_off; /* 0D0: offset to config data block */
+ ulong rpb_fru_off; /* 0D8: offset to FRU table */
+ void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */
+ long rpb_saveterm_pv; /* 0E8: proc value for save term routine */
+ void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */
+ long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */
+ void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */
+ long rpb_restart_pv; /* 108: proc value for CPU restart routine */
+ long rpb_software; /* 110: used to determine presence of kdebug */
+ long rpb_hardware; /* 118: reserved for hardware */
+ long rpb_checksum; /* 120: checksum of prior entries in rpb */
+ long rpb_rxrdy; /* 128: receive ready bitmask */
+ long rpb_txrdy; /* 130: transmit ready bitmask */
+ ulong rpb_dsr_off; /* 138: Dynamic System Recog. offset */
};
#define rpb_kdebug rpb_software
* with formats used by other palcode types.
*/
struct bootpcb {
- long rpb_ksp; /* 000: kernel stack pointer */
- long rpb_usp; /* 008: user stack pointer */
- long rpb_ptbr; /* 010: page table base register */
- int rpb_cc; /* 018: cycle counter */
- int rpb_asn; /* 01C: address space number */
- long rpb_proc_uniq; /* 020: proc/thread unique value */
- long rpb_fen; /* 028: floating point enable */
- long rpb_palscr[2]; /* 030: pal scratch area */
- long rpb_pcbpad[8]; /* 040: padding for fixed size */
+ long rpb_ksp; /* 000: kernel stack pointer */
+ long rpb_usp; /* 008: user stack pointer */
+ long rpb_ptbr; /* 010: page table base register */
+ int rpb_cc; /* 018: cycle counter */
+ int rpb_asn; /* 01C: address space number */
+ long rpb_proc_uniq; /* 020: proc/thread unique value */
+ long rpb_fen; /* 028: floating point enable */
+ long rpb_palscr[2]; /* 030: pal scratch area */
+ long rpb_pcbpad[8]; /* 040: padding for fixed size */
};
/*
* of secondary processors.
*/
struct iccb {
- u_int iccb_rxlen; /* receive length in bytes */
- u_int iccb_txlen; /* transmit length in bytes */
- char iccb_rxbuf[80]; /* receive buffer */
- char iccb_txbuf[80]; /* transmit buffer */
+ uint iccb_rxlen; /* receive length in bytes */
+ uint iccb_txlen; /* transmit length in bytes */
+ char iccb_rxbuf[80]; /* receive buffer */
+ char iccb_txbuf[80]; /* transmit buffer */
};
/*
*/
struct rpb_percpu {
struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */
- long rpb_state; /* 080: per-cpu state bits */
- long rpb_palmem; /* 088: palcode memory length */
- long rpb_palscratch; /* 090: palcode scratch length */
- long rpb_palmem_addr; /* 098: phys addr of palcode mem space */
- long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */
- long rpb_palrev; /* 0A8: PALcode rev required */
- long rpb_proctype; /* 0B0: processor type */
- long rpb_procvar; /* 0B8: processor variation */
- long rpb_procrev; /* 0C0: processor revision */
- char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */
- long rpb_logout; /* 0D8: phys addr of logout area */
- long rpb_logout_len; /* 0E0: length in bytes of logout area */
- long rpb_haltpb; /* 0E8: halt pcb base */
- long rpb_haltpc; /* 0F0: halt pc */
- long rpb_haltps; /* 0F8: halt ps */
- long rpb_haltal; /* 100: halt arg list (R25) */
- long rpb_haltra; /* 108: halt return address (R26) */
- long rpb_haltpv; /* 110: halt procedure value (R27) */
- long rpb_haltcode; /* 118: reason for halt */
- long rpb_software; /* 120: for software */
- struct iccb rpb_iccb; /* 128: inter-console communications buffer */
- long rpb_palrev_avail[16];/* 1D0: PALcode revs available */
- long rpb_pcrsvd[6]; /* 250: reserved for arch use */
+ long rpb_state; /* 080: per-cpu state bits */
+ long rpb_palmem; /* 088: palcode memory length */
+ long rpb_palscratch; /* 090: palcode scratch length */
+ long rpb_palmem_addr; /* 098: phys addr of palcode mem space */
+ long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */
+ long rpb_palrev; /* 0A8: PALcode rev required */
+ long rpb_proctype; /* 0B0: processor type */
+ long rpb_procvar; /* 0B8: processor variation */
+ long rpb_procrev; /* 0C0: processor revision */
+ char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */
+ long rpb_logout; /* 0D8: phys addr of logout area */
+ long rpb_logout_len; /* 0E0: length in bytes of logout area */
+ long rpb_haltpb; /* 0E8: halt pcb base */
+ long rpb_haltpc; /* 0F0: halt pc */
+ long rpb_haltps; /* 0F8: halt ps */
+ long rpb_haltal; /* 100: halt arg list (R25) */
+ long rpb_haltra; /* 108: halt return address (R26) */
+ long rpb_haltpv; /* 110: halt procedure value (R27) */
+ long rpb_haltcode; /* 118: reason for halt */
+ long rpb_software; /* 120: for software */
+ struct iccb rpb_iccb; /* 128: inter-console communications buffer */
+ long rpb_palrev_avail[16]; /* 1D0: PALcode revs available */
+ long rpb_pcrsvd[6]; /* 250: reserved for arch use */
/* the dump stack grows from the end of the rpb page not to reach here */
};
* The memory cluster descriptor.
*/
struct rpb_cluster {
- long rpb_pfn; /* 000: starting PFN of this cluster */
- long rpb_pfncount; /* 008: count of PFNs in this cluster */
- long rpb_pfntested; /* 010: count of tested PFNs in cluster */
- long rpb_va; /* 018: va of bitmap */
- long rpb_pa; /* 020: pa of bitmap */
- long rpb_checksum; /* 028: checksum of bitmap */
- long rpb_usage; /* 030: usage of cluster */
+ long rpb_pfn; /* 000: starting PFN of this cluster */
+ long rpb_pfncount; /* 008: count of PFNs in this cluster */
+ long rpb_pfntested; /* 010: count of tested PFNs in cluster */
+ long rpb_va; /* 018: va of bitmap */
+ long rpb_pa; /* 020: pa of bitmap */
+ long rpb_checksum; /* 028: checksum of bitmap */
+ long rpb_usage; /* 030: usage of cluster */
};
#define CLUSTER_USAGE_OS ((long)0)
#define CLUSTER_USAGE_PAL ((long)1)
* of memory).
*/
struct rpb_mdt {
- long rpb_checksum; /* 000: checksum of entire mem desc table */
- long rpb_impaddr; /* 008: PA of implementation dep info */
- long rpb_numcl; /* 010: number of clusters */
+ long rpb_checksum; /* 000: checksum of entire mem desc table */
+ long rpb_impaddr; /* 008: PA of implementation dep info */
+ long rpb_numcl; /* 010: number of clusters */
struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */
};
* UART console device.
*/
struct ctb_tt {
- long ctb_type; /* 000: console type */
- long ctb_unit; /* 008: console unit */
- long ctb_resv; /* 010: reserved */
- long ctb_length; /* 018: byte length of device dep */
- /* portion */
- long ctb_csr; /* 020: CSR Address */
- long ctb_tivec; /* 028: <63>=tie; interrupt vector */
- long ctb_rivec; /* 030: <63>=rie; interrupt vector */
- long ctb_baud; /* 038: baud rate */
- long ctb_put_sts; /* 040: PUTS callback extended status */
- long ctb_get_sts; /* 048: GETS callback extended status */
- long ctb_rsvd[1]; /* 050: reserved for console use */
+ long ctb_type; /* 000: console type */
+ long ctb_unit; /* 008: console unit */
+ long ctb_resv; /* 010: reserved */
+ long ctb_length; /* 018: byte length of device dep portion */
+ long ctb_csr; /* 020: CSR Address */
+ long ctb_tivec; /* 028: <63>=tie; interrupt vector */
+ long ctb_rivec; /* 030: <63>=rie; interrupt vector */
+ long ctb_baud; /* 038: baud rate */
+ long ctb_put_sts; /* 040: PUTS callback extended status */
+ long ctb_get_sts; /* 048: GETS callback extended status */
+ long ctb_rsvd[1]; /* 050: reserved for console use */
};
/*
* The "Console Terminal Block" portion of the HWRPB.
*/
struct rpb_ctb {
- long rpb_type; /* 000: console type */
- long rpb_unit; /* 008: console unit */
- long rpb_resv; /* 010: reserved */
- long rpb_length; /* 018: byte length of device dep portion */
- long rpb_first; /* 000: first field of device dep portion */
+ long rpb_type; /* 000: console type */
+ long rpb_unit; /* 008: console unit */
+ long rpb_resv; /* 010: reserved */
+ long rpb_length; /* 018: byte length of device dep portion */
+ long rpb_first; /* 000: first field of device dep portion */
};
/*
* The physical/virtual map for the console routine block.
*/
struct rpb_map {
- long rpb_virt; /* virtual address for map entry */
- long rpb_phys; /* phys address for map entry */
- long rpb_pgcount; /* page count for map entry */
+ long rpb_virt; /* virtual address for map entry */
+ long rpb_phys; /* phys address for map entry */
+ long rpb_pgcount; /* page count for map entry */
};
/*
* Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR).
*/
struct rpb_crb {
- long rpb_va_disp; /* va of call-back dispatch rtn */
- long rpb_pa_disp; /* pa of call-back dispatch rtn */
- long rpb_va_fixup; /* va of call-back fixup rtn */
- long rpb_pa_fixup; /* pa of call-back fixup rtn */
- long rpb_num; /* number of entries in phys/virt map */
- long rpb_mapped_pages; /* Number of pages to be mapped */
- struct rpb_map rpb_map[1]; /* first instance of a map entry */
+ long rpb_va_disp; /* va of call-back dispatch rtn */
+ long rpb_pa_disp; /* pa of call-back dispatch rtn */
+ long rpb_va_fixup; /* va of call-back fixup rtn */
+ long rpb_pa_fixup; /* pa of call-back fixup rtn */
+ long rpb_num; /* number of entries in phys/virt map */
+ long rpb_mapped_pages; /* Number of pages to be mapped */
+ struct rpb_map rpb_map[1]; /* first instance of a map entry */
};
/*
* These macros define where within the HWRPB the CTB and CRB are located.
*/
-#define CTB_SETUP ((struct rpb_ctb *) ((long)hwrpb_addr + \
- (long)(hwrpb_addr->rpb_ctb_off)))
-#define CRB_SETUP ((struct rpb_crb *) ((long)hwrpb_addr + \
- (long)(hwrpb_addr->rpb_crb_off)))
+#define CTB_SETUP \
+ ((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off)))
+
+#define CRB_SETUP \
+ ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off)))
/*
* The "Dynamic System Recognition" portion of the HWRPB.
* data for software licensing
*/
struct rpb_dsr {
- long rpb_smm; /* SMM nubber used by LMF */
- u_long rpb_lurt_off; /* offset to LURT table */
- u_long rpb_sysname_off; /* offset to sysname char count */
- int lurt[10]; /* XXM has one LURT entry */
+ long rpb_smm; /* SMM nubber used by LMF */
+ ulong rpb_lurt_off; /* offset to LURT table */
+ ulong rpb_sysname_off; /* offset to sysname char count */
+ int lurt[10]; /* XXM has one LURT entry */
};
-#Copyright (c) 2003, 2004
-#The Regents of The University of Michigan
-#All Rights Reserved
+# Copyright (c) 2003, 2004
+# The Regents of The University of Michigan
+# All Rights Reserved
#
-#This code is part of the M5 simulator, developed by Nathan Binkert,
-#Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
-#from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
-#Schultz.
+# This code is part of the M5 simulator, developed by Nathan Binkert,
+# Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+# from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
+# Schultz.
#
-#Permission is granted to use, copy, create derivative works and
-#redistribute this software and such derivative works for any purpose,
-#so long as the copyright notice above, this grant of permission, and
-#the disclaimer below appear in all copies made; and so long as the
-#name of The University of Michigan is not used in any advertising or
-#publicity pertaining to the use or distribution of this software
-#without specific, written prior authorization.
+# Permission is granted to use, copy, create derivative works and
+# redistribute this software and such derivative works for any purpose,
+# so long as the copyright notice above, this grant of permission, and
+# the disclaimer below appear in all copies made; and so long as the
+# name of The University of Michigan is not used in any advertising or
+# publicity pertaining to the use or distribution of this software
+# without specific, written prior authorization.
#
-#THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
-#UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
-#WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
-#IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
-#MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
-#THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
-#INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
-#DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
-#WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
-#ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-
-#Makefile for palcode
-#Works on alpha-linux and builds elf executable
+# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
+# WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
+# THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
+# INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+# DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
+# WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+# Makefile for palcode
+# Works on alpha-linux and builds elf executable
### If we are not compiling on an alpha, we must use cross tools ###
-ifneq ($(ARCHNAME), alpha)
+ifneq ($(shell uname -m), alpha)
CROSS_COMPILE?=alpha-unknown-linux-gnu-
endif
CC=$(CROSS_COMPILE)gcc
AS=$(CROSS_COMPILE)as
LD=$(CROSS_COMPILE)ld
-CFLAGS=-I . -I ../h -D SIMOS -D BUILD_PALCODE -nostdinc -nostdinc++ -Wa,-m21164
+CFLAGS=-I . -I ../h -nostdinc -nostdinc++ -Wa,-m21164
LDFLAGS=-Ttext 0x4000
-TLOBJS = osfpal.o platform_tlaser.o
-TLOBJS_COPY = osfpal_cache_copy.o osfpal_cache_copy_unaligned.o
-TSOBJS = osfpal.o platform_m5.o
-TSBOBJS = osfpal.o platform_m5b.o
-TSOBJS_COPY = osfpal_cache_copy.o osfpal_cache_copy_unaligned.o
+TLOBJS = osfpal.o platform_tlaser.o
+TLOBJS_COPY = osfpal_cache_copy.o platform_tlaser.o
+TLOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_tlaser.o
+TSOBJS = osfpal.o platform_tsunami.o
+TSBOBJS = osfpal.o platform_bigtsunami.o
+TSOBJS_COPY = osfpal_cache_copy.o platform_tsunami.o
+TSOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_bigtsunami.o
+
+all: tlaser tsunami tsunami_b64
-%.o: %.S
+all_copy: tlaser tlaser_copy tsunami tsunami_b64 tsunami_copy
+
+osfpal.o: osfpal.S
$(CC) $(CFLAGS) -o $@ -c $<
-all: tsunami tsunami_b64
-
-platform_m5b.o: platform_m5.S
+osfpal_cache_copy.o: osfpal.S
+ $(CC) $(CFLAGS) -DCACHE_COPY -o $@ -c $<
+
+osfpal_cache_copy_unaligned.o: osfpal.S
+ $(CC) $(CFLAGS) -DCACHE_COPY -DCACHE_COPY_UNALIGNED -o $@ -c $<
+
+platform_tlaser.o: platform.S
+ $(CC) $(CFLAGS) -DTLASER -o $@ -c $<
+
+platform_tsunami.o: platform.S
+ $(CC) $(CFLAGS) -DTSUNAMI -o $@ -c $<
+
+platform_bigtsunami.o: platform.S
$(CC) $(CFLAGS) -DBIG_TSUNAMI -o $@ -c $<
-
+
tlaser: $(TLOBJS)
- $(LD) $(LDFLAGS) -o tl_osfpal osfpal.o platform_tlaser.o
+ $(LD) $(LDFLAGS) -o tl_osfpal $(TLOBJS)
-tlaser_copy: $(TLOBJS_COPY) $(TLOBJS)
- $(LD) $(LDFLAGS) -o tl_osfpal_cache osfpal_cache_copy.o platform_tlaser.o
- $(LD) $(LDFLAGS) -o tl_osfpal_unalign osfpal_cache_copy_unaligned.o platform_tlaser.o
+tlaser_copy: $(TLOBJS_COPY) $(TLOBJS_COPY_UNALIGNED)
+ $(LD) $(LDFLAGS) -o tl_osfpal_cache $(TLOBJS_COPY)
+ $(LD) $(LDFLAGS) -o tl_osfpal_unalign $(TLOBJS_COPY_UNALIGNED)
tsunami: $(TSOBJS)
- $(LD) $(LDFLAGS) -o ts_osfpal osfpal.o platform_m5.o
+ $(LD) $(LDFLAGS) -o ts_osfpal $(TSOBJS)
tsunami_b64: $(TSBOBJS)
- $(LD) $(LDFLAGS) -o tsb_osfpal osfpal.o platform_m5b.o
+ $(LD) $(LDFLAGS) -o tsb_osfpal $(TSBOBJS)
-tsunami_copy: $(TSOBJS) $(TSOBJS_COPY)
- $(LD) $(LDFLAGS) -o ts_osfpal_cache osfpal_cache_copy.o platform_m5.o
- $(LD) $(LDFLAGS) -o ts_osfpal_unalign osfpal_cache_copy_unaligned.o platform_m5.o
+tsunami_copy: $(TSOBJS_COPY) $(TSOBJS_COPY_UNALIGNED)
+ $(LD) $(LDFLAGS) -o ts_osfpal_cache $(TSOBJS_COPY)
+ $(LD) $(LDFLAGS) -o ts_osfpal_unalign $(TSOBJS_COPY_UNALIGNED)
clean:
rm -f *.o tl_osfpal tl_osfpal_cache tl_osfpal_unalign ts_osfpal \
*/
/*
-Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
+ * Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development
+ * Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl
// since we don't have a mechanism to expand the data structures.... pb Nov/95
-
-// build_fixed_image: not sure what means
-// real_mm to be replaced during rewrite
-// remove_save_state remove_restore_state can be remooved to save space ??
-
-
#include "ev5_defs.h"
#include "ev5_impure.h"
#include "ev5_alpha_defs.h"
#include "fromHudsonOsf.h"
#include "dc21164FromGasSources.h"
-#ifdef SIMOS
#define DEBUGSTORE(c) nop
-#else
-#define DEBUGSTORE(c) \
- lda r13, c(zero) ; \
- bsr r25, debugstore
-#endif
#define DEBUG_EXC_ADDR()\
bsr r25, put_exc_addr; \
DEBUGSTORE(13) ; \
DEBUGSTORE(10)
-#define egore 0
-#define acore 0
-#define beh_model 0
-#define ev5_p2 1
-#define ev5_p1 0
-#define ldvpte_bug_fix 1
-#define osf_chm_fix 0
-
-// Do we want to do this?? pb
-#define spe_fix 0
-// Do we want to do this?? pb
-#define build_fixed_image 0
-
-#define ev5_pass2
-#define enable_p4_fixups 0
-#define osf_svmin 1
-#define enable_physical_console 0
-#define fill_err_hack 0
-#define icflush_on_tbix 0
-#define max_cpuid 1
-#define perfmon_debug 0
-#define rawhide_system 0
-#define rax_mode 0
-
-
-// This is the fix for the user-mode super page references causing the machine to crash.
-#if (spe_fix == 1) && (build_fixed_image==1)
-#define hw_rei_spe br r31, hw_rei_update_spe
-#else
+// This is the fix for the user-mode super page references causing the
+// machine to crash.
#define hw_rei_spe hw_rei
-#endif
-
-// redefine a few of the distribution-code names to match the Hudson gas names.
-// opcodes
-#define ldqp ldq_p
-#define stqp stq_p
-#define ldlp ldl_p
-#define stlp stl_p
-
-#define r0 $0
-#define r1 $1
-#define r2 $2
-#define r3 $3
-#define r4 $4
-#define r5 $5
-#define r6 $6
-#define r7 $7
-#define r8 $8
-#define r9 $9
-#define r10 $10
-#define r11 $11
-#define r12 $12
-#define r13 $13
-#define r14 $14
-#define r15 $15
-#define r16 $16
-#define r17 $17
-#define r18 $18
-#define r19 $19
-#define r20 $20
-#define r21 $21
-#define r22 $22
-#define r23 $23
-#define r24 $24
-#define r25 $25
-#define r26 $26
-#define r27 $27
-#define r28 $28
-#define r29 $29
-#define r30 $30
-#define r31 $31
-
-// .title "EV5 OSF PAL"
-// .ident "V1.18"
-//
-//****************************************************************************
-//* *
-//* Copyright (c) 1992, 1993, 1994, 1995 *
-//* by DIGITAL Equipment Corporation, Maynard, Mass. *
-//* *
-//* This software is furnished under a license and may be used and copied *
-//* only in accordance with the terms of such license and with the *
-//* inclusion of the above copyright notice. This software or any other *
-//* copies thereof may not be provided or otherwise made available to any *
-//* other person. No title to and ownership of the software is hereby *
-//* transferred. *
-//* *
-//* The information in this software is subject to change without notice *
-//* and should not be construed as a commitment by DIGITAL Equipment *
-//* Corporation. *
-//* *
-//* DIGITAL assumes no responsibility for the use or reliability of its *
-//* software on equipment which is not supplied by DIGITAL. *
-//* *
-//****************************************************************************
-
-// .sbttl "Edit History"
-//+
-// Who Rev When What
-// ------------ --- ----------- --------------------------------
-// DB 0.0 03-Nov-1992 Start
-// DB 0.1 28-Dec-1992 add swpctx
-// DB 0.2 05-Jan-1993 Bug: PVC found mtpr dtb_CM -> virt ref bug
-// DB 0.3 11-Jan-1993 rearrange trap entry points
-// DB 0.4 01-Feb-1993 add tbi
-// DB 0.5 04-Feb-1993 real MM, kludge reset flow, kludge swppal
-// DB 0.6 09-Feb-1993 Bug: several stack pushers used r16 for pc (should be r14)
-// DB 0.7 10-Feb-1993 Bug: pushed wrong PC (+8) on CALL_PAL OPCDEC
-// Bug: typo on register number for store in wrunique
-// Bug: rti to kern uses r16 as scratch
-// Bug: callsys saving wrong value in pt_usp
-// DB 0.8 16-Feb-1993 PVC: fix possible pt write->read bug in wrkgp, wrusp
-// DB 0.9 18-Feb-1993 Bug: invalid_dpte_handler shifted pte twice
-// Bug: rti stl_c could corrupt the stack
-// Bug: unaligned returning wrong value in r17 (or should be and)
-// DB 0.10 19-Feb-1993 Add draina, rd/wrmces, cflush, cserve, interrupt
-// DB 0.11 23-Feb-1993 Turn caches on in reset flow
-// DB 0.12 10-Mar-1993 Bug: wrong value for icsr for FEN in kern mode flow
-// DB 0.13 15-Mar-1993 Bug: wrong value pushed for PC in invalid_dpte_handler if stack push tbmisses
-// DB 0.14 23-Mar-1993 Add impure pointer paltemp, reshuffle some other paltemps to match VMS
-// DB 0.15 15-Apr-1993 Combine paltemps for WHAMI and MCES
-// DB 0.16 12-May-1993 Update reset
-// New restriction: no mfpr exc_addr in cycle 1 of call_pal flows
-// Bug: in wrmces, not clearing DPC, DSC
-// Update swppal
-// Add pal bugchecks, pal_save_state, pal_restore_state
-// DB 0.17 24-May-1993 Add dfault_in_pal flow; fixup stack builder to have common state for pc/ps.
-// New restriction: No hw_rei_stall in 0,1,2 after mtpr itb_asn
-// DB 0.18 26-May-1993 PVC fixes
-// JM 0.19 01-jul-1993 Bug: OSFPAL_CALPAL_OPCDEC, TRAP_OPCDEC -- move mt exc_addr after stores
-// JM 0.20 07-jul-1993 Update cns_ and mchk_ names for impure.mar conversion to .sdl
-// Bug: exc_addr was being loaded before stores that could dtb_miss in the following
-// routines: TRAP_FEN,FEN_TO_OPCDEC,CALL_PAL_CALLSYS,RTI_TO_KERN
-// JM 0.21 26-jul-1993 Bug: move exc_addr load after ALL stores in the following routines:
-// TRAP_IACCVIO::,TRAP_OPCDEC::,TRAP_ARITH::,TRAP_FEN::
-// dfault_trap_cont:,fen_to_opcdec:,invalid_dpte_handler:
-// osfpal_calpal_opcdec:,CALL_PAL_callsys::,TRAP_UNALIGN::
-// Bugs from PVC: trap_unalign - mt pt0 ->mf pt0 within 2 cycles
-// JM 0.22 28-jul-1993 Add WRIPIR instruction
-// JM 0.23 05-aug-1993 Bump version number for release
-// JM 0.24 11-aug-1993 Bug: call_pal_swpipl - palshadow write -> hw_rei violation
-// JM 0.25 09-sep-1993 Disable certain "hidden" pvc checks in call_pals;
-// New restriction: No hw_rei_stall in 0,1,2,3,4 after mtpr itb_asn - affects HALT(raxmode),
-// and SWPCTX
-// JM 0.26 07-oct-1993 Re-implement pal_version
-// JM 0.27 12-oct-1993 One more time: change pal_version format to conform to SRM
-// JM 0.28 14-oct-1993 Change ic_flush routine to pal_ic_flush
-// JM 0.29 19-oct-1993 BUG(?): dfault_in_pal: use exc_addr to check for dtbmiss,itbmiss check instead
-// of mm_stat<opcode>. mm_stat contains original opcode, not hw_ld.
-// JM 0.30 28-oct-1993 BUG: PVC violation - mf exc_addr in first cycles of call_pal in rti,retsys
-// JM 0.31 15-nov-1993 BUG: WRFEN trashing r0
-// JM 0.32 21-nov-1993 BUG: dtb_ldq,itb_ldq (used in dfault_in_pal) not defined when real_mm=0
-// JM 0.33 24-nov-1993 save/restore_state -
-// BUG: use ivptbr to restore mvptbr
-// BUG: adjust hw_ld/st base/offsets to accomodate 10-bit offset limit
-// CHANGE: Load 2 pages into dtb to accomodate compressed logout area/multiprocessors
-// JM 0.34 20-dec-1993 BUG: set r11<mode> to kernel for ksnv halt case
-// BUG: generate ksnv halt when tb miss on kernel stack accesses
-// save exc_addr in r14 for invalid_dpte stack builder
-// JM 0.35 30-dec-1993 BUG: PVC violation in trap_arith - mt exc_sum in shadow of store with mf exc_mask in
-// the same shadow
-// JM 0.36 6-jan-1994 BUG: fen_to_opcdec - savePC should be PC+4, need to save old PS, update new PS
-// New palcode restiction: mt icsr<fpe,hwe> --> 3 bubbles to hw_rei --affects wrfen
-// JM 0.37 25-jan-1994 BUG: PVC violations in restore_state - mt dc_mode/maf_mode ->mbox instructions
-// Hide impure area manipulations in macros
-// BUG: PVC violation in save and restore state-- move mt icsr out of shadow of ld/st
-// Add some pvc_violate statements
-// JM 0.38 1-feb-1994 Changes to save_state: save pt1; don't save r31,f31; update comments to reflect reality;
-// Changes to restore_state: restore pt1, icsr; don't restore r31,f31; update comments
-// Add code to ensure fen bit set in icsr before ldt
-// conditionally compile rax_more_reset out.
-// move ldqp,stqp macro definitions to ev5_pal_macros.mar and add .mcall's for them here
-// move rax reset stuff to ev5_osf_system_pal.m64
-// JM 0.39 7-feb-1994 Move impure pointer to pal scratch space. Use former pt_impure for bc_ctl shadow
-// and performance monitoring bits
-// Change to save_state routine to save more iprs.
-// JM 0.40 19-feb-1994 Change algorithm in save/restore_state routines; add f31,r31 back in
-// JM 0.41 21-feb-1994 Add flags to compile out save/restore state (not needed in some systems)
-// remove_save_state,remove_restore_state;fix new pvc violation in save_state
-// JM 0.42 22-feb-1994 BUG: save_state overwriting r3
-// JM 0.43 24-feb-1994 BUG: save_state saving wrong icsr
-// JM 0.44 28-feb-1994 Remove ic_flush from wr_tbix instructions
-// JM 0.45 15-mar-1994 BUG: call_pal_tbi trashes a0 prior to range check (instruction order problem)
-// New pal restriction in pal_restore_state: icsr<fpe>->floating instr = 3 bubbles
-// Add exc_sum and exc_mask to pal_save_state (not restore)
-// JM 0.46 22-apr-1994 Move impure pointer back into paltemp; Move bc_ctl shadow and pmctr_ctl into impure
-// area.
-// Add performance counter support to swpctx and wrperfmon
-// JM 0.47 9-may-1994 Bump version # (for ev5_osf_system_pal.m64 sys_perfmon fix)
-// JM 0.48 13-jun-1994 BUG: trap_interrupt --> put new ev5 ipl at 30 for all osfipl6 interrupts
-// JM 0.49 8-jul-1994 BUG: In the unlikely (impossible?) event that the branch to pal_pal_bug_check is
-// taken in the interrupt flow, stack is pushed twice.
-// SWPPAL - update to support ECO 59 to allow 0 as a valid address
-// Add itb flush to save/restore state routines
-// Change hw_rei to hw_rei_stall in ic_flush routine. Shouldn't be necessary, but
-// conforms to itbia restriction.
-// Added enable_physical_console flag (for enter/exit console routines only)
-// JM 0.50 29-jul-1994 Add code to dfault & invalid_dpte_handler to ignore exceptions on a
-// load to r31/f31. changed dfault_fetch_err to dfault_fetch_ldr31_err and
-// nmiss_fetch_err to nmiss_fetch_ldr31_err.
-// JM 1.00 1-aug-1994 Add pass2 support (swpctx)
-// JM 1.01 2-aug-1994 swppal now passes bc_ctl/bc_config in r1/r2
-// JM 1.02 15-sep-1994 BUG: swpctx missing shift of pme bit to correct position in icsr (pass2)
-// Moved perfmon code here from system file.
-// BUG: pal_perfmon - enable function not saving correct enables when pme not set (pass1)
-// JM 1.03 3-oct-1994 Added (pass2 only) code to wrperfmon enable function to look at pme bit.
-// JM 1.04 14-oct-1994 BUG: trap_interrupt - ISR read (and saved) before INTID -- INTID can change
-// after ISR read, but we won't catch the ISR update. reverse order
-// JM 1.05 17-nov-1994 Add code to dismiss UNALIGN trap if LD r31/F31
-// JM 1.06 28-nov-1994 BUG: missing mm_stat shift for store case in trap_unalign (new bug due to "dismiss" code)
-// JM 1.07 1-dec-1994 EV5 PASS1,2,3 BUG WORKAROUND: Add flag LDVPTE_BUG_FIX. In DTBMISS_DOUBLE, branch to
-// DTBMISS_SINGLE if not in palmode.
-// JM 1.08 9-jan-1995 Bump version number for change to EV5_OSF_SYSTEM_PAL.M64 - ei_stat fix in mchk logout frame
-// JM 1.09 2-feb-1995 Add flag "spe_fix" and accompanying code to workaround pre-pass4 bug: Disable Ibox
-// superpage mode in User mode and re-enable in kernel mode.
-// EV5_OSF_SYSTEM_PAL.M64 and EV5_PALDEF.MAR (added pt_misc_v_cm) also changed to support this.
-// JM 1.10 24-feb-1995 Set ldvpte_bug_fix regardless of ev5 pass. set default to ev5_p2
-// ES 1.11 10-mar-1995 Add flag "osf_chm_fix" to enable dcache in user mode only to avoid
-// cpu bug.
-// JM 1.12 17-mar-1995 BUG FIX: Fix F0 corruption problem in pal_restore_state
-// ES 1.13 17-mar-1995 Refine osf_chm_fix
-// ES 1.14 20-mar-1995 Don't need as many stalls before hw_rei_stall in chm_fix
-// ES 1.15 21-mar-1995 Add a stall to avoid a pvc violation in pal_restore_state
-// Force pvc checking of exit_console
-// ES 1.16 26-apr-1995 In the wrperfmon disable function, correct meaning of R17<2:0> to ctl2,ctl2,ctl0
-// ES 1.17 01-may-1995 In hw_rei_update_spe code, in the osf_chm fix, use bic and bis (self-correcting)
-// instead of xor to maintain previous mode in pt_misc
-// ES 1.18 14-jul-1995 In wrperfmon enable on pass2, update pmctr even if current process does
-// not have pme set. The bits in icsr maintain the master enable state.
-// In sys_reset, add icsr<17>=1 for ev56 byte/word eco enable
-//
#define vmaj 1
#define vmin 18
#define vms_pal 1
#define osf_pal 2
#define pal_type osf_pal
#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0))
-//-
-// .sbttl "PALtemp register usage"
-//+
+///////////////////////////
+// PALtemp register usage
+///////////////////////////
+
// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage
// for these PALtemps:
//
// pt13 reserved for system specific PAL
// pt14 reserved for system specific PAL
// pt15 reserved for system specific PAL
-// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, pt_mces
+// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami,
+// pt_mces
// pt17 sysval pt_sysval
// pt18 usp pt_usp
// pt19 ksp pt_ksp
// pt22 kgp pt_kgp
// pt23 PCBB pt_pcbb
//
-//-
-
-// .sbttl "PALshadow register usage"
//
-//+
+
+
+/////////////////////////////
+// PALshadow register usage
+/////////////////////////////
+
//
// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1.
// This maps the OSF PAL usage of R8 - R14 and R25:
// r14 local scratch
// r25 local scratch
//
-//
-//-
-
-// .sbttl "ALPHA symbol definitions"
-// _OSF_PSDEF GLOBAL
-// _OSF_PTEDEF GLOBAL
-// _OSF_VADEF GLOBAL
-// _OSF_PCBDEF GLOBAL
-// _OSF_SFDEF GLOBAL
-// _OSF_MMCSR_DEF GLOBAL
-// _SCBDEF GLOBAL
-// _FRMDEF GLOBAL
-// _EXSDEF GLOBAL
-// _OSF_A0_DEF GLOBAL
-// _MCESDEF GLOBAL
-
-// .sbttl "EV5 symbol definitions"
-
-// _EV5DEF
-// _PALTEMP
-// _MM_STAT_DEF
-// _EV5_MM
-// _EV5_IPLDEF
-
-// _HALT_CODES GLOBAL
-// _MCHK_CODES GLOBAL
-
-// _PAL_IMPURE
-// _PAL_LOGOUT
-
// the following). The options that can be adjusted cause the resultant PALcode
// to reflect the desired target system.
-
-#define osfpal 1 // This is the PALcode for OSF.
-
-#ifndef rawhide_system
-
-#define rawhide_system 0
-#endif
-
-
-#ifndef real_mm
-// Page table translation vs 1-1 mapping
-#define real_mm 1
-#endif
-
-
-#ifndef rax_mode
-
-#define rax_mode 0
-#endif
-
-#ifndef egore
-// End of reset flow starts a program at 200000(hex).
-#define egore 1
-#endif
-
-#ifndef acore
-// End of reset flow starts a program at 40000(hex).
-#define acore 0
-#endif
-
-
-// assume acore+egore+rax_mode lt 2 // Assertion checker
-
-#ifndef beh_model
-// EV5 behavioral model specific code
-#define beh_model 1
-#endif
-
-#ifndef init_cbox
-// Reset flow init of Bcache and Scache
-#define init_cbox 1
-#endif
-
-#ifndef disable_crd
-// Decides whether the reset flow will disable
-#define disable_crd 0
-#endif
-
- // correctable read interrupts via ICSR
-#ifndef perfmon_debug
-#define perfmon_debug 0
-#endif
-
-#ifndef icflush_on_tbix
-#define icflush_on_tbix 0
-#endif
-
-#ifndef remove_restore_state
-#define remove_restore_state 0
-#endif
-
-#ifndef remove_save_state
-#define remove_save_state 0
-#endif
-
-#ifndef enable_physical_console
-#define enable_physical_console 0
-#endif
-
-#ifndef ev5_p1
-#define ev5_p1 0
-#endif
-
-#ifndef ev5_p2
-#define ev5_p2 1
-#endif
-
-// assume ev5_p1+ev5_p2 eq 1
-
-#ifndef ldvpte_bug_fix
-#define ldvpte_bug_fix 1 // If set, fix ldvpte bug in dtbmiss_double flow.
-#endif
-
-#ifndef spe_fix
-// If set, disable super-page mode in user mode and re-enable
-#define spe_fix 0
-#endif
- // in kernel. Workaround for cpu bug.
-#ifndef build_fixed_image
-#define build_fixed_image 0
-#endif
-
-
-#ifndef fill_err_hack
-// If set, disable fill_error mode in user mode and re-enable
-#define fill_err_hack 0
-#endif
-
- // in kernel. Workaround for cpu bug.
-
-// .macro hw_rei_spe
-// .iif eq spe_fix, hw_rei
-//#if spe_fix != 0
-//
-//
-//#define hw_rei_chm_count hw_rei_chm_count + 1
-// p4_fixup_label \hw_rei_chm_count
-// .iif eq build_fixed_image, br r31, hw_rei_update_spe
-// .iif ne build_fixed_image, hw_rei
-//#endif
-//
-// .endm
-
-// Add flag "osf_chm_fix" to enable dcache in user mode only
-// to avoid cpu bug.
-
-#ifndef osf_chm_fix
-// If set, enable D-Cache in
-#define osf_chm_fix 0
-#endif
-
-#if osf_chm_fix != 0
-// user mode only.
-#define hw_rei_chm_count 0
-#endif
-
-#if osf_chm_fix != 0
-
-#define hw_rei_stall_chm_count 0
-#endif
-
-#ifndef enable_p4_fixups
-
-#define enable_p4_fixups 0
-#endif
-
- // If set, do EV5 Pass 4 fixups
-#if spe_fix == 0
-
-#define osf_chm_fix 0
-#endif
-
-#if spe_fix == 0
-
-#define enable_p4_fixups 0
-#endif
-
- // Only allow fixups if fix enabled
-
- //Turn off fill_errors and MEM_NEM in user mode
-// .macro fill_error_hack ?L10_, ?L20_, ?L30_, ?L40_
-// //save r22,r23,r24
-// stqp r22, 0x150(r31) //add
-// stqp r23, 0x158(r31) //contents
-// stqp r24, 0x160(r31) //bit mask
-//
-// lda r22, 0x82(r31)
-// ldah r22, 0x8740(r22)
-// sll r22, 8, r22
-// ldlp r23, 0x80(r22) // r23 <- contents of CIA_MASK
-// bis r23,r31,r23
-//
-// lda r24, 0x8(r31) // r24 <- MEM_NEM bit
-// beq r10, L10_ // IF user mode (r10<0> == 0) pal mode
-// bic r23, r24, r23 // set fillerr_en bit
-// br r31, L20_ // ELSE
-//L10_: bis r23, r24, r23 // clear fillerr_en bit
-//L20_: // ENDIF
-//
-// stlp r23, 0x80(r22) // write back the CIA_MASK register
-// mb
-// ldlp r23, 0x80(r22)
-// bis r23,r31,r23
-// mb
-//
-// lda r22, 1(r31) // r22 <- 87.4000.0100 ptr to CIA_CTRL
-// ldah r22, 0x8740(r22)
-// sll r22, 8, r22
-// ldlp r23, 0(r22) // r23 <- contents of CIA_CTRL
-// bis r23,r31,r23
-//
-//
-// lda r24, 0x400(r31) // r9 <- fillerr_en bit
-// beq r10, L30_ // IF user mode (r10<0> == 0) pal mode
-// bic r23, r24, r23 // set fillerr_en bit
-// br r31, L40_ // ELSE
-//L30_: bis r23, r24, r23 // clear fillerr_en bit
-//L40_: // ENDIF
-//
-// stlp r23, 0(r22) // write back the CIA_CTRL register
-// mb
-// ldlp r23, 0(r22)
-// bis r23,r31,r23
-// mb
-//
-// //restore r22,r23,r24
-// ldqp r22, 0x150(r31)
-// ldqp r23, 0x158(r31)
-// ldqp r24, 0x160(r31)
-//
-// .endm
-
// multiprocessor support can be enabled for a max of n processors by
// setting the following to the number of processors on the system.
// Note that this is really the max cpuid.
+#define max_cpuid 1
#ifndef max_cpuid
#define max_cpuid 8
#endif
-#ifndef osf_svmin // platform specific palcode version number
-#define osf_svmin 0
-#endif
-
-
+#define osf_svmin 1
#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0))
-// .mcall ldqp // override macro64 definition with macro from library
-// .mcall stqp // override macro64 definition with macro from library
-
-
-// .psect _pal,mix
-// huh pb pal_base:
-// huh pb #define current_block_base . - pal_base
-
-// .sbttl "RESET - Reset Trap Entry Point"
-//+
+//
+// RESET - Reset Trap Entry Point
+//
// RESET - offset 0000
// Entry:
// Vectored into via hardware trap on reset, or branched to
//
// Function:
//
-//-
+//
.text 0
. = 0x0000
+ .globl _start
.globl Pal_Base
+_start:
Pal_Base:
HDW_VECTOR(PAL_RESET_ENTRY)
Trap_Reset:
nop
-#ifdef SIMOS
/*
* store into r1
*/
br r1,sys_reset
-#else
- /* following is a srcmax change */
-
- DEBUGSTORE(0x41)
- /* The original code jumped using r1 as a linkage register to pass the base
- of PALcode to the platform specific code. We use r1 to pass a parameter
- from the SROM, so we hardcode the address of Pal_Base in platform.s
- */
- br r31, sys_reset
-#endif
// Specify PAL version info as a constant
// at a known location (reset + 8).
.quad 0
pal_debug_ptr:
.quad 0 // reserved for debug pointer ; 20
-#if beh_model == 0
-
-
-#if enable_p4_fixups != 0
-
-
- .quad 0
- .long p4_fixup_hw_rei_fixup_table
-#endif
-
-#else
-
- .quad 0 //
- .quad 0 //0x0030
- .quad 0
- .quad 0 //0x0040
- .quad 0
- .quad 0 //0x0050
- .quad 0
- .quad 0 //0x0060
- .quad 0
-pal_enter_cns_address:
- .quad 0 //0x0070 -- address to jump to from enter_console
- .long <<sys_exit_console-pal_base>+1> //0x0078 -- offset to sys_exit_console (set palmode bit)
-#endif
-
-
-// .sbttl "IACCVIO- Istream Access Violation Trap Entry Point"
-
-//+
+//
+// IACCVIO - Istream Access Violation Trap Entry Point
+//
// IACCVIO - offset 0080
// Entry:
// Vectored into via hardware trap on Istream access violation or sign check error on PC.
// a1 <- MMCSR (1 for ACV)
// a2 <- -1 (for ifetch fault)
// vector via entMM
-//-
+//
HDW_VECTOR(PAL_IACCVIO_ENTRY)
Trap_Iaccvio:
hw_rei_spe
-// .sbttl "INTERRUPT- Interrupt Trap Entry Point"
-
-//+
+//
+// INTERRUPT - Interrupt Trap Entry Point
+//
// INTERRUPT - offset 0100
// Entry:
// Vectored into via trap on hardware interrupt
// Function:
// check for halt interrupt
// check for passive release (current ipl geq requestor)
-// if necessary, switch to kernel mode
-// push stack frame, update ps (including current mode and ipl copies), sp, and gp
+// if necessary, switch to kernel mode push stack frame,
+// update ps (including current mode and ipl copies), sp, and gp
// pass the interrupt info to the system module
//
-//-
-
-
+//
HDW_VECTOR(PAL_INTERRUPT_ENTRY)
Trap_Interrupt:
mfpr r13, ev5__intid // Fetch level of interruptor
mfpr r12, pt_intmask
and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already)
-#ifdef SIMOS
/*
* Lance had space problems. We don't.
*/
extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
mfpr r29, pt_kgp // update gp
mtpr r14, ev5__ipl // load the new IPL into Ibox
-#else
-// Moved the following three lines to sys_interrupt to make room for debug
-// extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
-// mfpr r29, pt_kgp // update gp
-
-// mtpr r14, ev5__ipl // load the new IPL into Ibox
-#endif
br r31, sys_interrupt // Go handle interrupt
-// .sbttl "ITBMISS- Istream TBmiss Trap Entry Point"
-
-//+
+//
+// ITBMISS - Istream TBmiss Trap Entry Point
+//
// ITBMISS - offset 0180
// Entry:
// Vectored into via hardware trap on Istream translation buffer miss.
// Can trap into DTBMISS_DOUBLE.
// This routine can use the PALshadow registers r8, r9, and r10
//
-//-
+//
HDW_VECTOR(PAL_ITB_MISS_ENTRY)
Trap_Itbmiss:
-#if real_mm == 0
-
-
- // Simple 1-1 va->pa mapping
-
- nop // Pad to align to E1
- mfpr r8, exc_addr
-
- srl r8, page_offset_size_bits, r9
- sll r9, 32, r9
-
- lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
- mtpr r9, itb_pte // E1
-
- hw_rei_stall // Nital says I don't have to obey shadow wait rule here.
-#else
-
- // Real MM mapping
+ // Real MM mapping
nop
mfpr r8, ev5__ifault_va_form // Get virtual address of PTE.
hw_rei_stall //
-#endif
-
-
-
-// .sbttl "DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point"
-
-//+
+//
+// DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point
+//
// DTBMISS_SINGLE - offset 0200
// Entry:
-// Vectored into via hardware trap on Dstream single translation buffer miss.
+// Vectored into via hardware trap on Dstream single translation
+// buffer miss.
//
// Function:
// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid.
// Can trap into DTBMISS_DOUBLE.
// This routine can use the PALshadow registers r8, r9, and r10
-//-
+//
HDW_VECTOR(PAL_DTB_MISS_ENTRY)
Trap_Dtbmiss_Single:
-#if real_mm == 0
- // Simple 1-1 va->pa mapping
- mfpr r8, va // E0
- srl r8, page_offset_size_bits, r9
-
- sll r9, 32, r9
- lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
-
- mtpr r9, dtb_pte // E0
- nop // Pad to align to E0
-
-
-
- mtpr r8, dtb_tag // E0
- nop
-
- nop // Pad tag write
- nop
-
- nop // Pad tag write
- nop
-
- hw_rei
-#else
mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0.
mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1.
mfpr r31, pt0 // Pad the write to dtb_tag
hw_rei // Done, return
-#endif
-
-
-// .sbttl "DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point"
-
-//+
+//
+// DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point
+//
+//
// DTBMISS_DOUBLE - offset 0280
// Entry:
-// Vectored into via hardware trap on Double TBmiss from single miss flows.
+// Vectored into via hardware trap on Double TBmiss from single
+// miss flows.
//
// r8 - faulting VA
// r9 - original MMstat
// pt4 and pt5 are reserved for this flow.
//
//
-//-
+//
HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY)
Trap_Dtbmiss_double:
-#if ldvpte_bug_fix != 0
mtpr r8, pt4 // save r8 to do exc_addr check
mfpr r8, exc_addr
blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy!
mfpr r8, pt4 // restore r8
-#endif
nop
mtpr r22, pt5 // Get some scratch space. E1.
// Due to virtual scheme, we can skip the first lookup and go
addq r21, r22, r21 // Index into page table for level 2 PTE.
sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA
- ldqp r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
+ ldq_p r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8
blbc r21, double_pte_inv // Check for Invalid PTE.
addq r21, r22, r21 // Index into page table for level 3 PTE.
nop
- ldqp r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
+ ldq_p r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
blbc r21, double_pte_inv // Check for invalid PTE.
mtpr r21, ev5__dtb_pte // Write the PTE. E0.
-// .sbttl "UNALIGN -- Dstream unalign trap"
-//+
+//
+// UNALIGN -- Dstream unalign trap
+//
// UNALIGN - offset 0300
// Entry:
// Vectored into via hardware trap on unaligned Dstream reference.
// a1 <- Opcode
// a2 <- src/dst register number
// vector via entUna
-//-
+//
HDW_VECTOR(PAL_UNALIGN_ENTRY)
Trap_Unalign:
br r31, unalign_trap_cont
-
-
-// .sbttl "DFAULT - Dstream Fault Trap Entry Point"
-
-//+
+//
+// DFAULT - Dstream Fault Trap Entry Point
+//
// DFAULT - offset 0380
// Entry:
-// Vectored into via hardware trap on dstream fault or sign check error on DVA.
+// Vectored into via hardware trap on dstream fault or sign check
+// error on DVA.
//
// Function:
// Ignore faults on FETCH/FETCH_M
// a2 <- R/W
// vector via entMM
//
-//-
+//
HDW_VECTOR(PAL_D_FAULT_ENTRY)
Trap_Dfault:
// DEBUGSTORE(0x48)
br r31, dfault_trap_cont
-
-
-
-// .sbttl "MCHK - Machine Check Trap Entry Point"
-
-//+
+//
+// MCHK - Machine Check Trap Entry Point
+//
// MCHK - offset 0400
// Entry:
// Vectored into via hardware trap on machine check.
//
// Function:
//
-//-
+//
HDW_VECTOR(PAL_MCHK_ENTRY)
Trap_Mchk:
br r31, sys_machine_check
-
-
-// .sbttl "OPCDEC - Illegal Opcode Trap Entry Point"
-
-//+
+//
+// OPCDEC - Illegal Opcode Trap Entry Point
+//
// OPCDEC - offset 0480
// Entry:
// Vectored into via hardware trap on illegal opcode.
// a2 <- unpred
// vector via entIF
//
-//-
+//
HDW_VECTOR(PAL_OPCDEC_ENTRY)
Trap_Opcdec:
hw_rei_spe // done, E1
-
-
-
-
-// .sbttl "ARITH - Arithmetic Exception Trap Entry Point"
-
-//+
+//
+// ARITH - Arithmetic Exception Trap Entry Point
+//
// ARITH - offset 0500
// Entry:
// Vectored into via hardware trap on arithmetic excpetion.
// a2 <- unpred
// vector via entArith
//
-//-
+//
HDW_VECTOR(PAL_ARITH_ENTRY)
Trap_Arith:
DEBUGSTORE(0x4b)
bis r25, r31, r11 // set new ps
stq r16, osfsf_a0(sp) // save regs
- srl r13, exc_sum_v_swc, r16// shift data to correct position
+ srl r13, exc_sum_v_swc, r16 // shift data to correct position
stq r18, osfsf_a2(sp)
// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow
hw_rei_spe // done - E1
-
-
-
-
-// .sbttl "FEN - Illegal Floating Point Operation Trap Entry Point"
-
-//+
+//
+// FEN - Illegal Floating Point Operation Trap Entry Point
+//
// FEN - offset 0580
// Entry:
// Vectored into via hardware trap on illegal FP op.
// a2 <- unpred
// vector via entIF
//
-//-
+//
HDW_VECTOR(PAL_FEN_ENTRY)
Trap_Fen:
-// .sbttl "Misc handlers"
- // Start area for misc code.
-//+
-//dfault_trap_cont
+//////////////////////////////////////////////////////////////////////////////
+// Misc handlers - Start area for misc code.
+//////////////////////////////////////////////////////////////////////////////
+
+//
+// dfault_trap_cont
// A dfault trap has been taken. The sp has been updated if necessary.
// Push a stack frame a vector via entMM.
//
// r13 - MMstat
// VA - locked
//
-//-
+//
ALIGN_BLOCK
dfault_trap_cont:
lda sp, 0-osfsf_c_size(sp)// allocate stack space
hw_rei_spe // done
-//+
+//
//unalign_trap_cont
// An unalign trap has been taken. Just need to finish up a few things.
//
// r25 - entUna
// r13 - shifted MMstat
//
-//-
+//
ALIGN_BLOCK
unalign_trap_cont:
mtpr r25, exc_addr // load exc_addr with entUna
-//+
+//
// dfault_in_pal
// Dfault trap was taken, exc_addr points to a PAL PC.
// r9 - mmstat<opcode> right justified
// r11 - original PS
//
//
-//-
+//
ALIGN_BLOCK
dfault_in_pal:
DEBUGSTORE(0x50)
mfpr r9, pal_base
mfpr r31, va // unlock VA
-#if real_mm != 0
- // if not real_mm, should never get here from miss flows
+
+ // if not real_mm, should never get here from miss flows
subq r9, r8, r8 // pal_base - offset
lda r9, pal_dtb_ldq-pal_base(r8)
beq r9, dfault_do_bugcheck
-#endif
//
// KSP invalid halt case --
mtpr r31, ips
mtpr r14, exc_addr // Set PC to instruction that caused trouble
-//orig pvc_jsr updpcb, bsr=1
bsr r0, pal_update_pcb // update the pcb
lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt
br r31, pal_pal_bug_check
- ALIGN_BLOCK
-//+
+//
// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31
// On entry -
// r14 - exc_addr
// VA is locked
//
-//-
+//
+ ALIGN_BLOCK
dfault_fetch_ldr31_err:
mtpr r11, ev5__dtb_cm
mtpr r11, ev5__ps // Make sure ps hasn't changed
ALIGN_BLOCK
-//+
+//
// sys_from_kern
// callsys from kernel mode - OS bugcheck machine check
//
-//-
+//
sys_from_kern:
mfpr r14, exc_addr // PC points to call_pal
subq r14, 4, r14
br r31, pal_pal_mchk
-// .sbttl "Continuation of long call_pal flows"
- ALIGN_BLOCK
-//+
+// Continuation of long call_pal flows
+//
// wrent_tbl
// Table to write *int in paltemps.
// 4 instructions/entry
// r16 has new value
//
-//-
+//
+ ALIGN_BLOCK
wrent_tbl:
//orig pvc_jsr wrent, dest=1
nop
hw_rei
ALIGN_BLOCK
-//+
+//
// tbi_tbl
// Table to do tbi instructions
// 4 instructions per entry
-//-
+//
tbi_tbl:
// -2 tbia
//orig pvc_jsr tbi, dest=1
mtpr r31, ev5__dtb_ia // Flush DTB
mtpr r31, ev5__itb_ia // Flush ITB
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush // Flush Icache
-#else
-
hw_rei_stall
-#endif
nop // Pad table
mtpr r31, ev5__dtb_iap // Flush DTB
mtpr r31, ev5__itb_iap // Flush ITB
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush // Flush Icache
-#else
-
hw_rei_stall
-#endif
nop // Pad table
// 1 tbisi
//orig pvc_jsr tbi, dest=1
-#if icflush_on_tbix != 0
-
-
-
- nop
- br r31, pal_ic_flush_and_tbisi // Flush Icache
- nop
- nop // Pad table
-#else
nop
nop
mtpr r17, ev5__itb_is // Flush ITB
hw_rei_stall
-#endif
-
-
// 2 tbisd
//orig pvc_jsr tbi, dest=1
// 3 tbis
//orig pvc_jsr tbi, dest=1
mtpr r17, ev5__dtb_is // Flush DTB
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush_and_tbisi // Flush Icache and ITB
-#else
br r31, tbi_finish
ALIGN_BRANCH
tbi_finish:
mtpr r17, ev5__itb_is // Flush ITB
hw_rei_stall
-#endif
ALIGN_BLOCK
-//+
+//
// bpt_bchk_common:
// Finish up the bpt/bchk instructions
-//-
+//
bpt_bchk_common:
stq r18, osfsf_a2(sp) // a2
mfpr r13, pt_entif // get entry point
ALIGN_BLOCK
-//+
+//
// rti_to_user
// Finish up the rti instruction
-//-
+//
rti_to_user:
mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
ALIGN_BLOCK
-//+
+//
// rti_to_kern
// Finish up the rti instruction
-//-
+//
rti_to_kern:
and r12, osfps_m_ipl, r11 // clean ps
mfpr r12, pt_intmask // get int mask
hw_rei
ALIGN_BLOCK
-//+
+//
// swpctx_cont
// Finish up the swpctx instruction
-//-
+//
swpctx_cont:
-#if ev5_p1 != 0
-
-
- bic r25, r24, r25 // clean icsr<FPE>
- get_impure r8 // get impure pointer
-
- sll r12, icsr_v_fpe, r12 // shift new fen to pos
- fix_impure_ipr r8 // adjust impure pointer
-
- restore_reg1 pmctr_ctl, r8, r8, ipr=1 // "ldqp" - get pmctr_ctl bits
- srl r23, 32, r24 // move asn to low asn pos
-
- ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
- srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
-
- or r25, r12, r25 // icsr with new fen
- sll r24, itb_asn_v_asn, r12
-
-#else
bic r25, r24, r25 // clean icsr<FPE,PMP>
sll r12, icsr_v_fpe, r12 // shift new fen to pos
- ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
+ ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr
srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
or r25, r12, r25 // icsr with new fen
nop
or r25, r22, r25 // icsr with new pme
-#endif
sll r24, dtb_asn_v_asn, r24
mtpr r25, icsr // write the icsr
sll r14, page_offset_size_bits, r14 // Move PTBR into internal position.
- ldqp r25, osfpcb_q_usp(r16) // get new usp
+ ldq_p r25, osfpcb_q_usp(r16) // get new usp
insll r13, 4, r13 // >> 32
-// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
+// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow
mtpr r14, pt_ptbr // load the new ptbr
mtpr r13, cc // set new offset
- ldqp r30, osfpcb_q_ksp(r16) // get new ksp
+ ldq_p r30, osfpcb_q_ksp(r16) // get new ksp
-// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
+// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow
mtpr r25, pt_usp // save usp
-#if ev5_p1 != 0
-
-
- blbc r8, no_pm_change // if monitoring all processes -- no need to change pm
-
- // otherwise, monitoring select processes - update pm
- lda r25, 0x3F(r31)
- cmovlbc r22, r31, r8 // if pme set, disable counters, otherwise use saved encodings
-
- sll r25, pmctr_v_ctl2, r25 // create ctl field bit mask
- mfpr r22, ev5__pmctr
-
- and r8, r25, r8 // mask new ctl value
- bic r22, r25, r22 // clear ctl field in pmctr
-
- or r8, r22, r8
- mtpr r8, ev5__pmctr
-
-no_pm_change:
-#endif
-
-
-#if osf_chm_fix != 0
-
-
- p4_fixup_hw_rei_stall // removes this section for Pass 4 by placing a hw_rei_stall here
-
-#if build_fixed_image != 0
-
-
- hw_rei_stall
-#else
-
- mfpr r9, pt_pcbb // get FEN
-#endif
-
- ldqp r9, osfpcb_q_fen(r9)
- blbc r9, no_pm_change_10_ // skip if FEN disabled
-
- mb // ensure no outstanding fills
- lda r12, 1<<dc_mode_v_dc_ena(r31)
- mtpr r12, dc_mode // turn dcache on so we can flush it
- nop // force correct slotting
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
-
- lda r8, 0(r31) // flood the dcache with junk data
-no_pm_change_5_: ldqp r31, 0(r8)
- lda r8, 0x20(r8) // touch each cache block
- srl r8, 13, r9
- blbc r9, no_pm_change_5_
-
- mb // ensure no outstanding fills
- mtpr r31, dc_mode // turn the dcache back off
- nop // force correct slotting
- mfpr r31, pt0 // no hw_rei_stall in 0,1
-#endif
-
-
no_pm_change_10_: hw_rei_stall // back we go
ALIGN_BLOCK
-//+
+//
// swppal_cont - finish up the swppal call_pal
-//-
+//
swppal_cont:
mfpr r2, pt_misc // get misc bits
// .sbttl "Memory management"
ALIGN_BLOCK
-//+
+//
//foe_ipte_handler
// IFOE detected on level 3 pte, sort out FOE vs ACV
//
// Function
// Determine TNV vs ACV vs FOE. Build stack and dispatch
// Will not be here if TNV.
-//-
+//
foe_ipte_handler:
sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
hw_rei_spe // out to exec
ALIGN_BLOCK
-//+
+//
//invalid_ipte_handler
// TNV detected on level 3 pte, sort out TNV vs ACV
//
//
// Function
// Determine TNV vs ACV. Build stack and dispatch.
-//-
+//
invalid_ipte_handler:
sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
ALIGN_BLOCK
-//+
+//
//invalid_dpte_handler
// INVALID detected on level 3 pte, sort out TNV vs ACV
//
//
// Function
// Determine TNV vs ACV. Build stack and dispatch
-//-
+//
invalid_dpte_handler:
hw_rei_spe // out to exec
-//+
+//
//
// We come here if we are erring on a dtb_miss, and the instr is a
// fetch, fetch_m, of load to r31/f31.
// The PC is incremented, and we return to the program.
// essentially ignoring the instruction and error.
//
-//-
+//
ALIGN_BLOCK
nmiss_fetch_ldr31_err:
mfpr r12, pt6
hw_rei //
ALIGN_BLOCK
-//+
-// double_pte_inv
-// We had a single tbmiss which turned into a double tbmiss which found
-// an invalid PTE. Return to single miss with a fake pte, and the invalid
-// single miss flow will report the error.
-//
-// on entry:
-// r21 PTE
-// r22 available
-// VA IPR locked with original fault VA
-// pt4 saved r21
-// pt5 saved r22
-// pt6 original exc_addr
-//
-// on return to tbmiss flow:
-// r8 fake PTE
-//
-//
-//-
-double_pte_inv:
- srl r21, osfpte_v_kre, r21 // get the kre bit to <0>
- mfpr r22, exc_addr // get the pc
-
- lda r22, 4(r22) // inc the pc
- lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set
-
- cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0
- mtpr r22, exc_addr // set for rei
-
- mfpr r21, pt4 // restore regs
- mfpr r22, pt5 // restore regs
-
- hw_rei // back to tb miss
-
- ALIGN_BLOCK
-//+
-//tnv_in_pal
-// The only places in pal that ld or store are the
-// stack builders, rti or retsys. Any of these mean we
-// need to take a ksp not valid halt.
//
-//-
-tnv_in_pal:
-
-
- br r31, ksp_inval_halt
-
-
-// .sbttl "Icache flush routines"
-
- ALIGN_BLOCK
-//+
-// Common Icache flush routine.
-//
-//
-//-
-pal_ic_flush:
- nop
- mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
- nop
- nop
-
-// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20)
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 10
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 20
-
- nop
- nop
- nop
- nop
+// double_pte_inv
+// We had a single tbmiss which turned into a double tbmiss which found
+// an invalid PTE. Return to single miss with a fake pte, and the invalid
+// single miss flow will report the error.
+//
+// on entry:
+// r21 PTE
+// r22 available
+// VA IPR locked with original fault VA
+// pt4 saved r21
+// pt5 saved r22
+// pt6 original exc_addr
+//
+// on return to tbmiss flow:
+// r8 fake PTE
+//
+//
+//
+double_pte_inv:
+ srl r21, osfpte_v_kre, r21 // get the kre bit to <0>
+ mfpr r22, exc_addr // get the pc
- nop
- nop
- nop
- nop
+ lda r22, 4(r22) // inc the pc
+ lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set
- nop
- nop // 30
- nop
- nop
- nop
- nop
+ cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0
+ mtpr r22, exc_addr // set for rei
- nop
- nop
- nop
- nop
+ mfpr r21, pt4 // restore regs
+ mfpr r22, pt5 // restore regs
- nop
- nop // 40
+ hw_rei // back to tb miss
- nop
- nop
+ ALIGN_BLOCK
+//
+//tnv_in_pal
+// The only places in pal that ld or store are the
+// stack builders, rti or retsys. Any of these mean we
+// need to take a ksp not valid halt.
+//
+//
+tnv_in_pal:
-one_cycle_and_hw_rei:
- nop
- nop
- hw_rei_stall
+ br r31, ksp_inval_halt
-#if icflush_on_tbix != 0
+// .sbttl "Icache flush routines"
ALIGN_BLOCK
-
-//+
-// Common Icache flush and ITB invalidate single routine.
-// ITBIS and hw_rei_stall must be in same octaword.
-// r17 - has address to invalidate
//
-//-
-PAL_IC_FLUSH_AND_TBISI:
+// Common Icache flush routine.
+//
+//
+//
+pal_ic_flush:
nop
mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
nop
nop
nop // 40
-
nop
nop
+one_cycle_and_hw_rei:
nop
nop
- // A quadword is 64 bits, so an octaword is 128 bits -> 16 bytes -> 4 instructions
- // 44 nops plus 4 instructions before it is 48 instructions.
- // Since this routine started on a 32-byte (8 instruction) boundary,
- // the following 2 instructions will be in the same octword as required.
-// ALIGN_BRANCH
- mtpr r17, ev5__itb_is // Flush ITB
hw_rei_stall
-#endif
-
ALIGN_BLOCK
-//+
+//
//osfpal_calpal_opcdec
// Here for all opcdec CALL_PALs
//
// a2 <- unpred
// vector via entIF
//
-//-
+//
osfpal_calpal_opcdec:
sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
-//+
+//
//pal_update_pcb
// Update the PCB with the current SP, AST, and CC info
//
// r0 - return linkage
-//-
+//
ALIGN_BLOCK
pal_update_pcb:
and r11, osfps_m_mode, r25 // get mode
beq r25, pal_update_pcb_10_ // in kern? no need to update user sp
mtpr r30, pt_usp // save user stack
- stqp r30, osfpcb_q_usp(r12) // store usp
+ stq_p r30, osfpcb_q_usp(r12) // store usp
br r31, pal_update_pcb_20_ // join common
-pal_update_pcb_10_: stqp r30, osfpcb_q_ksp(r12) // store ksp
+pal_update_pcb_10_: stq_p r30, osfpcb_q_ksp(r12) // store ksp
pal_update_pcb_20_: rpcc r13 // get cyccounter
srl r13, 32, r14 // move offset
addl r13, r14, r14 // merge for new time
- stlp r14, osfpcb_l_cc(r12) // save time
+ stl_p r14, osfpcb_l_cc(r12) // save time
//orig pvc_jsr updpcb, bsr=1, dest=1
ret r31, (r0)
-
-#if remove_save_state == 0
-
-// .sbttl "PAL_SAVE_STATE"
-//+
//
-// Pal_save_state
+// pal_save_state
//
// Function
// All chip state saved, all PT's, SR's FR's, IPR's
// r3 = return_address
// r4 = scratch
//
-//-
-
+//
ALIGN_BLOCK
.globl pal_save_state
// Get out of shadow mode
//
- mfpr r2, icsr // Get icsr //orig
-//orig ldah r0, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
+ mfpr r2, icsr // Get icsr
ldah r0, (1<<(icsr_v_sde-16))(r31)
- bic r2, r0, r0 // ICSR with SDE clear //orig
- mtpr r0, icsr // Turn off SDE //orig
+ bic r2, r0, r0 // ICSR with SDE clear
+ mtpr r0, icsr // Turn off SDE
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
+ mfpr r31, pt0 // SDE bubble cycle 1
+ mfpr r31, pt0 // SDE bubble cycle 2
+ mfpr r31, pt0 // SDE bubble cycle 3
+ nop
// save integer regs R4-r31
-//orig #define t 4
-//orig .repeat 28
-//orig store_reg \t
-//orig #define t t + 1
-//orig .endr
SAVE_GPR(r4,CNS_Q_GPR+0x20,r1)
SAVE_GPR(r5,CNS_Q_GPR+0x28,r1)
SAVE_GPR(r6,CNS_Q_GPR+0x30,r1)
//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores
//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores
-//orig #define t 1
-//orig .repeat 23
-//orig store_reg \t , pal=1
-//orig #define t t + 1
-//orig .endr
lda r1, -0x200(r1) // Restore the impure base address.
lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area.
SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1)
// Restore shadow mode
- mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) //orig
- mfpr r31, pt0 //orig
- mtpr r2, icsr // Restore original ICSR //orig
+ mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write)
+ mfpr r31, pt0
+ mtpr r2, icsr // Restore original ICSR
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
+ mfpr r31, pt0 // SDE bubble cycle 1
+ mfpr r31, pt0 // SDE bubble cycle 2
+ mfpr r31, pt0 // SDE bubble cycle 3
+ nop
// save all integer shadow regs
-
-//orig #define t 8
-//orig .repeat 7
-//orig store_reg \t, shadow=1
-//orig #define t t + 1
-//orig .endr
-//orig store_reg 25, shadow=1
-
SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code
SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1)
SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1)
SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1)
SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1)
-//orig store_reg exc_addr, ipr=1 // save ipr
-//orig store_reg pal_base, ipr=1 // save ipr
-//orig store_reg mm_stat, ipr=1 // save ipr
-//orig store_reg va, ipr=1 // save ipr
-//orig store_reg icsr, ipr=1 // save ipr
-//orig store_reg ipl, ipr=1 // save ipr
-//orig store_reg ps, ipr=1 // save ipr
-//orig store_reg itb_asn, ipr=1 // save ipr
-//orig store_reg aster, ipr=1 // save ipr
-//orig store_reg astrr, ipr=1 // save ipr
-//orig store_reg sirr, ipr=1 // save ipr
-//orig store_reg isr, ipr=1 // save ipr
-//orig store_reg ivptbr, ipr=1 // save ipr
-//orig store_reg mcsr, ipr=1 // save ipr
-//orig store_reg dc_mode, ipr=1 // save ipr
-
SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1)
SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1)
SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1)
//the following iprs are informational only -- will not be restored
-//orig store_reg icperr_stat, ipr=1
-//orig store_reg pmctr, ipr=1
-//orig store_reg intid, ipr=1
-//orig store_reg exc_sum, ipr=1
-//orig store_reg exc_mask, ipr=1
-//orig ldah r14, 0xfff0(r31)
-//orig zap r14, 0xE0, r14 // Get Cbox IPR base
-//orig nop // pad mf dcperr_stat out of shadow of last store
-//orig nop
-//orig nop
-//orig store_reg dcperr_stat, ipr=1
-
SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1)
SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1)
SAVE_IPR(intId,CNS_Q_INT_ID,r1)
// read cbox ipr state
-//orig mb
-//orig ldqp r2, ev5__sc_ctl(r14)
-//orig ldqp r13, ld_lock(r14)
-//orig ldqp r4, ev5__sc_addr(r14)
-//orig ldqp r5, ev5__ei_addr(r14)
-//orig ldqp r6, ev5__bc_tag_addr(r14)
-//orig ldqp r7, ev5__fill_syn(r14)
-//orig bis r5, r4, r31
-//orig bis r7, r6, r31 // make sure previous loads finish before reading stat registers which unlock them
-//orig ldqp r8, ev5__sc_stat(r14) // unlocks sc_stat,sc_addr
-//orig ldqp r9, ev5__ei_stat(r14) // may unlock ei_*, bc_tag_addr, fill_syn
-//orig ldqp r31, ev5__ei_stat(r14) // ensures it is really unlocked
-//orig mb
-
-#ifndef SIMOS
mb
ldq_p r2, scCtl(r14)
ldq_p r13, ldLock(r14)
ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn.
ldq_p zero, eiStat(r14) // Make sure it is really unlocked.
mb
-#endif
-//orig // save cbox ipr state
-//orig store_reg1 sc_ctl, r2, r1, ipr=1
-//orig store_reg1 ld_lock, r13, r1, ipr=1
-//orig store_reg1 sc_addr, r4, r1, ipr=1
-//orig store_reg1 ei_addr, r5, r1, ipr=1
-//orig store_reg1 bc_tag_addr, r6, r1, ipr=1
-//orig store_reg1 fill_syn, r7, r1, ipr=1
-//orig store_reg1 sc_stat, r8, r1, ipr=1
-//orig store_reg1 ei_stat, r9, r1, ipr=1
-//orig //bc_config? sl_rcv?
+ // save cbox ipr state
SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1);
SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1);
SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1);
SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1);
SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1);
SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1);
+ //bc_config? sl_rcv?
-// restore impure base //orig
+// restore impure base
//orig unfix_impure_ipr r1
lda r1, -CNS_Q_IPR(r1)
-// save all floating regs //orig
- mfpr r0, icsr // get icsr //orig
- or r31, 1, r2 // get a one //orig
-//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot //orig
+// save all floating regs
+ mfpr r0, icsr // get icsr
+ or r31, 1, r2 // get a one
sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position
- or r2, r0, r0 // set FEN on //orig
- mtpr r0, icsr // write to icsr, enabling FEN //orig
+ or r2, r0, r0 // set FEN on
+ mtpr r0, icsr // write to icsr, enabling FEN
// map the save area virtually
-// orig mtpr r31, dtb_ia // clear the dtb
-// orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
-// orig sll r0, 32, r0 // shift to PFN field
-// orig lda r2, 0xff(r31) // all read enable and write enable bits set
-// orig sll r2, 8, r2 // move to PTE location
-// orig addq r0, r2, r0 // combine with PFN
-// orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-// orig mtpr r1, dtb_tag // write TB tag
-
mtpr r31, dtbIa // Clear all DTB entries
srl r1, va_s_off, r0 // Clean off byte-within-page offset
sll r0, pte_v_pfn, r0 // Shift to form PFN
mtpr r1, dtbTag // Write the PTE and tag into the DTB
-//orig // map the next page too - in case the impure area crosses a page boundary
-//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
-//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r4, dtb_tag // write TB tag
-
+// map the next page too - in case the impure area crosses a page boundary
lda r4, (1<<va_s_off)(r1) // Generate address for next page
srl r4, va_s_off, r0 // Clean off byte-within-page offset
sll r0, pte_v_pfn, r0 // Shift to form PFN
mtpr r0, dtbPte // Load the PTE and set valid
mtpr r4, dtbTag // Write the PTE and tag into the DTB
- sll r31, 0, r31 // stall cycle 1 // orig
- sll r31, 0, r31 // stall cycle 2 // orig
- sll r31, 0, r31 // stall cycle 3 // orig
- nop // orig
+ sll r31, 0, r31 // stall cycle 1
+ sll r31, 0, r31 // stall cycle 2
+ sll r31, 0, r31 // stall cycle 3
+ nop
-//orig // add offset for saving fpr regs
+// add offset for saving fpr regs
//orig fix_impure_gpr r1
-
lda r1, 0x200(r1) // Point to center of CPU segment
// now save the regs - F0-F31
-
-//orig #define t 0
-//orig .repeat 32
-//orig store_reg \t , fpu=1
-//orig #define t t + 1
-//orig .endr
-
mf_fpcr f0 // original
SAVE_FPR(f0,CNS_Q_FPR+0x00,r1)
SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1)
SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1)
-//orig //switch impure offset from gpr to ipr---
+//switch impure offset from gpr to ipr---
//orig unfix_impure_gpr r1
//orig fix_impure_ipr r1
//orig store_reg1 fpcsr, f0, r1, fpcsr=1
- SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach// pb
+ SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach
lda r1, -0x200(r1) // Restore the impure base address
-//orig // and back to gpr ---
+// and back to gpr ---
//orig unfix_impure_ipr r1
//orig fix_impure_gpr r1
SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag
mb
-//orig // restore impure area base
+ // restore impure area base
//orig unfix_impure_gpr r1
lda r1, -0x200(r1) // Point to center of CPU segment
- mtpr r31, dtb_ia // clear the dtb //orig
- mtpr r31, itb_ia // clear the itb //orig
+ mtpr r31, dtb_ia // clear the dtb
+ mtpr r31, itb_ia // clear the itb
//orig pvc_jsr savsta, bsr=1, dest=1
ret r31, (r3) // and back we go
-#endif
-#if remove_restore_state == 0
-
// .sbttl "PAL_RESTORE_STATE"
-//+
+//
//
// Pal_restore_state
//
// All chip state restored, all SRs, FRs, PTs, IPRs
// *** except R1, R3, PT0, PT4, PT5 ***
//
-//-
+//
ALIGN_BLOCK
pal_restore_state:
//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so.
-//orig // map the console io area virtually
-//orig mtpr r31, dtb_ia // clear the dtb
-//orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r1, dtb_tag // write TB tag
-//orig
-
+// map the console io area virtually
mtpr r31, dtbIa // Clear all DTB entries
srl r1, va_s_off, r0 // Clean off byte-within-page offset
sll r0, pte_v_pfn, r0 // Shift to form PFN
mtpr r1, dtbTag // Write the PTE and tag into the DTB
-//orig // map the next page too, in case impure area crosses page boundary
-//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
-//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r4, dtb_tag // write TB tag - no virtual mbox instruction for 3 cycles
-
+// map the next page too, in case impure area crosses page boundary
lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page
srl r4, va_s_off, r0 // Clean off byte-within-page offset
sll r0, pte_v_pfn, r0 // Shift to form PFN
mtpr r0, dtbPte // Load the PTE and set valid
mtpr r4, dtbTag // Write the PTE and tag into the DTB
-//orig // save all floating regs
-//orig mfpr r0, icsr // get icsr
-//orig// assume ICSR_V_SDE gt <ICSR_V_FPE> // assertion checker
-//orig or r31, <<1@<ICSR_V_SDE-ICSR_V_FPE>> ! 1>, r2 // set SDE and FPE
-//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot
-//orig or r2, r0, r0 // set FEN on
-//orig mtpr r0, icsr // write to icsr, enabling FEN and SDE. 3 bubbles to floating instr.
-
+// save all floating regs
mfpr r0, icsr // Get current ICSR
bis zero, 1, r2 // Get a '1'
or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2
//orig
//orig unfix_impure_ipr r1
//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access
-//orig
-//orig // restore all floating regs
-//orig#define t 0
-//orig .repeat 32
-//orig restore_reg \t , fpu=1
-//orig#define t t + 1
-//orig .endr
-
lda r1, 200(r1) // Point to base of IPR area again
RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb
mt_fpcr f0 // original
lda r1, 0x200(r1) // point to center of CPU segment
+
+// restore all floating regs
RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1)
RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1)
RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1)
RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1)
RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1)
-//orig // switch impure pointer from gpr to ipr area --
+// switch impure pointer from gpr to ipr area --
//orig unfix_impure_gpr r1
//orig fix_impure_ipr r1
-//orig
-//orig // restore all pal regs
-//orig#define t 1
-//orig .repeat 23
-//orig restore_reg \t , pal=1
-//orig#define t t + 1
-//orig .endr
-
lda r1, -0x200(r1) // Restore base address of impure area.
lda r1, CNS_Q_IPR(r1) // Point to base of IPR area.
+
+// restore all pal regs
RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle
RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1)
RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1)
// restore all integer shadow regs
-//orig#define t 8
-//orig .repeat 7
-//orig restore_reg \t, shadow=1
-//orig#define t t + 1
-//orig .endr
-//orig restore_reg 25, shadow=1
-//orig restore_reg dc_mode, ipr=1 // no mbox instructions for 4 cycles
-
RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code
RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1)
RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1)
// Get out of shadow mode
//
- mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) //orig
- mfpr r31, pt0 // "" //orig
- mfpr r0, icsr // Get icsr //orig
-//orig ldah r2, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
- ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location //orig
- bic r0, r2, r2 // ICSR with SDE clear //orig
- mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles //orig
+ mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway)
+ mfpr r31, pt0 // ""
+ mfpr r0, icsr // Get icsr
+ ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location
+ bic r0, r2, r2 // ICSR with SDE clear
+ mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
+ mfpr r31, pt0 // SDE bubble cycle 1
+ mfpr r31, pt0 // SDE bubble cycle 2
+ mfpr r31, pt0 // SDE bubble cycle 3
+ nop
-//orig // switch impure pointer from ipr to gpr area --
+// switch impure pointer from ipr to gpr area --
//orig unfix_impure_ipr r1
//orig fix_impure_gpr r1
-//orig // restore all integer regs
-//orig#define t 4
-//orig .repeat 28
-//orig restore_reg \t
-//orig#define t t + 1
-//orig .endr
// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ...
lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area
lda r1, 0x200(r1) // Point to center of CPU segment
+ // restore all integer regs
RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1)
RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1)
RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1)
RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1)
lda r1, -0x200(r1) // Restore impure base address
- mfpr r31, pt0 // stall for ldqp above //orig
+ mfpr r31, pt0 // stall for ldq_p above //orig
mtpr r31, dtb_ia // clear the tb //orig
mtpr r31, itb_ia // clear the itb //orig
//orig pvc_jsr rststa, bsr=1, dest=1
ret r31, (r3) // back we go //orig
-#endif
-//+
+//
// pal_pal_bug_check -- code has found a bugcheck situation.
// Set things up and join common machine check flow.
//
// pt_misc<31:16> - scb vector
// r14 - base of Cbox IPRs in IO space
// MCES<mchk> is set
-//-
+//
ALIGN_BLOCK
.globl pal_pal_bug_check_from_int
br r31, sys_mchk_collect_iprs // Join common machine check flow
-// align_to_call_pal_section // Align to address of first call_pal entry point - 2000
-// .sbttl "HALT - PALcode for HALT instruction"
-//+
+// align_to_call_pal_section
+// Align to address of first call_pal entry point - 2000
+
+//
+// HALT - PALcode for HALT instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// Function:
// GO to console code
//
-//-
+//
.text 1
// . = 0x2000
CALL_PAL_PRIV(PAL_HALT_ENTRY)
call_pal_halt:
-#if rax_mode == 0
mfpr r31, pt0 // Pad exc_addr read
mfpr r31, pt0
lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt
br r31, sys_enter_console // enter the console
-#else // RAX mode
- mb
- mb
- mtpr r9, ev5__dtb_asn // no Dstream virtual ref for next 3 cycles.
- mtpr r9, ev5__itb_asn // E1. Update ITB ASN. No hw_rei for 5 cycles.
- mtpr r8, exc_addr // no HW_REI for 1 cycle.
- blbc r9, not_begin_case
- mtpr r31, ev5__dtb_ia // clear DTB. No Dstream virtual ref for 2 cycles.
- mtpr r31, ev5__itb_ia // clear ITB.
-
-not_begin_case:
- nop
- nop
-
- nop
- nop // pad mt itb_asn ->hw_rei_stall
-
- hw_rei_stall
-#endif
-
-// .sbttl "CFLUSH- PALcode for CFLUSH instruction"
-
-//+
+//
+// CFLUSH - PALcode for CFLUSH instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// Flush all Dstream caches of 1 entire page
// The CFLUSH routine is in the system specific module.
//
-//-
+//
CALL_PAL_PRIV(PAL_CFLUSH_ENTRY)
Call_Pal_Cflush:
br r31, sys_cflush
-// .sbttl "DRAINA - PALcode for DRAINA instruction"
-//+
+//
+// DRAINA - PALcode for DRAINA instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// complete without incurring aborts. For the EV5 implementation, this
// means waiting until all pending DREADS are returned.
//
-//-
+//
CALL_PAL_PRIV(PAL_DRAINA_ENTRY)
Call_Pal_Draina:
DRAINA_LOOP_TOO_LONG:
br r31, call_pal_halt
-// .sbttl "CALL_PAL OPCDECs"
+// CALL_PAL OPCDECs
CALL_PAL_PRIV(0x0003)
CallPal_OpcDec03:
CallPal_OpcDec08:
br r31, osfpal_calpal_opcdec
-// .sbttl "CSERVE- PALcode for CSERVE instruction"
-//+
+//
+// CSERVE - PALcode for CSERVE instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// arguments in r16....
// The CSERVE routine is in the system specific module.
//
-//-
+//
CALL_PAL_PRIV(PAL_CSERVE_ENTRY)
Call_Pal_Cserve:
br r31, sys_cserve
-// .sbttl "swppal - PALcode for swppal instruction"
-
-//+
+//
+// swppal - PALcode for swppal instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// Swap control to another PAL.
-//-
+//
CALL_PAL_PRIV(PAL_SWPPAL_ENTRY)
Call_Pal_Swppal:
//orig halt // don't know how to get the address here - kludge ok, load pal at 0
.long 0 // ?? hack upon hack...pb
-CALL_PAL_SWPPAL_10_: ldlp r3, 0(r2) // fetch target addr
+CALL_PAL_SWPPAL_10_: ldl_p r3, 0(r2) // fetch target addr
// ble r3, swppal_fail ; if OSF not linked in say not loaded.
mfpr r2, pal_base // fetch pal base
CallPal_OpcDec0C:
br r31, osfpal_calpal_opcdec
-// .sbttl "wripir- PALcode for wripir instruction"
-//+
+//
+// wripir - PALcode for wripir instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// Exit:
// interprocessor interrupt is recorded on the target processor
// and is initiated when the proper enabling conditions are present.
-//-
+//
CALL_PAL_PRIV(PAL_WRIPIR_ENTRY)
Call_Pal_Wrpir:
CallPal_OpcDec0F:
br r31, osfpal_calpal_opcdec
-// .sbttl "rdmces- PALcode for rdmces instruction"
-
-//+
+//
+// rdmces - PALcode for rdmces instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// R0 <- ZEXT(MCES)
-//-
+//
CALL_PAL_PRIV(PAL_RDMCES_ENTRY)
Call_Pal_Rdmces:
hw_rei
-// .sbttl "wrmces- PALcode for wrmces instruction"
-
-//+
+//
+// wrmces - PALcode for wrmces instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// MCES<3> <- R16<3> (DPC)
// MCES<4> <- R16<4> (DSC)
//
-//-
+//
CALL_PAL_PRIV(PAL_WRMCES_ENTRY)
Call_Pal_Wrmces:
or r1, r17, r1 // Update DPC and DSC
mtpr r1, pt_mces // Write MCES back
-#if rawhide_system == 0
nop // Pad to fix PT write->read restriction
-#else
- blbs r16, RAWHIDE_clear_mchk_lock // Clear logout from lock
-#endif
nop
hw_rei
-// .sbttl "CALL_PAL OPCDECs"
+// CALL_PAL OPCDECs
CALL_PAL_PRIV(0x0012)
CallPal_OpcDec12:
CallPal_OpcDec2A:
br r31, osfpal_calpal_opcdec
-// .sbttl "wrfen - PALcode for wrfen instruction"
-
-//+
+//
+// wrfen - PALcode for wrfen instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// Function:
// a0<0> -> ICSR<FPE>
// Store new FEN in PCB
-// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) are UNPREDICTABLE
+// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16)
+// are UNPREDICTABLE
//
// Issue: What about pending FP loads when FEN goes from on->off????
-//-
+//
CALL_PAL_PRIV(PAL_WRFEN_ENTRY)
Call_Pal_Wrfen:
mfpr r12, pt_pcbb // Get PCBB - E1
mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI
- stlp r16, osfpcb_q_fen(r12) // Store FEN in PCB.
+ stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB.
mfpr r31, pt0 // Pad ICSR<FPE> write.
mfpr r31, pt0
CallPal_OpcDec2C:
br r31, osfpal_calpal_opcdec
-// .sbttl "wrvptpr - PALcode for wrvptpr instruction"
-//+
+//
+// wrvptpr - PALcode for wrvptpr instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// vptptr <- a0 (r16)
-//-
+//
CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY)
Call_Pal_Wrvptptr:
CallPal_OpcDec2F:
br r31, osfpal_calpal_opcdec
-// .sbttl "swpctx- PALcode for swpctx instruction"
-//+
+//
+// swpctx - PALcode for swpctx instruction
//
// Entry:
// hardware dispatch via callPal instruction
// old pcbb returned in R0
//
// Note: need to add perf monitor stuff
-//-
+//
CALL_PAL_PRIV(PAL_SWPCTX_ENTRY)
Call_Pal_Swpctx:
rpcc r13 // get cyccounter
mfpr r0, pt_pcbb // get pcbb
- ldqp r22, osfpcb_q_fen(r16) // get new fen/pme
- ldqp r23, osfpcb_l_cc(r16) // get new asn
+ ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme
+ ldq_p r23, osfpcb_l_cc(r16) // get new asn
srl r13, 32, r25 // move offset
mfpr r24, pt_usp // get usp
- stqp r30, osfpcb_q_ksp(r0) // store old ksp
-// pvc_violate 379 // stqp can't trap except replay. only problem if mf same ipr in same shadow.
+ stq_p r30, osfpcb_q_ksp(r0) // store old ksp
+// pvc_violate 379 // stq_p can't trap except replay. only problem if mf same ipr in same shadow.
mtpr r16, pt_pcbb // set new pcbb
- stqp r24, osfpcb_q_usp(r0) // store usp
+ stq_p r24, osfpcb_q_usp(r0) // store usp
addl r13, r25, r25 // merge for new time
- stlp r25, osfpcb_l_cc(r0) // save time
+ stl_p r25, osfpcb_l_cc(r0) // save time
ldah r24, (1<<(icsr_v_fpe-16))(r31)
and r22, 1, r12 // isolate fen
mfpr r25, icsr // get current icsr
- ev5_pass2 lda r24, (1<<icsr_v_pmp)(r24)
+ lda r24, (1<<icsr_v_pmp)(r24)
br r31, swpctx_cont
-// .sbttl "wrval - PALcode for wrval instruction"
-//+
+//
+// wrval - PALcode for wrval instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// sysvalue <- a0 (r16)
-//-
+//
CALL_PAL_PRIV(PAL_WRVAL_ENTRY)
Call_Pal_Wrval:
nop
hw_rei
-
-// .sbttl "rdval - PALcode for rdval instruction"
-
-//+
+//
+// rdval - PALcode for rdval instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// v0 (r0) <- sysvalue
-//-
+//
CALL_PAL_PRIV(PAL_RDVAL_ENTRY)
Call_Pal_Rdval:
nop
hw_rei
-// .sbttl "tbi - PALcode for tbi instruction"
-//+
+//
+// tbi - PALcode for tbi instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// TB invalidate
// r16/a0 = TBI type
// r17/a1 = Va for TBISx instructions
-//-
+//
CALL_PAL_PRIV(PAL_TBI_ENTRY)
Call_Pal_Tbi:
hw_rei
nop
-// .sbttl "wrent - PALcode for wrent instruction"
-//+
+//
+// wrent - PALcode for wrent instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// r17/a1 = Entry Number 0..5
//
// r22, r23 trashed
-//-
+//
CALL_PAL_PRIV(PAL_WRENT_ENTRY)
Call_Pal_Wrent:
CALL_PAL_wrent_30_:
hw_rei // out of range, just return
-// .sbttl "swpipl - PALcode for swpipl instruction"
-//+
+//
+// swpipl - PALcode for swpipl instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// PS<IPL> <- a0<2:0> (r16)
//
// t8 (r22) is scratch
-//-
+//
CALL_PAL_PRIV(PAL_SWPIPL_ENTRY)
Call_Pal_Swpipl:
hw_rei // back
-// .sbttl "rdps - PALcode for rdps instruction"
-//+
+//
+// rdps - PALcode for rdps instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// v0 (r0) <- ps
-//-
+//
CALL_PAL_PRIV(PAL_RDPS_ENTRY)
Call_Pal_Rdps:
nop // Must be 2 cycles long
hw_rei
-// .sbttl "wrkgp - PALcode for wrkgp instruction"
-//+
+//
+// wrkgp - PALcode for wrkgp instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// kgp <- a0 (r16)
-//-
+//
CALL_PAL_PRIV(PAL_WRKGP_ENTRY)
Call_Pal_Wrkgp:
nop
hw_rei
-// .sbttl "wrusp - PALcode for wrusp instruction"
-//+
+//
+// wrusp - PALcode for wrusp instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// usp <- a0 (r16)
-//-
+//
CALL_PAL_PRIV(PAL_WRUSP_ENTRY)
Call_Pal_Wrusp:
nop
hw_rei
-// .sbttl "wrperfmon - PALcode for wrperfmon instruction"
-//+
+//
+// wrperfmon - PALcode for wrperfmon instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
CALL_PAL_PRIV(0x0039)
// unsupported in Hudson code .. pboyle Nov/95
CALL_PAL_Wrperfmon:
-#if perfmon_debug == 0
// "real" performance monitoring code
cmpeq r16, 1, r0 // check for enable
bne r0, perfmon_en // br if requested to enable
beq r16, perfmon_dis // br if requested to disable (r16=0)
br r31, perfmon_unknown // br if unknown request
-#else
-
- br r31, pal_perfmon_debug
-#endif
-// .sbttl "rdusp - PALcode for rdusp instruction"
-//+
+//
+// rdusp - PALcode for rdusp instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// v0 (r0) <- usp
-//-
+//
CALL_PAL_PRIV(PAL_RDUSP_ENTRY)
Call_Pal_Rdusp:
CallPal_OpcDec3B:
br r31, osfpal_calpal_opcdec
-// .sbttl "whami - PALcode for whami instruction"
-//+
+//
+// whami - PALcode for whami instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
//
// Function:
// v0 (r0) <- whami
-//-
+//
CALL_PAL_PRIV(PAL_WHAMI_ENTRY)
Call_Pal_Whami:
nop
extbl r0, 1, r0 // Isolate just whami bits
hw_rei
-// .sbttl "retsys - PALcode for retsys instruction"
+//
+// retsys - PALcode for retsys instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// mode switched from kern to user.
// stacks swapped, ugp, upc restored.
// r23, r25 junked
-//-
+//
CALL_PAL_PRIV(PAL_RETSYS_ENTRY)
Call_Pal_Retsys:
CallPal_OpcDec3E:
br r31, osfpal_calpal_opcdec
-// .sbttl "rti - PALcode for rti instruction"
-//+
+//
+// rti - PALcode for rti instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// 24(sp) -> r16 (a0)
// 32(sp) -> r17 (a1)
// 40(sp) -> r18 (a3)
-//-
+//
CALL_PAL_PRIV(PAL_RTI_ENTRY)
-#ifdef SIMOS
/* called once by platform_tlaser */
.globl Call_Pal_Rti
-#endif
Call_Pal_Rti:
lda r25, osfsf_c_size(sp) // get updated sp
bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr
br r31, rti_to_user // out of call_pal space
-// .sbttl "Start the Unprivileged CALL_PAL Entry Points"
-// .sbttl "bpt- PALcode for bpt instruction"
-//+
+///////////////////////////////////////////////////
+// Start the Unprivileged CALL_PAL Entry Points
+///////////////////////////////////////////////////
+
+//
+// bpt - PALcode for bpt instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// a2 <- unpred
// vector via entIF
//
-//-
+//
//
.text 1
// . = 0x3000
br r31, bpt_bchk_common // out of call_pal space
-// .sbttl "bugchk- PALcode for bugchk instruction"
-//+
+//
+// bugchk - PALcode for bugchk instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// a2 <- unpred
// vector via entIF
//
-//-
+//
//
CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY)
Call_Pal_Bugchk:
CallPal_OpcDec82:
br r31, osfpal_calpal_opcdec
-// .sbttl "callsys - PALcode for callsys instruction"
-//+
+//
+// callsys - PALcode for callsys instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// gp = kgp
// t8 - t10 (r22-r24) trashed
//
-//-
+//
//
CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY)
Call_Pal_Callsys:
beq r24, sys_from_kern // sysCall from kern is not allowed
mfpr r12, pt_entsys // get address of callSys routine
-//+
+//
// from here on we know we are in user going to Kern
-//-
+//
mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
CallPal_OpcDec85:
br r31, osfpal_calpal_opcdec
-// .sbttl "imb - PALcode for imb instruction"
-//+
+//
+// imb - PALcode for imb instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// Function:
// Flush the writebuffer and flush the Icache
//
-//-
+//
//
CALL_PAL_UNPRIV(PAL_IMB_ENTRY)
Call_Pal_Imb:
br r31, pal_ic_flush // Flush Icache
-// .sbttl "CALL_PAL OPCDECs"
+// CALL_PAL OPCDECs
CALL_PAL_UNPRIV(0x0087)
CallPal_OpcDec87:
CallPal_OpcDec9D:
br r31, osfpal_calpal_opcdec
-// .sbttl "rdunique - PALcode for rdunique instruction"
-//+
+//
+// rdunique - PALcode for rdunique instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// Function:
// v0 (r0) <- unique
//
-//-
+//
//
CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY)
CALL_PALrdunique_:
mfpr r0, pt_pcbb // get pcb pointer
- ldqp r0, osfpcb_q_unique(r0) // get new value
+ ldq_p r0, osfpcb_q_unique(r0) // get new value
hw_rei
-// .sbttl "wrunique - PALcode for wrunique instruction"
-//+
+//
+// wrunique - PALcode for wrunique instruction
//
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// Function:
// unique <- a0 (r16)
//
-//-
+//
//
CALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY)
CALL_PAL_Wrunique:
nop
mfpr r12, pt_pcbb // get pcb pointer
- stqp r16, osfpcb_q_unique(r12)// get new value
+ stq_p r16, osfpcb_q_unique(r12)// get new value
nop // Pad palshadow write
hw_rei // back
-// .sbttl "CALL_PAL OPCDECs"
+// CALL_PAL OPCDECs
CALL_PAL_UNPRIV(0x00A0)
CallPal_OpcDecA0:
br r31, osfpal_calpal_opcdec
-// .sbttl "gentrap - PALcode for gentrap instruction"
-//+
+//
+// gentrap - PALcode for gentrap instruction
+//
// CALL_PAL_gentrap:
// Entry:
// Vectored into via hardware PALcode instruction dispatch.
// a2 <- unpred
// vector via entIF
//
-//-
+//
CALL_PAL_UNPRIV(0x00AA)
// unsupported in Hudson code .. pboyle Nov/95
br r31, bpt_bchk_common // out of call_pal space
-// .sbttl "CALL_PAL OPCDECs"
+// CALL_PAL OPCDECs
CALL_PAL_UNPRIV(0x00AB)
CallPal_OpcDecAB:
. = 0x4000
-// .sbttl "Continuation of MTPR_PERFMON"
+// Continuation of MTPR_PERFMON
ALIGN_BLOCK
-#if perfmon_debug == 0
// "real" performance monitoring code
// mux ctl
perfmon_muxctl:
bic r16, r8, r16 // isolate old mux select bits
or r16, r25, r25 // create new bc_ctl
mb // clear out cbox for future ipr write
- stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
+ stq_p r25, ev5__bc_ctl(r14) // store to cbox ipr
mb // clear out cbox for future ipr write
//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
lda r25, CNS_Q_IPR(r25)
RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25);
- ldqp r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
+ ldq_p r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
mfpr r14, ev5__pmctr // read ibox pmctr ipr
srl r16, osfpcb_v_pme, r16 // get pme bit
mfpr r13, icsr
and r16, 1, r16 // isolate pme bit
// this code only needed in pass2 and later
-//orig sget_addr r12, 1<<icsr_v_pmp, r31
lda r12, 1<<icsr_v_pmp(r31) // pb
bic r13, r12, r13 // clear pmp bit
sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position
or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear
- ev5_pass2 mtpr r13, icsr // update icsr
+ mtpr r13, icsr // update icsr
-#if ev5_p1 != 0
- lda r12, 1(r31)
- cmovlbc r25, r12, r16 // r16<0> set if either pme=1 or sprocess=0 (sprocess in bit 0 of r25)
-#else
bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable)
-#endif
sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions
bis r14, r31, r13 // copy pmctr
lda r12, CNS_Q_IPR(r12)
RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12);
-//orig get_addr r8, (1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk), r31 // build mode mask for pmctr register
+ // build mode mask for pmctr register
LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk)))
mfpr r0, ev5__pmctr
and r17, r8, r25 // isolate pmctr mode bits
or r0, r25, r25 // or in new mode bits
mtpr r25, ev5__pmctr
-//;the following code will only be used in pass2, but should not hurt anything if run in pass1.
+ // the following code will only be used in pass2, but should
+ // not hurt anything if run in pass1.
mfpr r8, icsr
lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0
bic r8, r25, r8 // clear old pma bit
cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1
or r8, r25, r8
- ev5_pass2 mtpr r8, icsr // 4 bubbles to hw_rei
+ mtpr r8, icsr // 4 bubbles to hw_rei
mfpr r31, pt0 // pad icsr write
mfpr r31, pt0 // pad icsr write
-//;the following code not needed for pass2 and later, but should work anyway.
+ // the following code not needed for pass2 and later, but
+ // should work anyway.
bis r14, 1, r14 // set for select processes
blbs r17, perfmon_sp // branch if select processes
bic r14, 1, r14 // all processes
lda r8, 0x3F(r31)
//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field
-// I guess this should be a shift of 4 bits from the above control register structure .. pb
+// I guess this should be a shift of 4 bits from the above control register structure
#define pmctr_ctl_v_frq2_SHIFT 4
sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field
lda r8, 0x3FFF(r31) // ctr2<13:0> mask
sll r8, pmctr_v_ctr2, r8
-//orig get_addr r9, 0xFFFFFFFF, r31, verify=0 // ctr2<15:0>,ctr1<15:0> mask
- LDLI(r9, (0xFFFFFFFF))
+ LDLI(r9, (0xFFFFFFFF)) // ctr2<15:0>,ctr1<15:0> mask
sll r9, pmctr_v_ctr1, r9
or r8, r9, r8 // or ctr2, ctr1, ctr0 mask
bic r14, r8, r14 // clear ctr fields
or r31, r31, r0 // set fail
hw_rei // back to user
-#else
-
-// end of "real code", start of debug code
-
-//+
-// Debug environment:
-// (in pass2, always set icsr<pma> to ensure master counter enable is on)
-// R16 = 0 Write to on-chip performance monitor ipr
-// r17 = on-chip ipr
-// r0 = return value of read of on-chip performance monitor ipr
-// R16 = 1 Setup Cbox mux selects
-// r17 = Cbox mux selects in same position as in bc_ctl ipr.
-// r0 = return value of read of on-chip performance monitor ipr
-//
-//-
-pal_perfmon_debug:
- mfpr r8, icsr
- lda r9, 1<<icsr_v_pma(r31)
- bis r8, r9, r8
- mtpr r8, icsr
-
- mfpr r0, ev5__pmctr // read old value
- bne r16, cbox_mux_sel
-
- mtpr r17, ev5__pmctr // update pmctr ipr
- br r31, end_pm
-
-cbox_mux_sel:
- // ok, now tackle cbox mux selects
- ldah r14, 0xfff0(r31)
- zap r14, 0xE0, r14 // Get Cbox IPR base
-//orig get_bc_ctl_shadow r16 // bc_ctl returned
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
-
- lda r8, 0x3F(r31) // build mux select mask
- sll r8, BC_CTL_V_PM_MUX_SEL, r8
-
- and r17, r8, r25 // isolate bc_ctl mux select bits
- bic r16, r8, r16 // isolate old mux select bits
- or r16, r25, r25 // create new bc_ctl
- mb // clear out cbox for future ipr write
- stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
- mb // clear out cbox for future ipr write
-//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
-
-end_pm: hw_rei
-
-#endif
-
-
-//;The following code is a workaround for a cpu bug where Istream prefetches to
-//;super-page address space in user mode may escape off-chip.
-#if spe_fix != 0
-
- ALIGN_BLOCK
-hw_rei_update_spe:
- mfpr r12, pt_misc // get previous mode
- srl r11, osfps_v_mode, r10 // isolate current mode bit
- and r10, 1, r10
- extbl r12, 7, r8 // get previous mode field
- and r8, 1, r8 // isolate previous mode bit
- cmpeq r10, r8, r8 // compare previous and current modes
- beq r8, hw_rei_update_spe_5_
- hw_rei // if same, just return
-
-hw_rei_update_spe_5_:
-
-#if fill_err_hack != 0
-
- fill_error_hack
-#endif
-
- mfpr r8, icsr // get current icsr value
- ldah r9, (2<<(icsr_v_spe-16))(r31) // get spe bit mask
- bic r8, r9, r8 // disable spe
- xor r10, 1, r9 // flip mode for new spe bit
- sll r9, icsr_v_spe+1, r9 // shift into position
- bis r8, r9, r8 // enable/disable spe
- lda r9, 1(r31) // now update our flag
- sll r9, pt_misc_v_cm, r9 // previous mode saved bit mask
- bic r12, r9, r12 // clear saved previous mode
- sll r10, pt_misc_v_cm, r9 // current mode saved bit mask
- bis r12, r9, r12 // set saved current mode
- mtpr r12, pt_misc // update pt_misc
- mtpr r8, icsr // update icsr
-
-#if osf_chm_fix != 0
-
-
- blbc r10, hw_rei_update_spe_10_ // branch if not user mode
-
- mb // ensure no outstanding fills
- lda r12, 1<<dc_mode_v_dc_ena(r31) // User mode
- mtpr r12, dc_mode // Turn on dcache
- mtpr r31, dc_flush // and flush it
- br r31, pal_ic_flush
-
-hw_rei_update_spe_10_: mfpr r9, pt_pcbb // Kernel mode
- ldqp r9, osfpcb_q_Fen(r9) // get FEN
- blbc r9, pal_ic_flush // return if FP disabled
- mb // ensure no outstanding fills
- mtpr r31, dc_mode // turn off dcache
-#endif
-
-
- br r31, pal_ic_flush // Pal restriction - must flush Icache if changing ICSR<SPE>
-#endif
+//////////////////////////////////////////////////////////
+// Copy code
+//////////////////////////////////////////////////////////
copypal_impl:
mov r16, r0
- ble r18, finished #if len <=0 we are finished
+#ifdef CACHE_COPY
+#ifndef CACHE_COPY_UNALIGNED
+ and r16, 63, r8
+ and r17, 63, r9
+ bis r8, r9, r8
+ bne r8, cache_copy_done
+#endif
+ bic r18, 63, r8
+ and r18, 63, r18
+ beq r8, cache_copy_done
+cache_loop:
+ ldf f17, 0(r16)
+ stf f17, 0(r16)
+ addq r17, 64, r17
+ addq r16, 64, r16
+ subq r8, 64, r8
+ bne r8, cache_loop
+cache_copy_done:
+#endif
+ ble r18, finished // if len <=0 we are finished
ldq_u r8, 0(r17)
xor r17, r16, r9
and r9, 7, r9
+++ /dev/null
-/*
- * Copyright (c) 2003, 2004
- * The Regents of The University of Michigan
- * All Rights Reserved
- *
- * This code is part of the M5 simulator, developed by Nathan Binkert,
- * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
- * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
- * Schultz.
- *
- * Permission is granted to use, copy, create derivative works and
- * redistribute this software and such derivative works for any
- * purpose, so long as the copyright notice above, this grant of
- * permission, and the disclaimer below appear in all copies made; and
- * so long as the name of The University of Michigan is not used in
- * any advertising or publicity pertaining to the use or distribution
- * of this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
- * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
- * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
- * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
- * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
- * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
- * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
- * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGES.
- */
-/*
-Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl
-// since we don't have a mechanism to expand the data structures.... pb Nov/95
-
-// build_fixed_image: not sure what means
-// real_mm to be replaced during rewrite
-// remove_save_state remove_restore_state can be remooved to save space ??
-
-
-#include "ev5_defs.h"
-#include "ev5_impure.h"
-#include "ev5_alpha_defs.h"
-#include "ev5_paldef.h"
-#include "ev5_osfalpha_defs.h"
-#include "fromHudsonMacros.h"
-#include "fromHudsonOsf.h"
-#include "dc21164FromGasSources.h"
-
-#ifdef SIMOS
-#define DEBUGSTORE(c) nop
-#else
-#define DEBUGSTORE(c) \
- lda r13, c(zero) ; \
- bsr r25, debugstore
-#endif
-
-#define DEBUG_EXC_ADDR()\
- bsr r25, put_exc_addr; \
- DEBUGSTORE(13) ; \
- DEBUGSTORE(10)
-
-#define egore 0
-#define acore 0
-#define beh_model 0
-#define ev5_p2 1
-#define ev5_p1 0
-#define ldvpte_bug_fix 1
-#define osf_chm_fix 0
-
-// Do we want to do this?? pb
-#define spe_fix 0
-// Do we want to do this?? pb
-#define build_fixed_image 0
-
-#define ev5_pass2
-#define enable_p4_fixups 0
-#define osf_svmin 1
-#define enable_physical_console 0
-#define fill_err_hack 0
-#define icflush_on_tbix 0
-#define max_cpuid 1
-#define perfmon_debug 0
-#define rawhide_system 0
-#define rax_mode 0
-
-
-// This is the fix for the user-mode super page references causing the machine to crash.
-#if (spe_fix == 1) && (build_fixed_image==1)
-#define hw_rei_spe br r31, hw_rei_update_spe
-#else
-#define hw_rei_spe hw_rei
-#endif
-
-
-// redefine a few of the distribution-code names to match the Hudson gas names.
-// opcodes
-#define ldqp ldq_p
-#define stqp stq_p
-#define ldlp ldl_p
-#define stlp stl_p
-
-#define r0 $0
-#define r1 $1
-#define r2 $2
-#define r3 $3
-#define r4 $4
-#define r5 $5
-#define r6 $6
-#define r7 $7
-#define r8 $8
-#define r9 $9
-#define r10 $10
-#define r11 $11
-#define r12 $12
-#define r13 $13
-#define r14 $14
-#define r15 $15
-#define r16 $16
-#define r17 $17
-#define r18 $18
-#define r19 $19
-#define r20 $20
-#define r21 $21
-#define r22 $22
-#define r23 $23
-#define r24 $24
-#define r25 $25
-#define r26 $26
-#define r27 $27
-#define r28 $28
-#define r29 $29
-#define r30 $30
-#define r31 $31
-
-// .title "EV5 OSF PAL"
-// .ident "V1.18"
-//
-//****************************************************************************
-//* *
-//* Copyright (c) 1992, 1993, 1994, 1995 *
-//* by DIGITAL Equipment Corporation, Maynard, Mass. *
-//* *
-//* This software is furnished under a license and may be used and copied *
-//* only in accordance with the terms of such license and with the *
-//* inclusion of the above copyright notice. This software or any other *
-//* copies thereof may not be provided or otherwise made available to any *
-//* other person. No title to and ownership of the software is hereby *
-//* transferred. *
-//* *
-//* The information in this software is subject to change without notice *
-//* and should not be construed as a commitment by DIGITAL Equipment *
-//* Corporation. *
-//* *
-//* DIGITAL assumes no responsibility for the use or reliability of its *
-//* software on equipment which is not supplied by DIGITAL. *
-//* *
-//****************************************************************************
-
-// .sbttl "Edit History"
-//+
-// Who Rev When What
-// ------------ --- ----------- --------------------------------
-// DB 0.0 03-Nov-1992 Start
-// DB 0.1 28-Dec-1992 add swpctx
-// DB 0.2 05-Jan-1993 Bug: PVC found mtpr dtb_CM -> virt ref bug
-// DB 0.3 11-Jan-1993 rearrange trap entry points
-// DB 0.4 01-Feb-1993 add tbi
-// DB 0.5 04-Feb-1993 real MM, kludge reset flow, kludge swppal
-// DB 0.6 09-Feb-1993 Bug: several stack pushers used r16 for pc (should be r14)
-// DB 0.7 10-Feb-1993 Bug: pushed wrong PC (+8) on CALL_PAL OPCDEC
-// Bug: typo on register number for store in wrunique
-// Bug: rti to kern uses r16 as scratch
-// Bug: callsys saving wrong value in pt_usp
-// DB 0.8 16-Feb-1993 PVC: fix possible pt write->read bug in wrkgp, wrusp
-// DB 0.9 18-Feb-1993 Bug: invalid_dpte_handler shifted pte twice
-// Bug: rti stl_c could corrupt the stack
-// Bug: unaligned returning wrong value in r17 (or should be and)
-// DB 0.10 19-Feb-1993 Add draina, rd/wrmces, cflush, cserve, interrupt
-// DB 0.11 23-Feb-1993 Turn caches on in reset flow
-// DB 0.12 10-Mar-1993 Bug: wrong value for icsr for FEN in kern mode flow
-// DB 0.13 15-Mar-1993 Bug: wrong value pushed for PC in invalid_dpte_handler if stack push tbmisses
-// DB 0.14 23-Mar-1993 Add impure pointer paltemp, reshuffle some other paltemps to match VMS
-// DB 0.15 15-Apr-1993 Combine paltemps for WHAMI and MCES
-// DB 0.16 12-May-1993 Update reset
-// New restriction: no mfpr exc_addr in cycle 1 of call_pal flows
-// Bug: in wrmces, not clearing DPC, DSC
-// Update swppal
-// Add pal bugchecks, pal_save_state, pal_restore_state
-// DB 0.17 24-May-1993 Add dfault_in_pal flow; fixup stack builder to have common state for pc/ps.
-// New restriction: No hw_rei_stall in 0,1,2 after mtpr itb_asn
-// DB 0.18 26-May-1993 PVC fixes
-// JM 0.19 01-jul-1993 Bug: OSFPAL_CALPAL_OPCDEC, TRAP_OPCDEC -- move mt exc_addr after stores
-// JM 0.20 07-jul-1993 Update cns_ and mchk_ names for impure.mar conversion to .sdl
-// Bug: exc_addr was being loaded before stores that could dtb_miss in the following
-// routines: TRAP_FEN,FEN_TO_OPCDEC,CALL_PAL_CALLSYS,RTI_TO_KERN
-// JM 0.21 26-jul-1993 Bug: move exc_addr load after ALL stores in the following routines:
-// TRAP_IACCVIO::,TRAP_OPCDEC::,TRAP_ARITH::,TRAP_FEN::
-// dfault_trap_cont:,fen_to_opcdec:,invalid_dpte_handler:
-// osfpal_calpal_opcdec:,CALL_PAL_callsys::,TRAP_UNALIGN::
-// Bugs from PVC: trap_unalign - mt pt0 ->mf pt0 within 2 cycles
-// JM 0.22 28-jul-1993 Add WRIPIR instruction
-// JM 0.23 05-aug-1993 Bump version number for release
-// JM 0.24 11-aug-1993 Bug: call_pal_swpipl - palshadow write -> hw_rei violation
-// JM 0.25 09-sep-1993 Disable certain "hidden" pvc checks in call_pals;
-// New restriction: No hw_rei_stall in 0,1,2,3,4 after mtpr itb_asn - affects HALT(raxmode),
-// and SWPCTX
-// JM 0.26 07-oct-1993 Re-implement pal_version
-// JM 0.27 12-oct-1993 One more time: change pal_version format to conform to SRM
-// JM 0.28 14-oct-1993 Change ic_flush routine to pal_ic_flush
-// JM 0.29 19-oct-1993 BUG(?): dfault_in_pal: use exc_addr to check for dtbmiss,itbmiss check instead
-// of mm_stat<opcode>. mm_stat contains original opcode, not hw_ld.
-// JM 0.30 28-oct-1993 BUG: PVC violation - mf exc_addr in first cycles of call_pal in rti,retsys
-// JM 0.31 15-nov-1993 BUG: WRFEN trashing r0
-// JM 0.32 21-nov-1993 BUG: dtb_ldq,itb_ldq (used in dfault_in_pal) not defined when real_mm=0
-// JM 0.33 24-nov-1993 save/restore_state -
-// BUG: use ivptbr to restore mvptbr
-// BUG: adjust hw_ld/st base/offsets to accomodate 10-bit offset limit
-// CHANGE: Load 2 pages into dtb to accomodate compressed logout area/multiprocessors
-// JM 0.34 20-dec-1993 BUG: set r11<mode> to kernel for ksnv halt case
-// BUG: generate ksnv halt when tb miss on kernel stack accesses
-// save exc_addr in r14 for invalid_dpte stack builder
-// JM 0.35 30-dec-1993 BUG: PVC violation in trap_arith - mt exc_sum in shadow of store with mf exc_mask in
-// the same shadow
-// JM 0.36 6-jan-1994 BUG: fen_to_opcdec - savePC should be PC+4, need to save old PS, update new PS
-// New palcode restiction: mt icsr<fpe,hwe> --> 3 bubbles to hw_rei --affects wrfen
-// JM 0.37 25-jan-1994 BUG: PVC violations in restore_state - mt dc_mode/maf_mode ->mbox instructions
-// Hide impure area manipulations in macros
-// BUG: PVC violation in save and restore state-- move mt icsr out of shadow of ld/st
-// Add some pvc_violate statements
-// JM 0.38 1-feb-1994 Changes to save_state: save pt1; don't save r31,f31; update comments to reflect reality;
-// Changes to restore_state: restore pt1, icsr; don't restore r31,f31; update comments
-// Add code to ensure fen bit set in icsr before ldt
-// conditionally compile rax_more_reset out.
-// move ldqp,stqp macro definitions to ev5_pal_macros.mar and add .mcall's for them here
-// move rax reset stuff to ev5_osf_system_pal.m64
-// JM 0.39 7-feb-1994 Move impure pointer to pal scratch space. Use former pt_impure for bc_ctl shadow
-// and performance monitoring bits
-// Change to save_state routine to save more iprs.
-// JM 0.40 19-feb-1994 Change algorithm in save/restore_state routines; add f31,r31 back in
-// JM 0.41 21-feb-1994 Add flags to compile out save/restore state (not needed in some systems)
-// remove_save_state,remove_restore_state;fix new pvc violation in save_state
-// JM 0.42 22-feb-1994 BUG: save_state overwriting r3
-// JM 0.43 24-feb-1994 BUG: save_state saving wrong icsr
-// JM 0.44 28-feb-1994 Remove ic_flush from wr_tbix instructions
-// JM 0.45 15-mar-1994 BUG: call_pal_tbi trashes a0 prior to range check (instruction order problem)
-// New pal restriction in pal_restore_state: icsr<fpe>->floating instr = 3 bubbles
-// Add exc_sum and exc_mask to pal_save_state (not restore)
-// JM 0.46 22-apr-1994 Move impure pointer back into paltemp; Move bc_ctl shadow and pmctr_ctl into impure
-// area.
-// Add performance counter support to swpctx and wrperfmon
-// JM 0.47 9-may-1994 Bump version # (for ev5_osf_system_pal.m64 sys_perfmon fix)
-// JM 0.48 13-jun-1994 BUG: trap_interrupt --> put new ev5 ipl at 30 for all osfipl6 interrupts
-// JM 0.49 8-jul-1994 BUG: In the unlikely (impossible?) event that the branch to pal_pal_bug_check is
-// taken in the interrupt flow, stack is pushed twice.
-// SWPPAL - update to support ECO 59 to allow 0 as a valid address
-// Add itb flush to save/restore state routines
-// Change hw_rei to hw_rei_stall in ic_flush routine. Shouldn't be necessary, but
-// conforms to itbia restriction.
-// Added enable_physical_console flag (for enter/exit console routines only)
-// JM 0.50 29-jul-1994 Add code to dfault & invalid_dpte_handler to ignore exceptions on a
-// load to r31/f31. changed dfault_fetch_err to dfault_fetch_ldr31_err and
-// nmiss_fetch_err to nmiss_fetch_ldr31_err.
-// JM 1.00 1-aug-1994 Add pass2 support (swpctx)
-// JM 1.01 2-aug-1994 swppal now passes bc_ctl/bc_config in r1/r2
-// JM 1.02 15-sep-1994 BUG: swpctx missing shift of pme bit to correct position in icsr (pass2)
-// Moved perfmon code here from system file.
-// BUG: pal_perfmon - enable function not saving correct enables when pme not set (pass1)
-// JM 1.03 3-oct-1994 Added (pass2 only) code to wrperfmon enable function to look at pme bit.
-// JM 1.04 14-oct-1994 BUG: trap_interrupt - ISR read (and saved) before INTID -- INTID can change
-// after ISR read, but we won't catch the ISR update. reverse order
-// JM 1.05 17-nov-1994 Add code to dismiss UNALIGN trap if LD r31/F31
-// JM 1.06 28-nov-1994 BUG: missing mm_stat shift for store case in trap_unalign (new bug due to "dismiss" code)
-// JM 1.07 1-dec-1994 EV5 PASS1,2,3 BUG WORKAROUND: Add flag LDVPTE_BUG_FIX. In DTBMISS_DOUBLE, branch to
-// DTBMISS_SINGLE if not in palmode.
-// JM 1.08 9-jan-1995 Bump version number for change to EV5_OSF_SYSTEM_PAL.M64 - ei_stat fix in mchk logout frame
-// JM 1.09 2-feb-1995 Add flag "spe_fix" and accompanying code to workaround pre-pass4 bug: Disable Ibox
-// superpage mode in User mode and re-enable in kernel mode.
-// EV5_OSF_SYSTEM_PAL.M64 and EV5_PALDEF.MAR (added pt_misc_v_cm) also changed to support this.
-// JM 1.10 24-feb-1995 Set ldvpte_bug_fix regardless of ev5 pass. set default to ev5_p2
-// ES 1.11 10-mar-1995 Add flag "osf_chm_fix" to enable dcache in user mode only to avoid
-// cpu bug.
-// JM 1.12 17-mar-1995 BUG FIX: Fix F0 corruption problem in pal_restore_state
-// ES 1.13 17-mar-1995 Refine osf_chm_fix
-// ES 1.14 20-mar-1995 Don't need as many stalls before hw_rei_stall in chm_fix
-// ES 1.15 21-mar-1995 Add a stall to avoid a pvc violation in pal_restore_state
-// Force pvc checking of exit_console
-// ES 1.16 26-apr-1995 In the wrperfmon disable function, correct meaning of R17<2:0> to ctl2,ctl2,ctl0
-// ES 1.17 01-may-1995 In hw_rei_update_spe code, in the osf_chm fix, use bic and bis (self-correcting)
-// instead of xor to maintain previous mode in pt_misc
-// ES 1.18 14-jul-1995 In wrperfmon enable on pass2, update pmctr even if current process does
-// not have pme set. The bits in icsr maintain the master enable state.
-// In sys_reset, add icsr<17>=1 for ev56 byte/word eco enable
-//
-#define vmaj 1
-#define vmin 18
-#define vms_pal 1
-#define osf_pal 2
-#define pal_type osf_pal
-#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0))
-//-
-
-// .sbttl "PALtemp register usage"
-
-//+
-// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage
-// for these PALtemps:
-//
-// pt0 local scratch
-// pt1 local scratch
-// pt2 entUna pt_entUna
-// pt3 CPU specific impure area pointer pt_impure
-// pt4 memory management temp
-// pt5 memory management temp
-// pt6 memory management temp
-// pt7 entIF pt_entIF
-// pt8 intmask pt_intmask
-// pt9 entSys pt_entSys
-// pt10
-// pt11 entInt pt_entInt
-// pt12 entArith pt_entArith
-// pt13 reserved for system specific PAL
-// pt14 reserved for system specific PAL
-// pt15 reserved for system specific PAL
-// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, pt_mces
-// pt17 sysval pt_sysval
-// pt18 usp pt_usp
-// pt19 ksp pt_ksp
-// pt20 PTBR pt_ptbr
-// pt21 entMM pt_entMM
-// pt22 kgp pt_kgp
-// pt23 PCBB pt_pcbb
-//
-//-
-
-// .sbttl "PALshadow register usage"
-//
-//+
-//
-// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1.
-// This maps the OSF PAL usage of R8 - R14 and R25:
-//
-// r8 ITBmiss/DTBmiss scratch
-// r9 ITBmiss/DTBmiss scratch
-// r10 ITBmiss/DTBmiss scratch
-// r11 PS
-// r12 local scratch
-// r13 local scratch
-// r14 local scratch
-// r25 local scratch
-//
-//
-//-
-
-// .sbttl "ALPHA symbol definitions"
-// _OSF_PSDEF GLOBAL
-// _OSF_PTEDEF GLOBAL
-// _OSF_VADEF GLOBAL
-// _OSF_PCBDEF GLOBAL
-// _OSF_SFDEF GLOBAL
-// _OSF_MMCSR_DEF GLOBAL
-// _SCBDEF GLOBAL
-// _FRMDEF GLOBAL
-// _EXSDEF GLOBAL
-// _OSF_A0_DEF GLOBAL
-// _MCESDEF GLOBAL
-
-// .sbttl "EV5 symbol definitions"
-
-// _EV5DEF
-// _PALTEMP
-// _MM_STAT_DEF
-// _EV5_MM
-// _EV5_IPLDEF
-
-// _HALT_CODES GLOBAL
-// _MCHK_CODES GLOBAL
-
-// _PAL_IMPURE
-// _PAL_LOGOUT
-
-
-
-
-// .sbttl "PALcode configuration options"
-
-// There are a number of options that may be assembled into this version of
-// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit
-// the following). The options that can be adjusted cause the resultant PALcode
-// to reflect the desired target system.
-
-
-#define osfpal 1 // This is the PALcode for OSF.
-
-#ifndef rawhide_system
-
-#define rawhide_system 0
-#endif
-
-
-#ifndef real_mm
-// Page table translation vs 1-1 mapping
-#define real_mm 1
-#endif
-
-
-#ifndef rax_mode
-
-#define rax_mode 0
-#endif
-
-#ifndef egore
-// End of reset flow starts a program at 200000(hex).
-#define egore 1
-#endif
-
-#ifndef acore
-// End of reset flow starts a program at 40000(hex).
-#define acore 0
-#endif
-
-
-// assume acore+egore+rax_mode lt 2 // Assertion checker
-
-#ifndef beh_model
-// EV5 behavioral model specific code
-#define beh_model 1
-#endif
-
-#ifndef init_cbox
-// Reset flow init of Bcache and Scache
-#define init_cbox 1
-#endif
-
-#ifndef disable_crd
-// Decides whether the reset flow will disable
-#define disable_crd 0
-#endif
-
- // correctable read interrupts via ICSR
-#ifndef perfmon_debug
-#define perfmon_debug 0
-#endif
-
-#ifndef icflush_on_tbix
-#define icflush_on_tbix 0
-#endif
-
-#ifndef remove_restore_state
-#define remove_restore_state 0
-#endif
-
-#ifndef remove_save_state
-#define remove_save_state 0
-#endif
-
-#ifndef enable_physical_console
-#define enable_physical_console 0
-#endif
-
-#ifndef ev5_p1
-#define ev5_p1 0
-#endif
-
-#ifndef ev5_p2
-#define ev5_p2 1
-#endif
-
-// assume ev5_p1+ev5_p2 eq 1
-
-#ifndef ldvpte_bug_fix
-#define ldvpte_bug_fix 1 // If set, fix ldvpte bug in dtbmiss_double flow.
-#endif
-
-#ifndef spe_fix
-// If set, disable super-page mode in user mode and re-enable
-#define spe_fix 0
-#endif
- // in kernel. Workaround for cpu bug.
-#ifndef build_fixed_image
-#define build_fixed_image 0
-#endif
-
-
-#ifndef fill_err_hack
-// If set, disable fill_error mode in user mode and re-enable
-#define fill_err_hack 0
-#endif
-
- // in kernel. Workaround for cpu bug.
-
-// .macro hw_rei_spe
-// .iif eq spe_fix, hw_rei
-//#if spe_fix != 0
-//
-//
-//#define hw_rei_chm_count hw_rei_chm_count + 1
-// p4_fixup_label \hw_rei_chm_count
-// .iif eq build_fixed_image, br r31, hw_rei_update_spe
-// .iif ne build_fixed_image, hw_rei
-//#endif
-//
-// .endm
-
-// Add flag "osf_chm_fix" to enable dcache in user mode only
-// to avoid cpu bug.
-
-#ifndef osf_chm_fix
-// If set, enable D-Cache in
-#define osf_chm_fix 0
-#endif
-
-#if osf_chm_fix != 0
-// user mode only.
-#define hw_rei_chm_count 0
-#endif
-
-#if osf_chm_fix != 0
-
-#define hw_rei_stall_chm_count 0
-#endif
-
-#ifndef enable_p4_fixups
-
-#define enable_p4_fixups 0
-#endif
-
- // If set, do EV5 Pass 4 fixups
-#if spe_fix == 0
-
-#define osf_chm_fix 0
-#endif
-
-#if spe_fix == 0
-
-#define enable_p4_fixups 0
-#endif
-
- // Only allow fixups if fix enabled
-
- //Turn off fill_errors and MEM_NEM in user mode
-// .macro fill_error_hack ?L10_, ?L20_, ?L30_, ?L40_
-// //save r22,r23,r24
-// stqp r22, 0x150(r31) //add
-// stqp r23, 0x158(r31) //contents
-// stqp r24, 0x160(r31) //bit mask
-//
-// lda r22, 0x82(r31)
-// ldah r22, 0x8740(r22)
-// sll r22, 8, r22
-// ldlp r23, 0x80(r22) // r23 <- contents of CIA_MASK
-// bis r23,r31,r23
-//
-// lda r24, 0x8(r31) // r24 <- MEM_NEM bit
-// beq r10, L10_ // IF user mode (r10<0> == 0) pal mode
-// bic r23, r24, r23 // set fillerr_en bit
-// br r31, L20_ // ELSE
-//L10_: bis r23, r24, r23 // clear fillerr_en bit
-//L20_: // ENDIF
-//
-// stlp r23, 0x80(r22) // write back the CIA_MASK register
-// mb
-// ldlp r23, 0x80(r22)
-// bis r23,r31,r23
-// mb
-//
-// lda r22, 1(r31) // r22 <- 87.4000.0100 ptr to CIA_CTRL
-// ldah r22, 0x8740(r22)
-// sll r22, 8, r22
-// ldlp r23, 0(r22) // r23 <- contents of CIA_CTRL
-// bis r23,r31,r23
-//
-//
-// lda r24, 0x400(r31) // r9 <- fillerr_en bit
-// beq r10, L30_ // IF user mode (r10<0> == 0) pal mode
-// bic r23, r24, r23 // set fillerr_en bit
-// br r31, L40_ // ELSE
-//L30_: bis r23, r24, r23 // clear fillerr_en bit
-//L40_: // ENDIF
-//
-// stlp r23, 0(r22) // write back the CIA_CTRL register
-// mb
-// ldlp r23, 0(r22)
-// bis r23,r31,r23
-// mb
-//
-// //restore r22,r23,r24
-// ldqp r22, 0x150(r31)
-// ldqp r23, 0x158(r31)
-// ldqp r24, 0x160(r31)
-//
-// .endm
-
-// multiprocessor support can be enabled for a max of n processors by
-// setting the following to the number of processors on the system.
-// Note that this is really the max cpuid.
-
-#ifndef max_cpuid
-#define max_cpuid 8
-#endif
-
-#ifndef osf_svmin // platform specific palcode version number
-#define osf_svmin 0
-#endif
-
-
-#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0))
-
-// .mcall ldqp // override macro64 definition with macro from library
-// .mcall stqp // override macro64 definition with macro from library
-
-
-// .psect _pal,mix
-// huh pb pal_base:
-// huh pb #define current_block_base . - pal_base
-
-// .sbttl "RESET - Reset Trap Entry Point"
-//+
-// RESET - offset 0000
-// Entry:
-// Vectored into via hardware trap on reset, or branched to
-// on swppal.
-//
-// r0 = whami
-// r1 = pal_base
-// r2 = base of scratch area
-// r3 = halt code
-//
-//
-// Function:
-//
-//-
-
- .text 0
- . = 0x0000
- .globl Pal_Base
-Pal_Base:
- HDW_VECTOR(PAL_RESET_ENTRY)
-Trap_Reset:
- nop
-#ifdef SIMOS
- /*
- * store into r1
- */
- br r1,sys_reset
-#else
- /* following is a srcmax change */
-
- DEBUGSTORE(0x41)
- /* The original code jumped using r1 as a linkage register to pass the base
- of PALcode to the platform specific code. We use r1 to pass a parameter
- from the SROM, so we hardcode the address of Pal_Base in platform.s
- */
- br r31, sys_reset
-#endif
-
- // Specify PAL version info as a constant
- // at a known location (reset + 8).
-
- .long osfpal_version_l // <pal_type@16> ! <vmaj@8> ! <vmin@0>
- .long osfpal_version_h // <max_cpuid@16> ! <osf_svmin@0>
- .long 0
- .long 0
-pal_impure_start:
- .quad 0
-pal_debug_ptr:
- .quad 0 // reserved for debug pointer ; 20
-#if beh_model == 0
-
-
-#if enable_p4_fixups != 0
-
-
- .quad 0
- .long p4_fixup_hw_rei_fixup_table
-#endif
-
-#else
-
- .quad 0 //
- .quad 0 //0x0030
- .quad 0
- .quad 0 //0x0040
- .quad 0
- .quad 0 //0x0050
- .quad 0
- .quad 0 //0x0060
- .quad 0
-pal_enter_cns_address:
- .quad 0 //0x0070 -- address to jump to from enter_console
- .long <<sys_exit_console-pal_base>+1> //0x0078 -- offset to sys_exit_console (set palmode bit)
-#endif
-
-
-
-
-// .sbttl "IACCVIO- Istream Access Violation Trap Entry Point"
-
-//+
-// IACCVIO - offset 0080
-// Entry:
-// Vectored into via hardware trap on Istream access violation or sign check error on PC.
-//
-// Function:
-// Build stack frame
-// a0 <- Faulting VA
-// a1 <- MMCSR (1 for ACV)
-// a2 <- -1 (for ifetch fault)
-// vector via entMM
-//-
-
- HDW_VECTOR(PAL_IACCVIO_ENTRY)
-Trap_Iaccvio:
- DEBUGSTORE(0x42)
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS
- bge r25, TRAP_IACCVIO_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r12 // Set new PS
- mfpr r30, pt_ksp
-
-TRAP_IACCVIO_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r16, osfsf_a0(sp) // save regs
- bic r14, 3, r16 // pass pc/va as a0
-
- stq r17, osfsf_a1(sp) // a1
- or r31, mmcsr_c_acv, r17 // pass mm_csr as a1
-
- stq r18, osfsf_a2(sp) // a2
- mfpr r13, pt_entmm // get entry point
-
- stq r11, osfsf_ps(sp) // save old ps
- bis r12, r31, r11 // update ps
-
- stq r16, osfsf_pc(sp) // save pc
- stq r29, osfsf_gp(sp) // save gp
-
- mtpr r13, exc_addr // load exc_addr with entMM
- // 1 cycle to hw_rei
- mfpr r29, pt_kgp // get the kgp
-
- subq r31, 1, r18 // pass flag of istream, as a2
- hw_rei_spe
-
-
-// .sbttl "INTERRUPT- Interrupt Trap Entry Point"
-
-//+
-// INTERRUPT - offset 0100
-// Entry:
-// Vectored into via trap on hardware interrupt
-//
-// Function:
-// check for halt interrupt
-// check for passive release (current ipl geq requestor)
-// if necessary, switch to kernel mode
-// push stack frame, update ps (including current mode and ipl copies), sp, and gp
-// pass the interrupt info to the system module
-//
-//-
-
-
- HDW_VECTOR(PAL_INTERRUPT_ENTRY)
-Trap_Interrupt:
- mfpr r13, ev5__intid // Fetch level of interruptor
- mfpr r25, ev5__isr // Fetch interrupt summary register
-
- srl r25, isr_v_hlt, r9 // Get HLT bit
- mfpr r14, ev5__ipl
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern
- blbs r9, sys_halt_interrupt // halt_interrupt if HLT bit set
-
- cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl
- bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl
-
- and r11, osfps_m_mode, r10 // get mode bit
- beq r10, TRAP_INTERRUPT_10_ // Skip stack swap in kernel
-
- mtpr r30, pt_usp // save user stack
- mfpr r30, pt_ksp // get kern stack
-
-TRAP_INTERRUPT_10_:
- lda sp, (0-osfsf_c_size)(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r11, osfsf_ps(sp) // save ps
- stq r14, osfsf_pc(sp) // save pc
-
- stq r29, osfsf_gp(sp) // push gp
- stq r16, osfsf_a0(sp) // a0
-
-// pvc_violate 354 // ps is cleared anyway, if store to stack faults.
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
- stq r17, osfsf_a1(sp) // a1
-
- stq r18, osfsf_a2(sp) // a2
- subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL
-
- srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7.
- subq r13, 0x1d, r9 // Check for 1d, 1e, 1f
-
- cmovge r9, r8, r12 // if .ge. 1d, then take shifted value
- bis r12, r31, r11 // set new ps
-
- mfpr r12, pt_intmask
- and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already)
-
-#ifdef SIMOS
- /*
- * Lance had space problems. We don't.
- */
- extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
- mfpr r29, pt_kgp // update gp
- mtpr r14, ev5__ipl // load the new IPL into Ibox
-#else
-// Moved the following three lines to sys_interrupt to make room for debug
-// extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
-// mfpr r29, pt_kgp // update gp
-
-// mtpr r14, ev5__ipl // load the new IPL into Ibox
-#endif
- br r31, sys_interrupt // Go handle interrupt
-
-
-
-// .sbttl "ITBMISS- Istream TBmiss Trap Entry Point"
-
-//+
-// ITBMISS - offset 0180
-// Entry:
-// Vectored into via hardware trap on Istream translation buffer miss.
-//
-// Function:
-// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid.
-// Can trap into DTBMISS_DOUBLE.
-// This routine can use the PALshadow registers r8, r9, and r10
-//
-//-
-
- HDW_VECTOR(PAL_ITB_MISS_ENTRY)
-Trap_Itbmiss:
-#if real_mm == 0
-
-
- // Simple 1-1 va->pa mapping
-
- nop // Pad to align to E1
- mfpr r8, exc_addr
-
- srl r8, page_offset_size_bits, r9
- sll r9, 32, r9
-
- lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
- mtpr r9, itb_pte // E1
-
- hw_rei_stall // Nital says I don't have to obey shadow wait rule here.
-#else
-
- // Real MM mapping
- nop
- mfpr r8, ev5__ifault_va_form // Get virtual address of PTE.
-
- nop
- mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss.
-
-pal_itb_ldq:
- ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss
- mtpr r10, exc_addr // Restore exc_address if there was a trap.
-
- mfpr r31, ev5__va // Unlock VA in case there was a double miss
- nop
-
- and r8, osfpte_m_foe, r25 // Look for FOE set.
- blbc r8, invalid_ipte_handler // PTE not valid.
-
- nop
- bne r25, foe_ipte_handler // FOE is set
-
- nop
- mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB.
-
- hw_rei_stall //
-
-#endif
-
-
-
-
-// .sbttl "DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point"
-
-//+
-// DTBMISS_SINGLE - offset 0200
-// Entry:
-// Vectored into via hardware trap on Dstream single translation buffer miss.
-//
-// Function:
-// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid.
-// Can trap into DTBMISS_DOUBLE.
-// This routine can use the PALshadow registers r8, r9, and r10
-//-
-
- HDW_VECTOR(PAL_DTB_MISS_ENTRY)
-Trap_Dtbmiss_Single:
-#if real_mm == 0
- // Simple 1-1 va->pa mapping
- mfpr r8, va // E0
- srl r8, page_offset_size_bits, r9
-
- sll r9, 32, r9
- lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
-
- mtpr r9, dtb_pte // E0
- nop // Pad to align to E0
-
-
-
- mtpr r8, dtb_tag // E0
- nop
-
- nop // Pad tag write
- nop
-
- nop // Pad tag write
- nop
-
- hw_rei
-#else
- mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0.
- mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1.
-
-// DEBUGSTORE(0x45)
-// DEBUG_EXC_ADDR()
- // Real MM mapping
- mfpr r9, ev5__mm_stat // Get read/write bit. E0.
- mtpr r10, pt6 // Stash exc_addr away
-
-pal_dtb_ldq:
- ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss
- nop // Pad MF VA
-
- mfpr r10, ev5__va // Get original faulting VA for TB load. E0.
- nop
-
- mtpr r8, ev5__dtb_pte // Write DTB PTE part. E0.
- blbc r8, invalid_dpte_handler // Handle invalid PTE
-
- mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles.
- mfpr r10, pt6
-
- // Following 2 instructions take 2 cycles
- mtpr r10, exc_addr // Return linkage in case we trapped. E1.
- mfpr r31, pt0 // Pad the write to dtb_tag
-
- hw_rei // Done, return
-#endif
-
-
-
-
-// .sbttl "DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point"
-
-//+
-// DTBMISS_DOUBLE - offset 0280
-// Entry:
-// Vectored into via hardware trap on Double TBmiss from single miss flows.
-//
-// r8 - faulting VA
-// r9 - original MMstat
-// r10 - original exc_addr (both itb,dtb miss)
-// pt6 - original exc_addr (dtb miss flow only)
-// VA IPR - locked with original faulting VA
-//
-// Function:
-// Get PTE, if valid load TB and return.
-// If not valid then take TNV/ACV exception.
-//
-// pt4 and pt5 are reserved for this flow.
-//
-//
-//-
-
- HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY)
-Trap_Dtbmiss_double:
-#if ldvpte_bug_fix != 0
- mtpr r8, pt4 // save r8 to do exc_addr check
- mfpr r8, exc_addr
- blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy!
- mfpr r8, pt4 // restore r8
-#endif
- nop
- mtpr r22, pt5 // Get some scratch space. E1.
- // Due to virtual scheme, we can skip the first lookup and go
- // right to fetch of level 2 PTE
- sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA
- mtpr r21, pt4 // Get some scratch space. E1.
-
- srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8
- mfpr r21, pt_ptbr // Get physical address of the page table.
-
- nop
- addq r21, r22, r21 // Index into page table for level 2 PTE.
-
- sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA
- ldqp r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
-
- srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8
- blbc r21, double_pte_inv // Check for Invalid PTE.
-
- srl r21, 32, r21 // extract PFN from PTE
- sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to <seg3>*8
-
- addq r21, r22, r21 // Index into page table for level 3 PTE.
- nop
-
- ldqp r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
- blbc r21, double_pte_inv // Check for invalid PTE.
-
- mtpr r21, ev5__dtb_pte // Write the PTE. E0.
- mfpr r22, pt5 // Restore scratch register
-
- mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles.
- mfpr r21, pt4 // Restore scratch register
-
- nop // Pad write to tag.
- nop
-
- nop // Pad write to tag.
- nop
-
- hw_rei
-
-
-
-// .sbttl "UNALIGN -- Dstream unalign trap"
-//+
-// UNALIGN - offset 0300
-// Entry:
-// Vectored into via hardware trap on unaligned Dstream reference.
-//
-// Function:
-// Build stack frame
-// a0 <- Faulting VA
-// a1 <- Opcode
-// a2 <- src/dst register number
-// vector via entUna
-//-
-
- HDW_VECTOR(PAL_UNALIGN_ENTRY)
-Trap_Unalign:
-/* DEBUGSTORE(0x47)*/
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss
- mfpr r14, exc_addr // get pc
-
- srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits
- blbs r14, pal_pal_bug_check // Bugcheck if unaligned in PAL
-
- blbs r8, UNALIGN_NO_DISMISS // lsb only set on store or fetch_m
- // not set, must be a load
- and r13, 0x1F, r8 // isolate ra
-
- cmpeq r8, 0x1F, r8 // check for r31/F31
- bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault
-
-UNALIGN_NO_DISMISS:
- bis r11, r31, r12 // Save PS
- bge r25, UNALIGN_NO_DISMISS_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r12 // Set new PS
- mfpr r30, pt_ksp
-
-UNALIGN_NO_DISMISS_10_:
- mfpr r25, ev5__va // Unlock VA
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
-
- mtpr r25, pt0 // Stash VA
- stq r18, osfsf_a2(sp) // a2
-
- stq r11, osfsf_ps(sp) // save old ps
- srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode
-
- stq r29, osfsf_gp(sp) // save gp
- addq r14, 4, r14 // inc PC past the ld/st
-
- stq r17, osfsf_a1(sp) // a1
- and r25, mm_stat_m_opcode, r17// Clean opocde for a1
-
- stq r16, osfsf_a0(sp) // save regs
- mfpr r16, pt0 // a0 <- va/unlock
-
- stq r14, osfsf_pc(sp) // save pc
- mfpr r25, pt_entuna // get entry point
-
-
- bis r12, r31, r11 // update ps
- br r31, unalign_trap_cont
-
-
-
-
-// .sbttl "DFAULT - Dstream Fault Trap Entry Point"
-
-//+
-// DFAULT - offset 0380
-// Entry:
-// Vectored into via hardware trap on dstream fault or sign check error on DVA.
-//
-// Function:
-// Ignore faults on FETCH/FETCH_M
-// Check for DFAULT in PAL
-// Build stack frame
-// a0 <- Faulting VA
-// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW)
-// a2 <- R/W
-// vector via entMM
-//
-//-
- HDW_VECTOR(PAL_D_FAULT_ENTRY)
-Trap_Dfault:
-// DEBUGSTORE(0x48)
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r13, ev5__mm_stat // Get mmstat
- mfpr r8, exc_addr // get pc, preserve r14
-
- srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits
- blbs r8, dfault_in_pal
-
- bis r8, r31, r14 // move exc_addr to correct place
- bis r11, r31, r12 // Save PS
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- and r9, mm_stat_m_opcode, r9 // Clean all but opcode
-
- cmpeq r9, evx_opc_sync, r9 // Is the opcode fetch/fetchm?
- bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault
-
- //dismiss exception if load to r31/f31
- blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm
-
- // not a store or fetch, must be a load
- srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits
-
- and r9, 0x1F, r9 // isolate rnum
- nop
-
- cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31?
- bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault
-
-dfault_no_dismiss:
- and r13, 0xf, r13 // Clean extra bits in mm_stat
- bge r25, dfault_trap_cont // no stack swap needed if cm=kern
-
-
- mtpr r30, pt_usp // save user stack
- bis r31, r31, r12 // Set new PS
-
- mfpr r30, pt_ksp
- br r31, dfault_trap_cont
-
-
-
-
-
-// .sbttl "MCHK - Machine Check Trap Entry Point"
-
-//+
-// MCHK - offset 0400
-// Entry:
-// Vectored into via hardware trap on machine check.
-//
-// Function:
-//
-//-
-
- HDW_VECTOR(PAL_MCHK_ENTRY)
-Trap_Mchk:
- DEBUGSTORE(0x49)
- mtpr r31, ic_flush_ctl // Flush the Icache
- br r31, sys_machine_check
-
-
-
-
-// .sbttl "OPCDEC - Illegal Opcode Trap Entry Point"
-
-//+
-// OPCDEC - offset 0480
-// Entry:
-// Vectored into via hardware trap on illegal opcode.
-//
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-
- HDW_VECTOR(PAL_OPCDEC_ENTRY)
-Trap_Opcdec:
- DEBUGSTORE(0x4a)
-//simos DEBUG_EXC_ADDR()
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r14, exc_addr // get pc
- blbs r14, pal_pal_bug_check // check opcdec in palmode
-
- bis r11, r31, r12 // Save PS
- bge r25, TRAP_OPCDEC_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r12 // Set new PS
- mfpr r30, pt_ksp
-
-TRAP_OPCDEC_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- addq r14, 4, r14 // inc pc
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_opdec, r16 // set a0
-
- stq r11, osfsf_ps(sp) // save old ps
- mfpr r13, pt_entif // get entry point
-
- stq r18, osfsf_a2(sp) // a2
- stq r17, osfsf_a1(sp) // a1
-
- stq r29, osfsf_gp(sp) // save gp
- stq r14, osfsf_pc(sp) // save pc
-
- bis r12, r31, r11 // update ps
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei, E1
-
- mfpr r29, pt_kgp // get the kgp, E1
-
- hw_rei_spe // done, E1
-
-
-
-
-
-
-// .sbttl "ARITH - Arithmetic Exception Trap Entry Point"
-
-//+
-// ARITH - offset 0500
-// Entry:
-// Vectored into via hardware trap on arithmetic excpetion.
-//
-// Function:
-// Build stack frame
-// a0 <- exc_sum
-// a1 <- exc_mask
-// a2 <- unpred
-// vector via entArith
-//
-//-
- HDW_VECTOR(PAL_ARITH_ENTRY)
-Trap_Arith:
- DEBUGSTORE(0x4b)
- and r11, osfps_m_mode, r12 // get mode bit
- mfpr r31, ev5__va // unlock mbox
-
- bis r11, r31, r25 // save ps
- mfpr r14, exc_addr // get pc
-
- nop
- blbs r14, pal_pal_bug_check // arith trap from PAL
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- beq r12, TRAP_ARITH_10_ // if zero we are in kern now
-
- bis r31, r31, r25 // set the new ps
- mtpr r30, pt_usp // save user stack
-
- nop
- mfpr r30, pt_ksp // get kern stack
-
-TRAP_ARITH_10_: lda sp, 0-osfsf_c_size(sp) // allocate stack space
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- nop // Pad current mode write and stq
- mfpr r13, ev5__exc_sum // get the exc_sum
-
- mfpr r12, pt_entarith
- stq r14, osfsf_pc(sp) // save pc
-
- stq r17, osfsf_a1(sp)
- mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
-
- stq r11, osfsf_ps(sp) // save ps
- bis r25, r31, r11 // set new ps
-
- stq r16, osfsf_a0(sp) // save regs
- srl r13, exc_sum_v_swc, r16// shift data to correct position
-
- stq r18, osfsf_a2(sp)
-// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow
- mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask
-
- stq r29, osfsf_gp(sp)
- mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1
-
- mfpr r29, pt_kgp // get the kern gp - E1
- hw_rei_spe // done - E1
-
-
-
-
-
-
-// .sbttl "FEN - Illegal Floating Point Operation Trap Entry Point"
-
-//+
-// FEN - offset 0580
-// Entry:
-// Vectored into via hardware trap on illegal FP op.
-//
-// Function:
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-
- HDW_VECTOR(PAL_FEN_ENTRY)
-Trap_Fen:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r14, exc_addr // get pc
- blbs r14, pal_pal_bug_check // check opcdec in palmode
-
- mfpr r13, ev5__icsr
- nop
-
- bis r11, r31, r12 // Save PS
- bge r25, TRAP_FEN_10_ // no stack swap needed if cm=kern
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r12 // Set new PS
- mfpr r30, pt_ksp
-
-TRAP_FEN_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0
-
-
- stq r16, osfsf_a0(sp) // save regs
- mfpr r13, pt_entif // get entry point
-
- stq r18, osfsf_a2(sp) // a2
- stq r11, osfsf_ps(sp) // save old ps
-
- stq r29, osfsf_gp(sp) // save gp
- bis r12, r31, r11 // set new ps
-
- stq r17, osfsf_a1(sp) // a1
- blbs r25,fen_to_opcdec // If FP is enabled, this is really OPCDEC.
-
- bis r31, osf_a0_fen, r16 // set a0
- stq r14, osfsf_pc(sp) // save pc
-
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei -E1
-
- mfpr r29, pt_kgp // get the kgp -E1
-
- hw_rei_spe // done -E1
-
-// FEN trap was taken, but the fault is really opcdec.
- ALIGN_BRANCH
-fen_to_opcdec:
- addq r14, 4, r14 // save PC+4
- bis r31, osf_a0_opdec, r16 // set a0
-
- stq r14, osfsf_pc(sp) // save pc
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei
-
- mfpr r29, pt_kgp // get the kgp
- hw_rei_spe // done
-
-
-
-// .sbttl "Misc handlers"
- // Start area for misc code.
-//+
-//dfault_trap_cont
-// A dfault trap has been taken. The sp has been updated if necessary.
-// Push a stack frame a vector via entMM.
-//
-// Current state:
-// r12 - new PS
-// r13 - MMstat
-// VA - locked
-//
-//-
- ALIGN_BLOCK
-dfault_trap_cont:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r25, ev5__va // Fetch VA/unlock
-
- stq r18, osfsf_a2(sp) // a2
- and r13, 1, r18 // Clean r/w bit for a2
-
- stq r16, osfsf_a0(sp) // save regs
- bis r25, r31, r16 // a0 <- va
-
- stq r17, osfsf_a1(sp) // a1
- srl r13, 1, r17 // shift fault bits to right position
-
- stq r11, osfsf_ps(sp) // save old ps
- bis r12, r31, r11 // update ps
-
- stq r14, osfsf_pc(sp) // save pc
- mfpr r25, pt_entmm // get entry point
-
- stq r29, osfsf_gp(sp) // save gp
- cmovlbs r17, 1, r17 // a2. acv overrides fox.
-
- mtpr r25, exc_addr // load exc_addr with entMM
- // 1 cycle to hw_rei
- mfpr r29, pt_kgp // get the kgp
-
- hw_rei_spe // done
-
-//+
-//unalign_trap_cont
-// An unalign trap has been taken. Just need to finish up a few things.
-//
-// Current state:
-// r25 - entUna
-// r13 - shifted MMstat
-//
-//-
- ALIGN_BLOCK
-unalign_trap_cont:
- mtpr r25, exc_addr // load exc_addr with entUna
- // 1 cycle to hw_rei
-
-
- mfpr r29, pt_kgp // get the kgp
- and r13, mm_stat_m_ra, r18 // Clean Ra for a2
-
- hw_rei_spe // done
-
-
-
-//+
-// dfault_in_pal
-// Dfault trap was taken, exc_addr points to a PAL PC.
-// r9 - mmstat<opcode> right justified
-// r8 - exception address
-//
-// These are the cases:
-// opcode was STQ -- from a stack builder, KSP not valid halt
-// r14 - original exc_addr
-// r11 - original PS
-// opcode was STL_C -- rti or retsys clear lock_flag by stack write,
-// KSP not valid halt
-// r11 - original PS
-// r14 - original exc_addr
-// opcode was LDQ -- retsys or rti stack read, KSP not valid halt
-// r11 - original PS
-// r14 - original exc_addr
-// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables
-// r10 - original exc_addr
-// r11 - original PS
-//
-//
-//-
- ALIGN_BLOCK
-dfault_in_pal:
- DEBUGSTORE(0x50)
- bic r8, 3, r8 // Clean PC
- mfpr r9, pal_base
-
- mfpr r31, va // unlock VA
-#if real_mm != 0
- // if not real_mm, should never get here from miss flows
-
- subq r9, r8, r8 // pal_base - offset
-
- lda r9, pal_itb_ldq-pal_base(r8)
- nop
-
- beq r9, dfault_do_bugcheck
- lda r9, pal_dtb_ldq-pal_base(r8)
-
- beq r9, dfault_do_bugcheck
-#endif
-
-//
-// KSP invalid halt case --
-ksp_inval_halt:
- DEBUGSTORE(76)
- bic r11, osfps_m_mode, r11 // set ps to kernel mode
- mtpr r0, pt0
-
- mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode
- mtpr r31, ips
-
- mtpr r14, exc_addr // Set PC to instruction that caused trouble
-//orig pvc_jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
-
- lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt
- br r31, sys_enter_console // enter the console
-
- ALIGN_BRANCH
-dfault_do_bugcheck:
- bis r10, r31, r14 // bugcheck expects exc_addr in r14
- br r31, pal_pal_bug_check
-
-
- ALIGN_BLOCK
-//+
-// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31
-// On entry -
-// r14 - exc_addr
-// VA is locked
-//
-//-
-dfault_fetch_ldr31_err:
- mtpr r11, ev5__dtb_cm
- mtpr r11, ev5__ps // Make sure ps hasn't changed
-
- mfpr r31, va // unlock the mbox
- addq r14, 4, r14 // inc the pc to skip the fetch
-
- mtpr r14, exc_addr // give ibox new PC
- mfpr r31, pt0 // pad exc_addr write
-
- hw_rei
-
-
-
- ALIGN_BLOCK
-//+
-// sys_from_kern
-// callsys from kernel mode - OS bugcheck machine check
-//
-//-
-sys_from_kern:
- mfpr r14, exc_addr // PC points to call_pal
- subq r14, 4, r14
-
- lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code
- br r31, pal_pal_mchk
-
-
-// .sbttl "Continuation of long call_pal flows"
- ALIGN_BLOCK
-//+
-// wrent_tbl
-// Table to write *int in paltemps.
-// 4 instructions/entry
-// r16 has new value
-//
-//-
-wrent_tbl:
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entint
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entarith
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entmm
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entif
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entuna
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entsys
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
- ALIGN_BLOCK
-//+
-// tbi_tbl
-// Table to do tbi instructions
-// 4 instructions per entry
-//-
-tbi_tbl:
- // -2 tbia
-//orig pvc_jsr tbi, dest=1
- mtpr r31, ev5__dtb_ia // Flush DTB
- mtpr r31, ev5__itb_ia // Flush ITB
-
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush // Flush Icache
-#else
-
- hw_rei_stall
-#endif
-
- nop // Pad table
-
- // -1 tbiap
-//orig pvc_jsr tbi, dest=1
- mtpr r31, ev5__dtb_iap // Flush DTB
- mtpr r31, ev5__itb_iap // Flush ITB
-
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush // Flush Icache
-#else
-
- hw_rei_stall
-#endif
-
- nop // Pad table
-
-
- // 0 unused
-//orig pvc_jsr tbi, dest=1
- hw_rei // Pad table
- nop
- nop
- nop
-
-
- // 1 tbisi
-//orig pvc_jsr tbi, dest=1
-#if icflush_on_tbix != 0
-
-
-
- nop
- br r31, pal_ic_flush_and_tbisi // Flush Icache
- nop
- nop // Pad table
-#else
-
- nop
- nop
- mtpr r17, ev5__itb_is // Flush ITB
- hw_rei_stall
-#endif
-
-
-
- // 2 tbisd
-//orig pvc_jsr tbi, dest=1
- mtpr r17, ev5__dtb_is // Flush DTB.
- nop
-
- nop
- hw_rei_stall
-
-
- // 3 tbis
-//orig pvc_jsr tbi, dest=1
- mtpr r17, ev5__dtb_is // Flush DTB
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush_and_tbisi // Flush Icache and ITB
-#else
- br r31, tbi_finish
- ALIGN_BRANCH
-tbi_finish:
- mtpr r17, ev5__itb_is // Flush ITB
- hw_rei_stall
-#endif
-
-
-
- ALIGN_BLOCK
-//+
-// bpt_bchk_common:
-// Finish up the bpt/bchk instructions
-//-
-bpt_bchk_common:
- stq r18, osfsf_a2(sp) // a2
- mfpr r13, pt_entif // get entry point
-
- stq r12, osfsf_ps(sp) // save old ps
- stq r14, osfsf_pc(sp) // save pc
-
- stq r29, osfsf_gp(sp) // save gp
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei
-
- mfpr r29, pt_kgp // get the kgp
-
-
- hw_rei_spe // done
-
-
- ALIGN_BLOCK
-//+
-// rti_to_user
-// Finish up the rti instruction
-//-
-rti_to_user:
- mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
- mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
-
- mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles
- mtpr r25, pt_ksp // save off incase RTI to user
-
- mfpr r30, pt_usp
- hw_rei_spe // and back
-
-
- ALIGN_BLOCK
-//+
-// rti_to_kern
-// Finish up the rti instruction
-//-
-rti_to_kern:
- and r12, osfps_m_ipl, r11 // clean ps
- mfpr r12, pt_intmask // get int mask
-
- extbl r12, r11, r12 // get mask for this ipl
- mtpr r25, pt_ksp // save off incase RTI to user
-
- mtpr r12, ev5__ipl // set the new ipl.
- or r25, r31, sp // sp
-
-// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals
- hw_rei
-
- ALIGN_BLOCK
-//+
-// swpctx_cont
-// Finish up the swpctx instruction
-//-
-
-swpctx_cont:
-#if ev5_p1 != 0
-
-
- bic r25, r24, r25 // clean icsr<FPE>
- get_impure r8 // get impure pointer
-
- sll r12, icsr_v_fpe, r12 // shift new fen to pos
- fix_impure_ipr r8 // adjust impure pointer
-
- restore_reg1 pmctr_ctl, r8, r8, ipr=1 // "ldqp" - get pmctr_ctl bits
- srl r23, 32, r24 // move asn to low asn pos
-
- ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
- srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
-
- or r25, r12, r25 // icsr with new fen
- sll r24, itb_asn_v_asn, r12
-
-#else
-
- bic r25, r24, r25 // clean icsr<FPE,PMP>
- sll r12, icsr_v_fpe, r12 // shift new fen to pos
-
- ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
- srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
-
- or r25, r12, r25 // icsr with new fen
- srl r23, 32, r24 // move asn to low asn pos
-
- and r22, 1, r22
- sll r24, itb_asn_v_asn, r12
-
- sll r22, icsr_v_pmp, r22
- nop
-
- or r25, r22, r25 // icsr with new pme
-#endif
-
- sll r24, dtb_asn_v_asn, r24
-
- subl r23, r13, r13 // gen new cc offset
- mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4
-
- mtpr r24, dtb_asn // Load up new ASN
- mtpr r25, icsr // write the icsr
-
- sll r14, page_offset_size_bits, r14 // Move PTBR into internal position.
- ldqp r25, osfpcb_q_usp(r16) // get new usp
-
- insll r13, 4, r13 // >> 32
-// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
- mtpr r14, pt_ptbr // load the new ptbr
-
- mtpr r13, cc // set new offset
- ldqp r30, osfpcb_q_ksp(r16) // get new ksp
-
-// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
- mtpr r25, pt_usp // save usp
-
-#if ev5_p1 != 0
-
-
- blbc r8, no_pm_change // if monitoring all processes -- no need to change pm
-
- // otherwise, monitoring select processes - update pm
- lda r25, 0x3F(r31)
- cmovlbc r22, r31, r8 // if pme set, disable counters, otherwise use saved encodings
-
- sll r25, pmctr_v_ctl2, r25 // create ctl field bit mask
- mfpr r22, ev5__pmctr
-
- and r8, r25, r8 // mask new ctl value
- bic r22, r25, r22 // clear ctl field in pmctr
-
- or r8, r22, r8
- mtpr r8, ev5__pmctr
-
-no_pm_change:
-#endif
-
-
-#if osf_chm_fix != 0
-
-
- p4_fixup_hw_rei_stall // removes this section for Pass 4 by placing a hw_rei_stall here
-
-#if build_fixed_image != 0
-
-
- hw_rei_stall
-#else
-
- mfpr r9, pt_pcbb // get FEN
-#endif
-
- ldqp r9, osfpcb_q_fen(r9)
- blbc r9, no_pm_change_10_ // skip if FEN disabled
-
- mb // ensure no outstanding fills
- lda r12, 1<<dc_mode_v_dc_ena(r31)
- mtpr r12, dc_mode // turn dcache on so we can flush it
- nop // force correct slotting
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
-
- lda r8, 0(r31) // flood the dcache with junk data
-no_pm_change_5_: ldqp r31, 0(r8)
- lda r8, 0x20(r8) // touch each cache block
- srl r8, 13, r9
- blbc r9, no_pm_change_5_
-
- mb // ensure no outstanding fills
- mtpr r31, dc_mode // turn the dcache back off
- nop // force correct slotting
- mfpr r31, pt0 // no hw_rei_stall in 0,1
-#endif
-
-
-no_pm_change_10_: hw_rei_stall // back we go
-
- ALIGN_BLOCK
-//+
-// swppal_cont - finish up the swppal call_pal
-//-
-
-swppal_cont:
- mfpr r2, pt_misc // get misc bits
- sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit
- or r2, r0, r2 // set the bit
- mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel)
- mtpr r2, pt_misc // update the chip
-
- or r3, r31, r4
- mfpr r3, pt_impure // pass pointer to the impure area in r3
-//orig fix_impure_ipr r3 // adjust impure pointer for ipr read
-//orig restore_reg1 bc_ctl, r1, r3, ipr=1 // pass cns_bc_ctl in r1
-//orig restore_reg1 bc_config, r2, r3, ipr=1 // pass cns_bc_config in r2
-//orig unfix_impure_ipr r3 // restore impure pointer
- lda r3, CNS_Q_IPR(r3)
- RESTORE_SHADOW(r1,CNS_Q_BC_CTL,r3);
- RESTORE_SHADOW(r1,CNS_Q_BC_CFG,r3);
- lda r3, -CNS_Q_IPR(r3)
-
- or r31, r31, r0 // set status to success
-// pvc_violate 1007
- jmp r31, (r4) // and call our friend, it's her problem now
-
-
-swppal_fail:
- addq r0, 1, r0 // set unknown pal or not loaded
- hw_rei // and return
-
-
-// .sbttl "Memory management"
-
- ALIGN_BLOCK
-//+
-//foe_ipte_handler
-// IFOE detected on level 3 pte, sort out FOE vs ACV
-//
-// on entry:
-// with
-// R8 = pte
-// R10 = pc
-//
-// Function
-// Determine TNV vs ACV vs FOE. Build stack and dispatch
-// Will not be here if TNV.
-//-
-
-foe_ipte_handler:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
- srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
- nop
-
-foe_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0>
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
-
- or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack
- mfpr r13, pt_entmm // get entry point
-
- stq r16, osfsf_a0(sp) // a0
- or r14, r31, r16 // pass pc/va as a0
-
- stq r17, osfsf_a1(sp) // a1
- nop
-
- stq r18, osfsf_a2(sp) // a2
- lda r17, mmcsr_c_acv(r31) // assume ACV
-
- stq r16, osfsf_pc(sp) // save pc
- cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE
-
- stq r12, osfsf_ps(sp) // save ps
- subq r31, 1, r18 // pass flag of istream as a2
-
- stq r29, osfsf_gp(sp)
- mtpr r13, exc_addr // set vector address
-
- mfpr r29, pt_kgp // load kgp
- hw_rei_spe // out to exec
-
- ALIGN_BLOCK
-//+
-//invalid_ipte_handler
-// TNV detected on level 3 pte, sort out TNV vs ACV
-//
-// on entry:
-// with
-// R8 = pte
-// R10 = pc
-//
-// Function
-// Determine TNV vs ACV. Build stack and dispatch.
-//-
-
-invalid_ipte_handler:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
- srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
- nop
-
-invalid_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0>
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
-
- or r10, r31, r14 // Save pc/va in case TBmiss on stack
- mfpr r13, pt_entmm // get entry point
-
- stq r16, osfsf_a0(sp) // a0
- or r14, r31, r16 // pass pc/va as a0
-
- stq r17, osfsf_a1(sp) // a1
- nop
-
- stq r18, osfsf_a2(sp) // a2
- and r25, 1, r17 // Isolate kre
-
- stq r16, osfsf_pc(sp) // save pc
- xor r17, 1, r17 // map to acv/tnv as a1
-
- stq r12, osfsf_ps(sp) // save ps
- subq r31, 1, r18 // pass flag of istream as a2
-
- stq r29, osfsf_gp(sp)
- mtpr r13, exc_addr // set vector address
-
- mfpr r29, pt_kgp // load kgp
- hw_rei_spe // out to exec
-
-
-
-
- ALIGN_BLOCK
-//+
-//invalid_dpte_handler
-// INVALID detected on level 3 pte, sort out TNV vs ACV
-//
-// on entry:
-// with
-// R10 = va
-// R8 = pte
-// R9 = mm_stat
-// PT6 = pc
-//
-// Function
-// Determine TNV vs ACV. Build stack and dispatch
-//-
-
-
-invalid_dpte_handler:
- mfpr r12, pt6
- blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode
-
- bis r12, r31, r14 // save PC in case of tbmiss or fault
- srl r9, mm_stat_v_opcode, r25 // shift opc to <0>
-
- mtpr r11, pt0 // Save PS for stack write
- and r25, mm_stat_m_opcode, r25 // isolate opcode
-
- cmpeq r25, evx_opc_sync, r25 // is it FETCH/FETCH_M?
- blbs r25, nmiss_fetch_ldr31_err // yes
-
- //dismiss exception if load to r31/f31
- blbs r9, invalid_dpte_no_dismiss // mm_stat<0> set on store or fetchm
-
- // not a store or fetch, must be a load
- srl r9, mm_stat_v_ra, r25 // Shift rnum to low bits
-
- and r25, 0x1F, r25 // isolate rnum
- nop
-
- cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31?
- bne r25, nmiss_fetch_ldr31_err // Yes, dismiss the fault
-
-invalid_dpte_no_dismiss:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- bge r25, invalid_dpte_no_dismiss_10_ // no stack swap needed if cm=kern
-
- srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-invalid_dpte_no_dismiss_10_: srl r8, osfpte_v_kre, r12 // get kre to <0>
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
-
- or r10, r31, r25 // Save va in case TBmiss on stack
- and r9, 1, r13 // save r/w flag
-
- stq r16, osfsf_a0(sp) // a0
- or r25, r31, r16 // pass va as a0
-
- stq r17, osfsf_a1(sp) // a1
- or r31, mmcsr_c_acv, r17 // assume acv
-
- srl r12, osfpte_v_kwe-osfpte_v_kre, r25 // get write enable to <0>
- stq r29, osfsf_gp(sp)
-
- stq r18, osfsf_a2(sp) // a2
- cmovlbs r13, r25, r12 // if write access move acv based on write enable
-
- or r13, r31, r18 // pass flag of dstream access and read vs write
- mfpr r25, pt0 // get ps
-
- stq r14, osfsf_pc(sp) // save pc
- mfpr r13, pt_entmm // get entry point
-
- stq r25, osfsf_ps(sp) // save ps
- mtpr r13, exc_addr // set vector address
-
- mfpr r29, pt_kgp // load kgp
- cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv
-
- hw_rei_spe // out to exec
-
-//+
-//
-// We come here if we are erring on a dtb_miss, and the instr is a
-// fetch, fetch_m, of load to r31/f31.
-// The PC is incremented, and we return to the program.
-// essentially ignoring the instruction and error.
-//
-//-
- ALIGN_BLOCK
-nmiss_fetch_ldr31_err:
- mfpr r12, pt6
- addq r12, 4, r12 // bump pc to pc+4
-
- mtpr r12, exc_addr // and set entry point
- mfpr r31, pt0 // pad exc_addr write
-
- hw_rei //
-
- ALIGN_BLOCK
-//+
-// double_pte_inv
-// We had a single tbmiss which turned into a double tbmiss which found
-// an invalid PTE. Return to single miss with a fake pte, and the invalid
-// single miss flow will report the error.
-//
-// on entry:
-// r21 PTE
-// r22 available
-// VA IPR locked with original fault VA
-// pt4 saved r21
-// pt5 saved r22
-// pt6 original exc_addr
-//
-// on return to tbmiss flow:
-// r8 fake PTE
-//
-//
-//-
-double_pte_inv:
- srl r21, osfpte_v_kre, r21 // get the kre bit to <0>
- mfpr r22, exc_addr // get the pc
-
- lda r22, 4(r22) // inc the pc
- lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set
-
- cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0
- mtpr r22, exc_addr // set for rei
-
- mfpr r21, pt4 // restore regs
- mfpr r22, pt5 // restore regs
-
- hw_rei // back to tb miss
-
- ALIGN_BLOCK
-//+
-//tnv_in_pal
-// The only places in pal that ld or store are the
-// stack builders, rti or retsys. Any of these mean we
-// need to take a ksp not valid halt.
-//
-//-
-tnv_in_pal:
-
-
- br r31, ksp_inval_halt
-
-
-// .sbttl "Icache flush routines"
-
- ALIGN_BLOCK
-//+
-// Common Icache flush routine.
-//
-//
-//-
-pal_ic_flush:
- nop
- mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
- nop
- nop
-
-// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20)
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 10
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 20
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 30
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 40
-
- nop
- nop
-
-one_cycle_and_hw_rei:
- nop
- nop
-
- hw_rei_stall
-
-#if icflush_on_tbix != 0
-
-
- ALIGN_BLOCK
-
-//+
-// Common Icache flush and ITB invalidate single routine.
-// ITBIS and hw_rei_stall must be in same octaword.
-// r17 - has address to invalidate
-//
-//-
-PAL_IC_FLUSH_AND_TBISI:
- nop
- mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
- nop
- nop
-
-// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20)
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 10
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 20
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 30
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 40
-
-
- nop
- nop
-
- nop
- nop
-
- // A quadword is 64 bits, so an octaword is 128 bits -> 16 bytes -> 4 instructions
- // 44 nops plus 4 instructions before it is 48 instructions.
- // Since this routine started on a 32-byte (8 instruction) boundary,
- // the following 2 instructions will be in the same octword as required.
-// ALIGN_BRANCH
- mtpr r17, ev5__itb_is // Flush ITB
- hw_rei_stall
-
-#endif
-
- ALIGN_BLOCK
-//+
-//osfpal_calpal_opcdec
-// Here for all opcdec CALL_PALs
-//
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-
-osfpal_calpal_opcdec:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r14, exc_addr // get pc
- nop
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, osfpal_calpal_opcdec_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-osfpal_calpal_opcdec_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- nop
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_opdec, r16 // set a0
-
- stq r18, osfsf_a2(sp) // a2
- mfpr r13, pt_entif // get entry point
-
- stq r12, osfsf_ps(sp) // save old ps
- stq r17, osfsf_a1(sp) // a1
-
- stq r14, osfsf_pc(sp) // save pc
- nop
-
- stq r29, osfsf_gp(sp) // save gp
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei
-
- mfpr r29, pt_kgp // get the kgp
-
-
- hw_rei_spe // done
-
-
-
-
-
-//+
-//pal_update_pcb
-// Update the PCB with the current SP, AST, and CC info
-//
-// r0 - return linkage
-//-
- ALIGN_BLOCK
-
-pal_update_pcb:
- mfpr r12, pt_pcbb // get pcbb
- and r11, osfps_m_mode, r25 // get mode
- beq r25, pal_update_pcb_10_ // in kern? no need to update user sp
- mtpr r30, pt_usp // save user stack
- stqp r30, osfpcb_q_usp(r12) // store usp
- br r31, pal_update_pcb_20_ // join common
-pal_update_pcb_10_: stqp r30, osfpcb_q_ksp(r12) // store ksp
-pal_update_pcb_20_: rpcc r13 // get cyccounter
- srl r13, 32, r14 // move offset
- addl r13, r14, r14 // merge for new time
- stlp r14, osfpcb_l_cc(r12) // save time
-
-//orig pvc_jsr updpcb, bsr=1, dest=1
- ret r31, (r0)
-
-
-
-#if remove_save_state == 0
-
-// .sbttl "PAL_SAVE_STATE"
-//+
-//
-// Pal_save_state
-//
-// Function
-// All chip state saved, all PT's, SR's FR's, IPR's
-//
-//
-// Regs' on entry...
-//
-// R0 = halt code
-// pt0 = r0
-// R1 = pointer to impure
-// pt4 = r1
-// R3 = return addr
-// pt5 = r3
-//
-// register usage:
-// r0 = halt_code
-// r1 = addr of impure area
-// r3 = return_address
-// r4 = scratch
-//
-//-
-
-
- ALIGN_BLOCK
- .globl pal_save_state
-pal_save_state:
-//
-//
-// start of implementation independent save routine
-//
-// the impure area is larger than the addressibility of hw_ld and hw_st
-// therefore, we need to play some games: The impure area
-// is informally divided into the "machine independent" part and the
-// "machine dependent" part. The state that will be saved in the
-// "machine independent" part are gpr's, fpr's, hlt, flag, mchkflag (use (un)fix_impure_gpr macros).
-// All others will be in the "machine dependent" part (use (un)fix_impure_ipr macros).
-// The impure pointer will need to be adjusted by a different offset for each. The store/restore_reg
-// macros will automagically adjust the offset correctly.
-//
-
-// The distributed code is commented out and followed by corresponding SRC code.
-// Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0)
-
-//orig fix_impure_gpr r1 // adjust impure area pointer for stores to "gpr" part of impure area
- lda r1, 0x200(r1) // Point to center of CPU segment
-//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag
- SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag
-//orig store_reg1 hlt, r0, r1, ipr=1
- SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code
-
- mfpr r0, pt0 // get r0 back //orig
-//orig store_reg1 0, r0, r1 // save r0
- SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0
-
- mfpr r0, pt4 // get r1 back //orig
-//orig store_reg1 1, r0, r1 // save r1
- SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1
-
-//orig store_reg 2 // save r2
- SAVE_GPR(r2,CNS_Q_GPR+0x10,r1) // Save r2
-
- mfpr r0, pt5 // get r3 back //orig
-//orig store_reg1 3, r0, r1 // save r3
- SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3
-
- // reason code has been saved
- // r0 has been saved
- // r1 has been saved
- // r2 has been saved
- // r3 has been saved
- // pt0, pt4, pt5 have been lost
-
- //
- // Get out of shadow mode
- //
-
- mfpr r2, icsr // Get icsr //orig
-//orig ldah r0, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
- ldah r0, (1<<(icsr_v_sde-16))(r31)
- bic r2, r0, r0 // ICSR with SDE clear //orig
- mtpr r0, icsr // Turn off SDE //orig
-
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
-
-
- // save integer regs R4-r31
-//orig #define t 4
-//orig .repeat 28
-//orig store_reg \t
-//orig #define t t + 1
-//orig .endr
- SAVE_GPR(r4,CNS_Q_GPR+0x20,r1)
- SAVE_GPR(r5,CNS_Q_GPR+0x28,r1)
- SAVE_GPR(r6,CNS_Q_GPR+0x30,r1)
- SAVE_GPR(r7,CNS_Q_GPR+0x38,r1)
- SAVE_GPR(r8,CNS_Q_GPR+0x40,r1)
- SAVE_GPR(r9,CNS_Q_GPR+0x48,r1)
- SAVE_GPR(r10,CNS_Q_GPR+0x50,r1)
- SAVE_GPR(r11,CNS_Q_GPR+0x58,r1)
- SAVE_GPR(r12,CNS_Q_GPR+0x60,r1)
- SAVE_GPR(r13,CNS_Q_GPR+0x68,r1)
- SAVE_GPR(r14,CNS_Q_GPR+0x70,r1)
- SAVE_GPR(r15,CNS_Q_GPR+0x78,r1)
- SAVE_GPR(r16,CNS_Q_GPR+0x80,r1)
- SAVE_GPR(r17,CNS_Q_GPR+0x88,r1)
- SAVE_GPR(r18,CNS_Q_GPR+0x90,r1)
- SAVE_GPR(r19,CNS_Q_GPR+0x98,r1)
- SAVE_GPR(r20,CNS_Q_GPR+0xA0,r1)
- SAVE_GPR(r21,CNS_Q_GPR+0xA8,r1)
- SAVE_GPR(r22,CNS_Q_GPR+0xB0,r1)
- SAVE_GPR(r23,CNS_Q_GPR+0xB8,r1)
- SAVE_GPR(r24,CNS_Q_GPR+0xC0,r1)
- SAVE_GPR(r25,CNS_Q_GPR+0xC8,r1)
- SAVE_GPR(r26,CNS_Q_GPR+0xD0,r1)
- SAVE_GPR(r27,CNS_Q_GPR+0xD8,r1)
- SAVE_GPR(r28,CNS_Q_GPR+0xE0,r1)
- SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1)
- SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1)
- SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1)
-
- // save all paltemp regs except pt0
-
-//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores
-//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores
-//orig #define t 1
-//orig .repeat 23
-//orig store_reg \t , pal=1
-//orig #define t t + 1
-//orig .endr
-
- lda r1, -0x200(r1) // Restore the impure base address.
- lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area.
- SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle
- SAVE_IPR(pt1,CNS_Q_PT+0x08,r1)
- SAVE_IPR(pt2,CNS_Q_PT+0x10,r1)
- SAVE_IPR(pt3,CNS_Q_PT+0x18,r1)
- SAVE_IPR(pt4,CNS_Q_PT+0x20,r1)
- SAVE_IPR(pt5,CNS_Q_PT+0x28,r1)
- SAVE_IPR(pt6,CNS_Q_PT+0x30,r1)
- SAVE_IPR(pt7,CNS_Q_PT+0x38,r1)
- SAVE_IPR(pt8,CNS_Q_PT+0x40,r1)
- SAVE_IPR(pt9,CNS_Q_PT+0x48,r1)
- SAVE_IPR(pt10,CNS_Q_PT+0x50,r1)
- SAVE_IPR(pt11,CNS_Q_PT+0x58,r1)
- SAVE_IPR(pt12,CNS_Q_PT+0x60,r1)
- SAVE_IPR(pt13,CNS_Q_PT+0x68,r1)
- SAVE_IPR(pt14,CNS_Q_PT+0x70,r1)
- SAVE_IPR(pt15,CNS_Q_PT+0x78,r1)
- SAVE_IPR(pt16,CNS_Q_PT+0x80,r1)
- SAVE_IPR(pt17,CNS_Q_PT+0x88,r1)
- SAVE_IPR(pt18,CNS_Q_PT+0x90,r1)
- SAVE_IPR(pt19,CNS_Q_PT+0x98,r1)
- SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1)
- SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1)
- SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1)
- SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1)
-
- // Restore shadow mode
- mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) //orig
- mfpr r31, pt0 //orig
- mtpr r2, icsr // Restore original ICSR //orig
-
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
-
- // save all integer shadow regs
-
-//orig #define t 8
-//orig .repeat 7
-//orig store_reg \t, shadow=1
-//orig #define t t + 1
-//orig .endr
-//orig store_reg 25, shadow=1
-
- SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code
- SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1)
- SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1)
- SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1)
- SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1)
- SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1)
- SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1)
- SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1)
-
-//orig store_reg exc_addr, ipr=1 // save ipr
-//orig store_reg pal_base, ipr=1 // save ipr
-//orig store_reg mm_stat, ipr=1 // save ipr
-//orig store_reg va, ipr=1 // save ipr
-//orig store_reg icsr, ipr=1 // save ipr
-//orig store_reg ipl, ipr=1 // save ipr
-//orig store_reg ps, ipr=1 // save ipr
-//orig store_reg itb_asn, ipr=1 // save ipr
-//orig store_reg aster, ipr=1 // save ipr
-//orig store_reg astrr, ipr=1 // save ipr
-//orig store_reg sirr, ipr=1 // save ipr
-//orig store_reg isr, ipr=1 // save ipr
-//orig store_reg ivptbr, ipr=1 // save ipr
-//orig store_reg mcsr, ipr=1 // save ipr
-//orig store_reg dc_mode, ipr=1 // save ipr
-
- SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1)
- SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1)
- SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1)
- SAVE_IPR(va,CNS_Q_VA,r1)
- SAVE_IPR(icsr,CNS_Q_ICSR,r1)
- SAVE_IPR(ipl,CNS_Q_IPL,r1)
- SAVE_IPR(ips,CNS_Q_IPS,r1)
- SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1)
- SAVE_IPR(aster,CNS_Q_ASTER,r1)
- SAVE_IPR(astrr,CNS_Q_ASTRR,r1)
- SAVE_IPR(sirr,CNS_Q_SIRR,r1)
- SAVE_IPR(isr,CNS_Q_ISR,r1)
- SAVE_IPR(iVptBr,CNS_Q_IVPTBR,r1)
- SAVE_IPR(mcsr,CNS_Q_MCSR,r1)
- SAVE_IPR(dcMode,CNS_Q_DC_MODE,r1)
-
-//orig pvc_violate 379 // mf maf_mode after a store ok (pvc doesn't distinguish ld from st)
-//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for
-//orig // PVC violation applies only to
-pvc$osf35$379: // loads. HW_ST ok here, so ignore
- SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2
-
-
- //the following iprs are informational only -- will not be restored
-
-//orig store_reg icperr_stat, ipr=1
-//orig store_reg pmctr, ipr=1
-//orig store_reg intid, ipr=1
-//orig store_reg exc_sum, ipr=1
-//orig store_reg exc_mask, ipr=1
-//orig ldah r14, 0xfff0(r31)
-//orig zap r14, 0xE0, r14 // Get Cbox IPR base
-//orig nop // pad mf dcperr_stat out of shadow of last store
-//orig nop
-//orig nop
-//orig store_reg dcperr_stat, ipr=1
-
- SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1)
- SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1)
- SAVE_IPR(intId,CNS_Q_INT_ID,r1)
- SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1)
- SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1)
- ldah r14, 0xFFF0(zero)
- zap r14, 0xE0, r14 // Get base address of CBOX IPRs
- NOP // Pad mfpr dcPerr out of shadow of
- NOP // last store
- NOP
- SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1)
-
- // read cbox ipr state
-
-//orig mb
-//orig ldqp r2, ev5__sc_ctl(r14)
-//orig ldqp r13, ld_lock(r14)
-//orig ldqp r4, ev5__sc_addr(r14)
-//orig ldqp r5, ev5__ei_addr(r14)
-//orig ldqp r6, ev5__bc_tag_addr(r14)
-//orig ldqp r7, ev5__fill_syn(r14)
-//orig bis r5, r4, r31
-//orig bis r7, r6, r31 // make sure previous loads finish before reading stat registers which unlock them
-//orig ldqp r8, ev5__sc_stat(r14) // unlocks sc_stat,sc_addr
-//orig ldqp r9, ev5__ei_stat(r14) // may unlock ei_*, bc_tag_addr, fill_syn
-//orig ldqp r31, ev5__ei_stat(r14) // ensures it is really unlocked
-//orig mb
-
-#ifndef SIMOS
- mb
- ldq_p r2, scCtl(r14)
- ldq_p r13, ldLock(r14)
- ldq_p r4, scAddr(r14)
- ldq_p r5, eiAddr(r14)
- ldq_p r6, bcTagAddr(r14)
- ldq_p r7, fillSyn(r14)
- bis r5, r4, zero // Make sure all loads complete before
- bis r7, r6, zero // reading registers that unlock them.
- ldq_p r8, scStat(r14) // Unlocks scAddr.
- ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn.
- ldq_p zero, eiStat(r14) // Make sure it is really unlocked.
- mb
-#endif
-//orig // save cbox ipr state
-//orig store_reg1 sc_ctl, r2, r1, ipr=1
-//orig store_reg1 ld_lock, r13, r1, ipr=1
-//orig store_reg1 sc_addr, r4, r1, ipr=1
-//orig store_reg1 ei_addr, r5, r1, ipr=1
-//orig store_reg1 bc_tag_addr, r6, r1, ipr=1
-//orig store_reg1 fill_syn, r7, r1, ipr=1
-//orig store_reg1 sc_stat, r8, r1, ipr=1
-//orig store_reg1 ei_stat, r9, r1, ipr=1
-//orig //bc_config? sl_rcv?
-
- SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1);
- SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1);
- SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1);
- SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1);
- SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1);
- SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1);
- SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1);
- SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1);
-
-// restore impure base //orig
-//orig unfix_impure_ipr r1
- lda r1, -CNS_Q_IPR(r1)
-
-// save all floating regs //orig
- mfpr r0, icsr // get icsr //orig
- or r31, 1, r2 // get a one //orig
-//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot //orig
- sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position
- or r2, r0, r0 // set FEN on //orig
- mtpr r0, icsr // write to icsr, enabling FEN //orig
-
-// map the save area virtually
-// orig mtpr r31, dtb_ia // clear the dtb
-// orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
-// orig sll r0, 32, r0 // shift to PFN field
-// orig lda r2, 0xff(r31) // all read enable and write enable bits set
-// orig sll r2, 8, r2 // move to PTE location
-// orig addq r0, r2, r0 // combine with PFN
-// orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-// orig mtpr r1, dtb_tag // write TB tag
-
- mtpr r31, dtbIa // Clear all DTB entries
- srl r1, va_s_off, r0 // Clean off byte-within-page offset
- sll r0, pte_v_pfn, r0 // Shift to form PFN
- lda r0, pte_m_prot(r0) // Set all read/write enable bits
- mtpr r0, dtbPte // Load the PTE and set valid
- mtpr r1, dtbTag // Write the PTE and tag into the DTB
-
-
-//orig // map the next page too - in case the impure area crosses a page boundary
-//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
-//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r4, dtb_tag // write TB tag
-
- lda r4, (1<<va_s_off)(r1) // Generate address for next page
- srl r4, va_s_off, r0 // Clean off byte-within-page offset
- sll r0, pte_v_pfn, r0 // Shift to form PFN
- lda r0, pte_m_prot(r0) // Set all read/write enable bits
- mtpr r0, dtbPte // Load the PTE and set valid
- mtpr r4, dtbTag // Write the PTE and tag into the DTB
-
- sll r31, 0, r31 // stall cycle 1 // orig
- sll r31, 0, r31 // stall cycle 2 // orig
- sll r31, 0, r31 // stall cycle 3 // orig
- nop // orig
-
-//orig // add offset for saving fpr regs
-//orig fix_impure_gpr r1
-
- lda r1, 0x200(r1) // Point to center of CPU segment
-
-// now save the regs - F0-F31
-
-//orig #define t 0
-//orig .repeat 32
-//orig store_reg \t , fpu=1
-//orig #define t t + 1
-//orig .endr
-
- mf_fpcr f0 // original
-
- SAVE_FPR(f0,CNS_Q_FPR+0x00,r1)
- SAVE_FPR(f1,CNS_Q_FPR+0x08,r1)
- SAVE_FPR(f2,CNS_Q_FPR+0x10,r1)
- SAVE_FPR(f3,CNS_Q_FPR+0x18,r1)
- SAVE_FPR(f4,CNS_Q_FPR+0x20,r1)
- SAVE_FPR(f5,CNS_Q_FPR+0x28,r1)
- SAVE_FPR(f6,CNS_Q_FPR+0x30,r1)
- SAVE_FPR(f7,CNS_Q_FPR+0x38,r1)
- SAVE_FPR(f8,CNS_Q_FPR+0x40,r1)
- SAVE_FPR(f9,CNS_Q_FPR+0x48,r1)
- SAVE_FPR(f10,CNS_Q_FPR+0x50,r1)
- SAVE_FPR(f11,CNS_Q_FPR+0x58,r1)
- SAVE_FPR(f12,CNS_Q_FPR+0x60,r1)
- SAVE_FPR(f13,CNS_Q_FPR+0x68,r1)
- SAVE_FPR(f14,CNS_Q_FPR+0x70,r1)
- SAVE_FPR(f15,CNS_Q_FPR+0x78,r1)
- SAVE_FPR(f16,CNS_Q_FPR+0x80,r1)
- SAVE_FPR(f17,CNS_Q_FPR+0x88,r1)
- SAVE_FPR(f18,CNS_Q_FPR+0x90,r1)
- SAVE_FPR(f19,CNS_Q_FPR+0x98,r1)
- SAVE_FPR(f20,CNS_Q_FPR+0xA0,r1)
- SAVE_FPR(f21,CNS_Q_FPR+0xA8,r1)
- SAVE_FPR(f22,CNS_Q_FPR+0xB0,r1)
- SAVE_FPR(f23,CNS_Q_FPR+0xB8,r1)
- SAVE_FPR(f24,CNS_Q_FPR+0xC0,r1)
- SAVE_FPR(f25,CNS_Q_FPR+0xC8,r1)
- SAVE_FPR(f26,CNS_Q_FPR+0xD0,r1)
- SAVE_FPR(f27,CNS_Q_FPR+0xD8,r1)
- SAVE_FPR(f28,CNS_Q_FPR+0xE0,r1)
- SAVE_FPR(f29,CNS_Q_FPR+0xE8,r1)
- SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1)
- SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1)
-
-//orig //switch impure offset from gpr to ipr---
-//orig unfix_impure_gpr r1
-//orig fix_impure_ipr r1
-//orig store_reg1 fpcsr, f0, r1, fpcsr=1
-
- SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach// pb
- lda r1, -0x200(r1) // Restore the impure base address
-
-//orig // and back to gpr ---
-//orig unfix_impure_ipr r1
-//orig fix_impure_gpr r1
-
-//orig lda r0, cns_mchksize(r31) // get size of mchk area
-//orig store_reg1 mchkflag, r0, r1, ipr=1
-//orig mb
-
- lda r1, CNS_Q_IPR(r1) // Point to base of IPR area again
- // save this using the IPR base (it is closer) not the GRP base as they used...pb
- lda r0, MACHINE_CHECK_SIZE(r31) // get size of mchk area
- SAVE_SHADOW(r0,CNS_Q_MCHK,r1);
- mb
-
-//orig or r31, 1, r0 // get a one
-//orig store_reg1 flag, r0, r1, ipr=1 // set dump area flag
-//orig mb
-
- lda r1, -CNS_Q_IPR(r1) // back to the base
- lda r1, 0x200(r1) // Point to center of CPU segment
- or r31, 1, r0 // get a one
- SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag
- mb
-
-//orig // restore impure area base
-//orig unfix_impure_gpr r1
- lda r1, -0x200(r1) // Point to center of CPU segment
-
- mtpr r31, dtb_ia // clear the dtb //orig
- mtpr r31, itb_ia // clear the itb //orig
-
-//orig pvc_jsr savsta, bsr=1, dest=1
- ret r31, (r3) // and back we go
-#endif
-
-
-#if remove_restore_state == 0
-
-
-// .sbttl "PAL_RESTORE_STATE"
-//+
-//
-// Pal_restore_state
-//
-//
-// register usage:
-// r1 = addr of impure area
-// r3 = return_address
-// all other regs are scratchable, as they are about to
-// be reloaded from ram.
-//
-// Function:
-// All chip state restored, all SRs, FRs, PTs, IPRs
-// *** except R1, R3, PT0, PT4, PT5 ***
-//
-//-
- ALIGN_BLOCK
-pal_restore_state:
-
-//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so.
-
-//orig // map the console io area virtually
-//orig mtpr r31, dtb_ia // clear the dtb
-//orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r1, dtb_tag // write TB tag
-//orig
-
- mtpr r31, dtbIa // Clear all DTB entries
- srl r1, va_s_off, r0 // Clean off byte-within-page offset
- sll r0, pte_v_pfn, r0 // Shift to form PFN
- lda r0, pte_m_prot(r0) // Set all read/write enable bits
- mtpr r0, dtbPte // Load the PTE and set valid
- mtpr r1, dtbTag // Write the PTE and tag into the DTB
-
-
-//orig // map the next page too, in case impure area crosses page boundary
-//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
-//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r4, dtb_tag // write TB tag - no virtual mbox instruction for 3 cycles
-
- lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page
- srl r4, va_s_off, r0 // Clean off byte-within-page offset
- sll r0, pte_v_pfn, r0 // Shift to form PFN
- lda r0, pte_m_prot(r0) // Set all read/write enable bits
- mtpr r0, dtbPte // Load the PTE and set valid
- mtpr r4, dtbTag // Write the PTE and tag into the DTB
-
-//orig // save all floating regs
-//orig mfpr r0, icsr // get icsr
-//orig// assume ICSR_V_SDE gt <ICSR_V_FPE> // assertion checker
-//orig or r31, <<1@<ICSR_V_SDE-ICSR_V_FPE>> ! 1>, r2 // set SDE and FPE
-//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot
-//orig or r2, r0, r0 // set FEN on
-//orig mtpr r0, icsr // write to icsr, enabling FEN and SDE. 3 bubbles to floating instr.
-
- mfpr r0, icsr // Get current ICSR
- bis zero, 1, r2 // Get a '1'
- or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2
- sll r2, icsr_v_fpe, r2 // Shift bits into position
- bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE>
- mtpr r0, icsr // Update the chip
-
- mfpr r31, pt0 // FPE bubble cycle 1 //orig
- mfpr r31, pt0 // FPE bubble cycle 2 //orig
- mfpr r31, pt0 // FPE bubble cycle 3 //orig
-
-//orig fix_impure_ipr r1
-//orig restore_reg1 fpcsr, f0, r1, fpcsr=1
-//orig mt_fpcr f0
-//orig
-//orig unfix_impure_ipr r1
-//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access
-//orig
-//orig // restore all floating regs
-//orig#define t 0
-//orig .repeat 32
-//orig restore_reg \t , fpu=1
-//orig#define t t + 1
-//orig .endr
-
- lda r1, 200(r1) // Point to base of IPR area again
- RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb
- mt_fpcr f0 // original
-
- lda r1, 0x200(r1) // point to center of CPU segment
- RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1)
- RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1)
- RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1)
- RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1)
- RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1)
- RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1)
- RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1)
- RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1)
- RESTORE_FPR(f8,CNS_Q_FPR+0x40,r1)
- RESTORE_FPR(f9,CNS_Q_FPR+0x48,r1)
- RESTORE_FPR(f10,CNS_Q_FPR+0x50,r1)
- RESTORE_FPR(f11,CNS_Q_FPR+0x58,r1)
- RESTORE_FPR(f12,CNS_Q_FPR+0x60,r1)
- RESTORE_FPR(f13,CNS_Q_FPR+0x68,r1)
- RESTORE_FPR(f14,CNS_Q_FPR+0x70,r1)
- RESTORE_FPR(f15,CNS_Q_FPR+0x78,r1)
- RESTORE_FPR(f16,CNS_Q_FPR+0x80,r1)
- RESTORE_FPR(f17,CNS_Q_FPR+0x88,r1)
- RESTORE_FPR(f18,CNS_Q_FPR+0x90,r1)
- RESTORE_FPR(f19,CNS_Q_FPR+0x98,r1)
- RESTORE_FPR(f20,CNS_Q_FPR+0xA0,r1)
- RESTORE_FPR(f21,CNS_Q_FPR+0xA8,r1)
- RESTORE_FPR(f22,CNS_Q_FPR+0xB0,r1)
- RESTORE_FPR(f23,CNS_Q_FPR+0xB8,r1)
- RESTORE_FPR(f24,CNS_Q_FPR+0xC0,r1)
- RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1)
- RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1)
- RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1)
- RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1)
- RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1)
- RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1)
- RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1)
-
-//orig // switch impure pointer from gpr to ipr area --
-//orig unfix_impure_gpr r1
-//orig fix_impure_ipr r1
-//orig
-//orig // restore all pal regs
-//orig#define t 1
-//orig .repeat 23
-//orig restore_reg \t , pal=1
-//orig#define t t + 1
-//orig .endr
-
- lda r1, -0x200(r1) // Restore base address of impure area.
- lda r1, CNS_Q_IPR(r1) // Point to base of IPR area.
- RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle
- RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1)
- RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1)
- RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1)
- RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1)
- RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1)
- RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1)
- RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1)
- RESTORE_IPR(pt8,CNS_Q_PT+0x40,r1)
- RESTORE_IPR(pt9,CNS_Q_PT+0x48,r1)
- RESTORE_IPR(pt10,CNS_Q_PT+0x50,r1)
- RESTORE_IPR(pt11,CNS_Q_PT+0x58,r1)
- RESTORE_IPR(pt12,CNS_Q_PT+0x60,r1)
- RESTORE_IPR(pt13,CNS_Q_PT+0x68,r1)
- RESTORE_IPR(pt14,CNS_Q_PT+0x70,r1)
- RESTORE_IPR(pt15,CNS_Q_PT+0x78,r1)
- RESTORE_IPR(pt16,CNS_Q_PT+0x80,r1)
- RESTORE_IPR(pt17,CNS_Q_PT+0x88,r1)
- RESTORE_IPR(pt18,CNS_Q_PT+0x90,r1)
- RESTORE_IPR(pt19,CNS_Q_PT+0x98,r1)
- RESTORE_IPR(pt20,CNS_Q_PT+0xA0,r1)
- RESTORE_IPR(pt21,CNS_Q_PT+0xA8,r1)
- RESTORE_IPR(pt22,CNS_Q_PT+0xB0,r1)
- RESTORE_IPR(pt23,CNS_Q_PT+0xB8,r1)
-
-
-//orig restore_reg exc_addr, ipr=1 // restore ipr
-//orig restore_reg pal_base, ipr=1 // restore ipr
-//orig restore_reg ipl, ipr=1 // restore ipr
-//orig restore_reg ps, ipr=1 // restore ipr
-//orig mtpr r0, dtb_cm // set current mode in mbox too
-//orig restore_reg itb_asn, ipr=1
-//orig srl r0, itb_asn_v_asn, r0
-//orig sll r0, dtb_asn_v_asn, r0
-//orig mtpr r0, dtb_asn // set ASN in Mbox too
-//orig restore_reg ivptbr, ipr=1
-//orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr
-//orig restore_reg mcsr, ipr=1
-//orig restore_reg aster, ipr=1
-//orig restore_reg astrr, ipr=1
-//orig restore_reg sirr, ipr=1
-//orig restore_reg maf_mode, ipr=1 // no mbox instruction for 3 cycles
-//orig mfpr r31, pt0 // (may issue with mt maf_mode)
-//orig mfpr r31, pt0 // bubble cycle 1
-//orig mfpr r31, pt0 // bubble cycle 2
-//orig mfpr r31, pt0 // bubble cycle 3
-//orig mfpr r31, pt0 // (may issue with following ld)
-
- // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag)
- RESTORE_IPR(excAddr,CNS_Q_EXC_ADDR,r1)
- RESTORE_IPR(palBase,CNS_Q_PAL_BASE,r1)
- RESTORE_IPR(ipl,CNS_Q_IPL,r1)
- RESTORE_IPR(ips,CNS_Q_IPS,r1)
- mtpr r0, dtbCm // Set Mbox current mode too.
- RESTORE_IPR(itbAsn,CNS_Q_ITB_ASN,r1)
- srl r0, 4, r0
- sll r0, 57, r0
- mtpr r0, dtbAsn // Set Mbox ASN too
- RESTORE_IPR(iVptBr,CNS_Q_IVPTBR,r1)
- mtpr r0, mVptBr // Set Mbox VptBr too
- RESTORE_IPR(mcsr,CNS_Q_MCSR,r1)
- RESTORE_IPR(aster,CNS_Q_ASTER,r1)
- RESTORE_IPR(astrr,CNS_Q_ASTRR,r1)
- RESTORE_IPR(sirr,CNS_Q_SIRR,r1)
- RESTORE_IPR(mafMode,CNS_Q_MAF_MODE,r1)
- STALL
- STALL
- STALL
- STALL
- STALL
-
-
- // restore all integer shadow regs
-//orig#define t 8
-//orig .repeat 7
-//orig restore_reg \t, shadow=1
-//orig#define t t + 1
-//orig .endr
-//orig restore_reg 25, shadow=1
-//orig restore_reg dc_mode, ipr=1 // no mbox instructions for 4 cycles
-
- RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code
- RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1)
- RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1)
- RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1)
- RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1)
- RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1)
- RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1)
- RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1)
- RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1)
-
- //
- // Get out of shadow mode
- //
-
- mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) //orig
- mfpr r31, pt0 // "" //orig
- mfpr r0, icsr // Get icsr //orig
-//orig ldah r2, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
- ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location //orig
- bic r0, r2, r2 // ICSR with SDE clear //orig
- mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles //orig
-
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
-
-//orig // switch impure pointer from ipr to gpr area --
-//orig unfix_impure_ipr r1
-//orig fix_impure_gpr r1
-//orig // restore all integer regs
-//orig#define t 4
-//orig .repeat 28
-//orig restore_reg \t
-//orig#define t t + 1
-//orig .endr
-
-// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ...
-
- lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area
- lda r1, 0x200(r1) // Point to center of CPU segment
-
- RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1)
- RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1)
- RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1)
- RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1)
- RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1)
- RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1)
- RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1)
- RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1)
- RESTORE_GPR(r12,CNS_Q_GPR+0x60,r1)
- RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1)
- RESTORE_GPR(r14,CNS_Q_GPR+0x70,r1)
- RESTORE_GPR(r15,CNS_Q_GPR+0x78,r1)
- RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1)
- RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1)
- RESTORE_GPR(r18,CNS_Q_GPR+0x90,r1)
- RESTORE_GPR(r19,CNS_Q_GPR+0x98,r1)
- RESTORE_GPR(r20,CNS_Q_GPR+0xA0,r1)
- RESTORE_GPR(r21,CNS_Q_GPR+0xA8,r1)
- RESTORE_GPR(r22,CNS_Q_GPR+0xB0,r1)
- RESTORE_GPR(r23,CNS_Q_GPR+0xB8,r1)
- RESTORE_GPR(r24,CNS_Q_GPR+0xC0,r1)
- RESTORE_GPR(r25,CNS_Q_GPR+0xC8,r1)
- RESTORE_GPR(r26,CNS_Q_GPR+0xD0,r1)
- RESTORE_GPR(r27,CNS_Q_GPR+0xD8,r1)
- RESTORE_GPR(r28,CNS_Q_GPR+0xE0,r1)
- RESTORE_GPR(r29,CNS_Q_GPR+0xE8,r1)
- RESTORE_GPR(r30,CNS_Q_GPR+0xF0,r1)
- RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1)
-
-//orig // switch impure pointer from gpr to ipr area --
-//orig unfix_impure_gpr r1
-//orig fix_impure_ipr r1
-//orig restore_reg icsr, ipr=1 // restore original icsr- 4 bubbles to hw_rei
-
- lda t0, -0x200(t0) // Restore base address of impure area.
- lda t0, CNS_Q_IPR(t0) // Point to base of IPR area again.
- RESTORE_IPR(icsr,CNS_Q_ICSR,r1)
-
-//orig // and back again --
-//orig unfix_impure_ipr r1
-//orig fix_impure_gpr r1
-//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag
-//orig mb
-
- lda t0, -CNS_Q_IPR(t0) // Back to base of impure area again,
- lda t0, 0x200(t0) // and back to center of CPU segment
- SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag
- mb
-
-//orig // and back we go
-//orig// restore_reg 3
-//orig restore_reg 2
-//orig// restore_reg 1
-//orig restore_reg 0
-//orig // restore impure area base
-//orig unfix_impure_gpr r1
-
- RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1)
- RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1)
- lda r1, -0x200(r1) // Restore impure base address
-
- mfpr r31, pt0 // stall for ldqp above //orig
-
- mtpr r31, dtb_ia // clear the tb //orig
- mtpr r31, itb_ia // clear the itb //orig
-
-//orig pvc_jsr rststa, bsr=1, dest=1
- ret r31, (r3) // back we go //orig
-#endif
-
-
-//+
-// pal_pal_bug_check -- code has found a bugcheck situation.
-// Set things up and join common machine check flow.
-//
-// Input:
-// r14 - exc_addr
-//
-// On exit:
-// pt0 - saved r0
-// pt1 - saved r1
-// pt4 - saved r4
-// pt5 - saved r5
-// pt6 - saved r6
-// pt10 - saved exc_addr
-// pt_misc<47:32> - mchk code
-// pt_misc<31:16> - scb vector
-// r14 - base of Cbox IPRs in IO space
-// MCES<mchk> is set
-//-
-
- ALIGN_BLOCK
- .globl pal_pal_bug_check_from_int
-pal_pal_bug_check_from_int:
- DEBUGSTORE(0x79)
-//simos DEBUG_EXC_ADDR()
- DEBUGSTORE(0x20)
-//simos bsr r25, put_hex
- lda r25, mchk_c_bugcheck(r31)
- addq r25, 1, r25 // set flag indicating we came from interrupt and stack is already pushed
- br r31, pal_pal_mchk
- nop
-
-pal_pal_bug_check:
- lda r25, mchk_c_bugcheck(r31)
-
-pal_pal_mchk:
- sll r25, 32, r25 // Move mchk code to position
-
- mtpr r14, pt10 // Stash exc_addr
- mtpr r14, exc_addr
-
- mfpr r12, pt_misc // Get MCES and scratch
- zap r12, 0x3c, r12
-
- or r12, r25, r12 // Combine mchk code
- lda r25, scb_v_procmchk(r31) // Get SCB vector
-
- sll r25, 16, r25 // Move SCBv to position
- or r12, r25, r25 // Combine SCBv
-
- mtpr r0, pt0 // Stash for scratch
- bis r25, mces_m_mchk, r25 // Set MCES<MCHK> bit
-
- mtpr r25, pt_misc // Save mchk code!scbv!whami!mces
- ldah r14, 0xfff0(r31)
-
- mtpr r1, pt1 // Stash for scratch
- zap r14, 0xE0, r14 // Get Cbox IPR base
-
- mtpr r4, pt4
- mtpr r5, pt5
-
- mtpr r6, pt6
- blbs r12, sys_double_machine_check // MCHK halt if double machine check
-
- br r31, sys_mchk_collect_iprs // Join common machine check flow
-
-// align_to_call_pal_section // Align to address of first call_pal entry point - 2000
-
-// .sbttl "HALT - PALcode for HALT instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// GO to console code
-//
-//-
-
- .text 1
-// . = 0x2000
- CALL_PAL_PRIV(PAL_HALT_ENTRY)
-call_pal_halt:
-#if rax_mode == 0
- mfpr r31, pt0 // Pad exc_addr read
- mfpr r31, pt0
-
- mfpr r12, exc_addr // get PC
- subq r12, 4, r12 // Point to the HALT
-
- mtpr r12, exc_addr
- mtpr r0, pt0
-
-//orig pvc_jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
- lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt
- br r31, sys_enter_console // enter the console
-
-#else // RAX mode
- mb
- mb
- mtpr r9, ev5__dtb_asn // no Dstream virtual ref for next 3 cycles.
- mtpr r9, ev5__itb_asn // E1. Update ITB ASN. No hw_rei for 5 cycles.
- mtpr r8, exc_addr // no HW_REI for 1 cycle.
- blbc r9, not_begin_case
- mtpr r31, ev5__dtb_ia // clear DTB. No Dstream virtual ref for 2 cycles.
- mtpr r31, ev5__itb_ia // clear ITB.
-
-not_begin_case:
- nop
- nop
-
- nop
- nop // pad mt itb_asn ->hw_rei_stall
-
- hw_rei_stall
-#endif
-
-// .sbttl "CFLUSH- PALcode for CFLUSH instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// R16 - contains the PFN of the page to be flushed
-//
-// Function:
-// Flush all Dstream caches of 1 entire page
-// The CFLUSH routine is in the system specific module.
-//
-//-
-
- CALL_PAL_PRIV(PAL_CFLUSH_ENTRY)
-Call_Pal_Cflush:
- br r31, sys_cflush
-
-// .sbttl "DRAINA - PALcode for DRAINA instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-// Implicit TRAPB performed by hardware.
-//
-// Function:
-// Stall instruction issue until all prior instructions are guaranteed to
-// complete without incurring aborts. For the EV5 implementation, this
-// means waiting until all pending DREADS are returned.
-//
-//-
-
- CALL_PAL_PRIV(PAL_DRAINA_ENTRY)
-Call_Pal_Draina:
- ldah r14, 0x100(r31) // Init counter. Value?
- nop
-
-DRAINA_LOOP:
- subq r14, 1, r14 // Decrement counter
- mfpr r13, ev5__maf_mode // Fetch status bit
-
- srl r13, maf_mode_v_dread_pending, r13
- ble r14, DRAINA_LOOP_TOO_LONG
-
- nop
- blbs r13, DRAINA_LOOP // Wait until all DREADS clear
-
- hw_rei
-
-DRAINA_LOOP_TOO_LONG:
- br r31, call_pal_halt
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_PRIV(0x0003)
-CallPal_OpcDec03:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0004)
-CallPal_OpcDec04:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0005)
-CallPal_OpcDec05:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0006)
-CallPal_OpcDec06:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0007)
-CallPal_OpcDec07:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0008)
-CallPal_OpcDec08:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "CSERVE- PALcode for CSERVE instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Various functions for private use of console software
-//
-// option selector in r0
-// arguments in r16....
-// The CSERVE routine is in the system specific module.
-//
-//-
-
- CALL_PAL_PRIV(PAL_CSERVE_ENTRY)
-Call_Pal_Cserve:
- br r31, sys_cserve
-
-// .sbttl "swppal - PALcode for swppal instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-// Vectored into via hardware PALcode instruction dispatch.
-// R16 contains the new PAL identifier
-// R17:R21 contain implementation-specific entry parameters
-//
-// R0 receives status:
-// 0 success (PAL was switched)
-// 1 unknown PAL variant
-// 2 known PAL variant, but PAL not loaded
-//
-//
-// Function:
-// Swap control to another PAL.
-//-
-
- CALL_PAL_PRIV(PAL_SWPPAL_ENTRY)
-Call_Pal_Swppal:
- cmpule r16, 255, r0 // see if a kibble was passed
- cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59)
-
- or r16, r31, r3 // set r3 incase this is a address
- blbc r0, swppal_cont // nope, try it as an address
-
- cmpeq r16, 2, r0 // is it our friend OSF?
- blbc r0, swppal_fail // nope, don't know this fellow
-
- br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF
-
-// .global osfpal_hw_entry_reset
-// .weak osfpal_hw_entry_reset
-// .long <osfpal_hw_entry_reset-pal_start>
-//orig halt // don't know how to get the address here - kludge ok, load pal at 0
- .long 0 // ?? hack upon hack...pb
-
-CALL_PAL_SWPPAL_10_: ldlp r3, 0(r2) // fetch target addr
-// ble r3, swppal_fail ; if OSF not linked in say not loaded.
- mfpr r2, pal_base // fetch pal base
-
- addq r2, r3, r3 // add pal base
- lda r2, 0x3FFF(r31) // get pal base checker mask
-
- and r3, r2, r2 // any funky bits set?
- cmpeq r2, 0, r0 //
-
- blbc r0, swppal_fail // return unknown if bad bit set.
- br r31, swppal_cont
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_PRIV(0x000B)
-CallPal_OpcDec0B:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x000C)
-CallPal_OpcDec0C:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "wripir- PALcode for wripir instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-// r16 = processor number to interrupt
-//
-// Function:
-// IPIR <- R16
-// Handled in system-specific code
-//
-// Exit:
-// interprocessor interrupt is recorded on the target processor
-// and is initiated when the proper enabling conditions are present.
-//-
-
- CALL_PAL_PRIV(PAL_WRIPIR_ENTRY)
-Call_Pal_Wrpir:
- br r31, sys_wripir
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_PRIV(0x000E)
-CallPal_OpcDec0E:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x000F)
-CallPal_OpcDec0F:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "rdmces- PALcode for rdmces instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// R0 <- ZEXT(MCES)
-//-
-
- CALL_PAL_PRIV(PAL_RDMCES_ENTRY)
-Call_Pal_Rdmces:
- mfpr r0, pt_mces // Read from PALtemp
- and r0, mces_m_all, r0 // Clear other bits
-
- hw_rei
-
-// .sbttl "wrmces- PALcode for wrmces instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK)
-// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE)
-// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE)
-// MCES<3> <- R16<3> (DPC)
-// MCES<4> <- R16<4> (DSC)
-//
-//-
-
- CALL_PAL_PRIV(PAL_WRMCES_ENTRY)
-Call_Pal_Wrmces:
- and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE
- mfpr r14, pt_mces // Get current value
-
- ornot r31, r13, r13 // Flip all the bits
- and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17
-
- and r14, r13, r1 // Update MCHK, SCE, PCE
- bic r1, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r1 // Clear old DPC, DSC
-
- or r1, r17, r1 // Update DPC and DSC
- mtpr r1, pt_mces // Write MCES back
-
-#if rawhide_system == 0
- nop // Pad to fix PT write->read restriction
-#else
- blbs r16, RAWHIDE_clear_mchk_lock // Clear logout from lock
-#endif
-
- nop
- hw_rei
-
-
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_PRIV(0x0012)
-CallPal_OpcDec12:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0013)
-CallPal_OpcDec13:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0014)
-CallPal_OpcDec14:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0015)
-CallPal_OpcDec15:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0016)
-CallPal_OpcDec16:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0017)
-CallPal_OpcDec17:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0018)
-CallPal_OpcDec18:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0019)
-CallPal_OpcDec19:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001A)
-CallPal_OpcDec1A:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001B)
-CallPal_OpcDec1B:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001C)
-CallPal_OpcDec1C:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001D)
-CallPal_OpcDec1D:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001E)
-CallPal_OpcDec1E:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001F)
-CallPal_OpcDec1F:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0020)
-CallPal_OpcDec20:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0021)
-CallPal_OpcDec21:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0022)
-CallPal_OpcDec22:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0023)
-CallPal_OpcDec23:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0024)
-CallPal_OpcDec24:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0025)
-CallPal_OpcDec25:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0026)
-CallPal_OpcDec26:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0027)
-CallPal_OpcDec27:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0028)
-CallPal_OpcDec28:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0029)
-CallPal_OpcDec29:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x002A)
-CallPal_OpcDec2A:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "wrfen - PALcode for wrfen instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// a0<0> -> ICSR<FPE>
-// Store new FEN in PCB
-// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) are UNPREDICTABLE
-//
-// Issue: What about pending FP loads when FEN goes from on->off????
-//-
-
- CALL_PAL_PRIV(PAL_WRFEN_ENTRY)
-Call_Pal_Wrfen:
- or r31, 1, r13 // Get a one
- mfpr r1, ev5__icsr // Get current FPE
-
- sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0
- and r16, 1, r16 // clean new fen
-
- sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position
- bic r1, r13, r1 // zero icsr<fpe>
-
- or r1, r12, r1 // Or new FEN into ICSR
- mfpr r12, pt_pcbb // Get PCBB - E1
-
- mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI
- stlp r16, osfpcb_q_fen(r12) // Store FEN in PCB.
-
- mfpr r31, pt0 // Pad ICSR<FPE> write.
- mfpr r31, pt0
-
- mfpr r31, pt0
-// pvc_violate 225 // cuz PVC can't distinguish which bits changed
- hw_rei
-
-
- CALL_PAL_PRIV(0x002C)
-CallPal_OpcDec2C:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "wrvptpr - PALcode for wrvptpr instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// vptptr <- a0 (r16)
-//-
-
- CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY)
-Call_Pal_Wrvptptr:
- mtpr r16, ev5__mvptbr // Load Mbox copy
- mtpr r16, ev5__ivptbr // Load Ibox copy
- nop // Pad IPR write
- nop
- hw_rei
-
- CALL_PAL_PRIV(0x002E)
-CallPal_OpcDec2E:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x002F)
-CallPal_OpcDec2F:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "swpctx- PALcode for swpctx instruction"
-
-//+
-//
-// Entry:
-// hardware dispatch via callPal instruction
-// R16 -> new pcb
-//
-// Function:
-// dynamic state moved to old pcb
-// new state loaded from new pcb
-// pcbb pointer set
-// old pcbb returned in R0
-//
-// Note: need to add perf monitor stuff
-//-
-
- CALL_PAL_PRIV(PAL_SWPCTX_ENTRY)
-Call_Pal_Swpctx:
- rpcc r13 // get cyccounter
- mfpr r0, pt_pcbb // get pcbb
-
- ldqp r22, osfpcb_q_fen(r16) // get new fen/pme
- ldqp r23, osfpcb_l_cc(r16) // get new asn
-
- srl r13, 32, r25 // move offset
- mfpr r24, pt_usp // get usp
-
- stqp r30, osfpcb_q_ksp(r0) // store old ksp
-// pvc_violate 379 // stqp can't trap except replay. only problem if mf same ipr in same shadow.
- mtpr r16, pt_pcbb // set new pcbb
-
- stqp r24, osfpcb_q_usp(r0) // store usp
- addl r13, r25, r25 // merge for new time
-
- stlp r25, osfpcb_l_cc(r0) // save time
- ldah r24, (1<<(icsr_v_fpe-16))(r31)
-
- and r22, 1, r12 // isolate fen
- mfpr r25, icsr // get current icsr
-
- ev5_pass2 lda r24, (1<<icsr_v_pmp)(r24)
- br r31, swpctx_cont
-
-// .sbttl "wrval - PALcode for wrval instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// sysvalue <- a0 (r16)
-//-
-
- CALL_PAL_PRIV(PAL_WRVAL_ENTRY)
-Call_Pal_Wrval:
- nop
- mtpr r16, pt_sysval // Pad paltemp write
- nop
- nop
- hw_rei
-
-
-// .sbttl "rdval - PALcode for rdval instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- sysvalue
-//-
-
- CALL_PAL_PRIV(PAL_RDVAL_ENTRY)
-Call_Pal_Rdval:
- nop
- mfpr r0, pt_sysval
- nop
- hw_rei
-
-// .sbttl "tbi - PALcode for tbi instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// TB invalidate
-// r16/a0 = TBI type
-// r17/a1 = Va for TBISx instructions
-//-
-
- CALL_PAL_PRIV(PAL_TBI_ENTRY)
-Call_Pal_Tbi:
- addq r16, 2, r16 // change range to 0-2
- br r23, CALL_PAL_tbi_10_ // get our address
-
-CALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range
- lda r23, tbi_tbl-CALL_PAL_tbi_10_(r23) // set base to start of table
- sll r16, 4, r16 // * 16
- blbc r22, CALL_PAL_tbi_30_ // go rei, if not
-
- addq r23, r16, r23 // addr of our code
-//orig pvc_jsr tbi
- jmp r31, (r23) // and go do it
-
-CALL_PAL_tbi_30_:
- hw_rei
- nop
-
-// .sbttl "wrent - PALcode for wrent instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Update ent* in paltemps
-// r16/a0 = Address of entry routine
-// r17/a1 = Entry Number 0..5
-//
-// r22, r23 trashed
-//-
-
- CALL_PAL_PRIV(PAL_WRENT_ENTRY)
-Call_Pal_Wrent:
- cmpult r17, 6, r22 // see if in range
- br r23, CALL_PAL_wrent_10_ // get our address
-
-CALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc
- blbc r22, CALL_PAL_wrent_30_ // go rei, if not in range
-
- lda r23, wrent_tbl-CALL_PAL_wrent_10_(r23) // set base to start of table
- sll r17, 4, r17 // *16
-
- addq r17, r23, r23 // Get address in table
-//orig pvc_jsr wrent
- jmp r31, (r23) // and go do it
-
-CALL_PAL_wrent_30_:
- hw_rei // out of range, just return
-
-// .sbttl "swpipl - PALcode for swpipl instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- PS<IPL>
-// PS<IPL> <- a0<2:0> (r16)
-//
-// t8 (r22) is scratch
-//-
-
- CALL_PAL_PRIV(PAL_SWPIPL_ENTRY)
-Call_Pal_Swpipl:
- and r16, osfps_m_ipl, r16 // clean New ipl
- mfpr r22, pt_intmask // get int mask
-
- extbl r22, r16, r22 // get mask for this ipl
- bis r11, r31, r0 // return old ipl
-
- bis r16, r31, r11 // set new ps
- mtpr r22, ev5__ipl // set new mask
-
- mfpr r31, pt0 // pad ipl write
- mfpr r31, pt0 // pad ipl write
-
- hw_rei // back
-
-// .sbttl "rdps - PALcode for rdps instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- ps
-//-
-
- CALL_PAL_PRIV(PAL_RDPS_ENTRY)
-Call_Pal_Rdps:
- bis r11, r31, r0 // Fetch PALshadow PS
- nop // Must be 2 cycles long
- hw_rei
-
-// .sbttl "wrkgp - PALcode for wrkgp instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// kgp <- a0 (r16)
-//-
-
- CALL_PAL_PRIV(PAL_WRKGP_ENTRY)
-Call_Pal_Wrkgp:
- nop
- mtpr r16, pt_kgp
- nop // Pad for pt write->read restriction
- nop
- hw_rei
-
-// .sbttl "wrusp - PALcode for wrusp instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// usp <- a0 (r16)
-//-
-
- CALL_PAL_PRIV(PAL_WRUSP_ENTRY)
-Call_Pal_Wrusp:
- nop
- mtpr r16, pt_usp
- nop // Pad possible pt write->read restriction
- nop
- hw_rei
-
-// .sbttl "wrperfmon - PALcode for wrperfmon instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-//
-// Function:
-// Various control functions for the onchip performance counters
-//
-// option selector in r16
-// option argument in r17
-// returned status in r0
-//
-//
-// r16 = 0 Disable performance monitoring for one or more cpu's
-// r17 = 0 disable no counters
-// r17 = bitmask disable counters specified in bit mask (1=disable)
-//
-// r16 = 1 Enable performance monitoring for one or more cpu's
-// r17 = 0 enable no counters
-// r17 = bitmask enable counters specified in bit mask (1=enable)
-//
-// r16 = 2 Mux select for one or more cpu's
-// r17 = Mux selection (cpu specific)
-// <24:19> bc_ctl<pm_mux_sel> field (see spec)
-// <31>,<7:4>,<3:0> pmctr <sel0>,<sel1>,<sel2> fields (see spec)
-//
-// r16 = 3 Options
-// r17 = (cpu specific)
-// <0> = 0 log all processes
-// <0> = 1 log only selected processes
-// <30,9,8> mode select - ku,kp,kk
-//
-// r16 = 4 Interrupt frequency select
-// r17 = (cpu specific) indicates interrupt frequencies desired for each
-// counter, with "zero interrupts" being an option
-// frequency info in r17 bits as defined by PMCTR_CTL<FRQx> below
-//
-// r16 = 5 Read Counters
-// r17 = na
-// r0 = value (same format as ev5 pmctr)
-// <0> = 0 Read failed
-// <0> = 1 Read succeeded
-//
-// r16 = 6 Write Counters
-// r17 = value (same format as ev5 pmctr; all counters written simultaneously)
-//
-// r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0
-// r17 = 0 enable no counters
-// r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear)
-//
-//=============================================================================
-//Assumptions:
-//PMCTR_CTL:
-//
-// <15:14> CTL0 -- encoded frequency select and enable - CTR0
-// <13:12> CTL1 -- " - CTR1
-// <11:10> CTL2 -- " - CTR2
-//
-// <9:8> FRQ0 -- frequency select for CTR0 (no enable info)
-// <7:6> FRQ1 -- frequency select for CTR1
-// <5:4> FRQ2 -- frequency select for CTR2
-//
-// <0> all vs. select processes (0=all,1=select)
-//
-// where
-// FRQx<1:0>
-// 0 1 disable interrupt
-// 1 0 frequency = 65536 (16384 for ctr2)
-// 1 1 frequency = 256
-// note: FRQx<1:0> = 00 will keep counters from ever being enabled.
-//
-//=============================================================================
-//
- CALL_PAL_PRIV(0x0039)
-// unsupported in Hudson code .. pboyle Nov/95
-CALL_PAL_Wrperfmon:
-#if perfmon_debug == 0
- // "real" performance monitoring code
- cmpeq r16, 1, r0 // check for enable
- bne r0, perfmon_en // br if requested to enable
-
- cmpeq r16, 2, r0 // check for mux ctl
- bne r0, perfmon_muxctl // br if request to set mux controls
-
- cmpeq r16, 3, r0 // check for options
- bne r0, perfmon_ctl // br if request to set options
-
- cmpeq r16, 4, r0 // check for interrupt frequency select
- bne r0, perfmon_freq // br if request to change frequency select
-
- cmpeq r16, 5, r0 // check for counter read request
- bne r0, perfmon_rd // br if request to read counters
-
- cmpeq r16, 6, r0 // check for counter write request
- bne r0, perfmon_wr // br if request to write counters
-
- cmpeq r16, 7, r0 // check for counter clear/enable request
- bne r0, perfmon_enclr // br if request to clear/enable counters
-
- beq r16, perfmon_dis // br if requested to disable (r16=0)
- br r31, perfmon_unknown // br if unknown request
-#else
-
- br r31, pal_perfmon_debug
-#endif
-
-// .sbttl "rdusp - PALcode for rdusp instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- usp
-//-
-
- CALL_PAL_PRIV(PAL_RDUSP_ENTRY)
-Call_Pal_Rdusp:
- nop
- mfpr r0, pt_usp
- hw_rei
-
-
- CALL_PAL_PRIV(0x003B)
-CallPal_OpcDec3B:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "whami - PALcode for whami instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- whami
-//-
- CALL_PAL_PRIV(PAL_WHAMI_ENTRY)
-Call_Pal_Whami:
- nop
- mfpr r0, pt_whami // Get Whami
- extbl r0, 1, r0 // Isolate just whami bits
- hw_rei
-
-// .sbttl "retsys - PALcode for retsys instruction"
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-// 00(sp) contains return pc
-// 08(sp) contains r29
-//
-// Function:
-// Return from system call.
-// mode switched from kern to user.
-// stacks swapped, ugp, upc restored.
-// r23, r25 junked
-//-
-
- CALL_PAL_PRIV(PAL_RETSYS_ENTRY)
-Call_Pal_Retsys:
- lda r25, osfsf_c_size(sp) // pop stack
- bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr
-
- mfpr r14, exc_addr // save exc_addr in case of fault
- ldq r23, osfsf_pc(sp) // get pc
-
- ldq r29, osfsf_gp(sp) // get gp
- stl_c r31, -4(sp) // clear lock_flag
-
- lda r11, 1<<osfps_v_mode(r31)// new PS:mode=user
- mfpr r30, pt_usp // get users stack
-
- bic r23, 3, r23 // clean return pc
- mtpr r31, ev5__ipl // zero ibox IPL - 2 bubbles to hw_rei
-
- mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
- mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
-
- mtpr r23, exc_addr // set return address - 1 bubble to hw_rei
- mtpr r25, pt_ksp // save kern stack
-
- rc r31 // clear inter_flag
-// pvc_violate 248 // possible hidden mt->mf pt violation ok in callpal
- hw_rei_spe // and back
-
-
- CALL_PAL_PRIV(0x003E)
-CallPal_OpcDec3E:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "rti - PALcode for rti instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// 00(sp) -> ps
-// 08(sp) -> pc
-// 16(sp) -> r29 (gp)
-// 24(sp) -> r16 (a0)
-// 32(sp) -> r17 (a1)
-// 40(sp) -> r18 (a3)
-//-
-
- CALL_PAL_PRIV(PAL_RTI_ENTRY)
-#ifdef SIMOS
- /* called once by platform_tlaser */
- .globl Call_Pal_Rti
-#endif
-Call_Pal_Rti:
- lda r25, osfsf_c_size(sp) // get updated sp
- bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr
-
- mfpr r14, exc_addr // save PC in case of fault
- rc r31 // clear intr_flag
-
- ldq r12, -6*8(r25) // get ps
- ldq r13, -5*8(r25) // pc
-
- ldq r18, -1*8(r25) // a2
- ldq r17, -2*8(r25) // a1
-
- ldq r16, -3*8(r25) // a0
- ldq r29, -4*8(r25) // gp
-
- bic r13, 3, r13 // clean return pc
- stl_c r31, -4(r25) // clear lock_flag
-
- and r12, osfps_m_mode, r11 // get mode
- mtpr r13, exc_addr // set return address
-
- beq r11, rti_to_kern // br if rti to Kern
- br r31, rti_to_user // out of call_pal space
-
-
-// .sbttl "Start the Unprivileged CALL_PAL Entry Points"
-// .sbttl "bpt- PALcode for bpt instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-//
- .text 1
-// . = 0x3000
- CALL_PAL_UNPRIV(PAL_BPT_ENTRY)
-Call_Pal_Bpt:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, CALL_PAL_bpt_10_ // no stack swap needed if cm=kern
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-CALL_PAL_bpt_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_bpt, r16 // set a0
-
- stq r17, osfsf_a1(sp) // a1
- br r31, bpt_bchk_common // out of call_pal space
-
-
-// .sbttl "bugchk- PALcode for bugchk instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-//
- CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY)
-Call_Pal_Bugchk:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, CALL_PAL_bugchk_10_ // no stack swap needed if cm=kern
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-CALL_PAL_bugchk_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_bugchk, r16 // set a0
-
- stq r17, osfsf_a1(sp) // a1
- br r31, bpt_bchk_common // out of call_pal space
-
-
- CALL_PAL_UNPRIV(0x0082)
-CallPal_OpcDec82:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "callsys - PALcode for callsys instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Switch mode to kernel and build a callsys stack frame.
-// sp = ksp
-// gp = kgp
-// t8 - t10 (r22-r24) trashed
-//
-//-
-//
- CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY)
-Call_Pal_Callsys:
-
- and r11, osfps_m_mode, r24 // get mode
- mfpr r22, pt_ksp // get ksp
-
- beq r24, sys_from_kern // sysCall from kern is not allowed
- mfpr r12, pt_entsys // get address of callSys routine
-
-//+
-// from here on we know we are in user going to Kern
-//-
- mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
- mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
-
- bis r31, r31, r11 // PS=0 (mode=kern)
- mfpr r23, exc_addr // get pc
-
- mtpr r30, pt_usp // save usp
- lda sp, 0-osfsf_c_size(r22)// set new sp
-
- stq r29, osfsf_gp(sp) // save user gp/r29
- stq r24, osfsf_ps(sp) // save ps
-
- stq r23, osfsf_pc(sp) // save pc
- mtpr r12, exc_addr // set address
- // 1 cycle to hw_rei
-
- mfpr r29, pt_kgp // get the kern gp/r29
-
- hw_rei_spe // and off we go!
-
-
- CALL_PAL_UNPRIV(0x0084)
-CallPal_OpcDec84:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0085)
-CallPal_OpcDec85:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "imb - PALcode for imb instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Flush the writebuffer and flush the Icache
-//
-//-
-//
- CALL_PAL_UNPRIV(PAL_IMB_ENTRY)
-Call_Pal_Imb:
- mb // Clear the writebuffer
- mfpr r31, ev5__mcsr // Sync with clear
- nop
- nop
- br r31, pal_ic_flush // Flush Icache
-
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_UNPRIV(0x0087)
-CallPal_OpcDec87:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0088)
-CallPal_OpcDec88:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0089)
-CallPal_OpcDec89:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008A)
-CallPal_OpcDec8A:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008B)
-CallPal_OpcDec8B:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008C)
-CallPal_OpcDec8C:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008D)
-CallPal_OpcDec8D:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008E)
-CallPal_OpcDec8E:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008F)
-CallPal_OpcDec8F:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0090)
-CallPal_OpcDec90:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0091)
-CallPal_OpcDec91:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0092)
-CallPal_OpcDec92:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0093)
-CallPal_OpcDec93:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0094)
-CallPal_OpcDec94:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0095)
-CallPal_OpcDec95:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0096)
-CallPal_OpcDec96:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0097)
-CallPal_OpcDec97:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0098)
-CallPal_OpcDec98:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0099)
-CallPal_OpcDec99:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x009A)
-CallPal_OpcDec9A:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x009B)
-CallPal_OpcDec9B:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x009C)
-CallPal_OpcDec9C:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x009D)
-CallPal_OpcDec9D:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "rdunique - PALcode for rdunique instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- unique
-//
-//-
-//
- CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY)
-CALL_PALrdunique_:
- mfpr r0, pt_pcbb // get pcb pointer
- ldqp r0, osfpcb_q_unique(r0) // get new value
-
- hw_rei
-
-// .sbttl "wrunique - PALcode for wrunique instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// unique <- a0 (r16)
-//
-//-
-//
-CALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY)
-CALL_PAL_Wrunique:
- nop
- mfpr r12, pt_pcbb // get pcb pointer
- stqp r16, osfpcb_q_unique(r12)// get new value
- nop // Pad palshadow write
- hw_rei // back
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_UNPRIV(0x00A0)
-CallPal_OpcDecA0:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A1)
-CallPal_OpcDecA1:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A2)
-CallPal_OpcDecA2:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A3)
-CallPal_OpcDecA3:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A4)
-CallPal_OpcDecA4:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A5)
-CallPal_OpcDecA5:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A6)
-CallPal_OpcDecA6:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A7)
-CallPal_OpcDecA7:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A8)
-CallPal_OpcDecA8:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A9)
-CallPal_OpcDecA9:
- br r31, osfpal_calpal_opcdec
-
-
-// .sbttl "gentrap - PALcode for gentrap instruction"
-//+
-// CALL_PAL_gentrap:
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-
- CALL_PAL_UNPRIV(0x00AA)
-// unsupported in Hudson code .. pboyle Nov/95
-CALL_PAL_gentrap:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, CALL_PAL_gentrap_10_ // no stack swap needed if cm=kern
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-CALL_PAL_gentrap_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_gentrap, r16// set a0
-
- stq r17, osfsf_a1(sp) // a1
- br r31, bpt_bchk_common // out of call_pal space
-
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_UNPRIV(0x00AB)
-CallPal_OpcDecAB:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00AC)
-CallPal_OpcDecAC:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00AD)
-CallPal_OpcDecAD:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00AE)
-CallPal_OpcDecAE:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00AF)
-CallPal_OpcDecAF:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B0)
-CallPal_OpcDecB0:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B1)
-CallPal_OpcDecB1:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B2)
-CallPal_OpcDecB2:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B3)
-CallPal_OpcDecB3:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B4)
-CallPal_OpcDecB4:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B5)
-CallPal_OpcDecB5:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B6)
-CallPal_OpcDecB6:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B7)
-CallPal_OpcDecB7:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B8)
-CallPal_OpcDecB8:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B9)
-CallPal_OpcDecB9:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BA)
-CallPal_OpcDecBA:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BB)
-CallPal_OpcDecBB:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BC)
-CallPal_OpcDecBC:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BD)
-CallPal_OpcDecBD:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BE)
-CallPal_OpcDecBE:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BF)
-CallPal_OpcDecBF:
- // MODIFIED BY EGH 2/25/04
- br r31, copypal_impl
-
-
-/*======================================================================*/
-/* OSF/1 CALL_PAL CONTINUATION AREA */
-/*======================================================================*/
-
- .text 2
-
- . = 0x4000
-
-
-// .sbttl "Continuation of MTPR_PERFMON"
- ALIGN_BLOCK
-#if perfmon_debug == 0
- // "real" performance monitoring code
-// mux ctl
-perfmon_muxctl:
- lda r8, 1(r31) // get a 1
- sll r8, pmctr_v_sel0, r8 // move to sel0 position
- or r8, ((0xf<<pmctr_v_sel1) | (0xf<<pmctr_v_sel2)), r8 // build mux select mask
- and r17, r8, r25 // isolate pmctr mux select bits
- mfpr r0, ev5__pmctr
- bic r0, r8, r0 // clear old mux select bits
- or r0,r25, r25 // or in new mux select bits
- mtpr r25, ev5__pmctr
-
- // ok, now tackle cbox mux selects
- ldah r14, 0xfff0(r31)
- zap r14, 0xE0, r14 // Get Cbox IPR base
-//orig get_bc_ctl_shadow r16 // bc_ctl returned in lower longword
-// adapted from ev5_pal_macros.mar
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
-
- lda r8, 0x3F(r31) // build mux select mask
- sll r8, bc_ctl_v_pm_mux_sel, r8
-
- and r17, r8, r25 // isolate bc_ctl mux select bits
- bic r16, r8, r16 // isolate old mux select bits
- or r16, r25, r25 // create new bc_ctl
- mb // clear out cbox for future ipr write
- stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
- mb // clear out cbox for future ipr write
-
-//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
-// adapted from ev5_pal_macros.mar
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
-
- br r31, perfmon_success
-
-
-// requested to disable perf monitoring
-perfmon_dis:
- mfpr r14, ev5__pmctr // read ibox pmctr ipr
-perfmon_dis_ctr0: // and begin with ctr0
- blbc r17, perfmon_dis_ctr1 // do not disable ctr0
- lda r8, 3(r31)
- sll r8, pmctr_v_ctl0, r8
- bic r14, r8, r14 // disable ctr0
-perfmon_dis_ctr1:
- srl r17, 1, r17
- blbc r17, perfmon_dis_ctr2 // do not disable ctr1
- lda r8, 3(r31)
- sll r8, pmctr_v_ctl1, r8
- bic r14, r8, r14 // disable ctr1
-perfmon_dis_ctr2:
- srl r17, 1, r17
- blbc r17, perfmon_dis_update // do not disable ctr2
- lda r8, 3(r31)
- sll r8, pmctr_v_ctl2, r8
- bic r14, r8, r14 // disable ctr2
-perfmon_dis_update:
- mtpr r14, ev5__pmctr // update pmctr ipr
-//;the following code is not needed for ev5 pass2 and later, but doesn't hurt anything to leave in
-// adapted from ev5_pal_macros.mar
-//orig get_pmctr_ctl r8, r25 // pmctr_ctl bit in r8. adjusted impure pointer in r25
- mfpr r25, pt_impure
- lda r25, CNS_Q_IPR(r25)
- RESTORE_SHADOW(r8,CNS_Q_PM_CTL,r25);
-
- lda r17, 0x3F(r31) // build mask
- sll r17, pmctr_v_ctl2, r17 // shift mask to correct position
- and r14, r17, r14 // isolate ctl bits
- bic r8, r17, r8 // clear out old ctl bits
- or r14, r8, r14 // create shadow ctl bits
-//orig store_reg1 pmctr_ctl, r14, r25, ipr=1 // update pmctr_ctl register
-//adjusted impure pointer still in r25
- SAVE_SHADOW(r14,CNS_Q_PM_CTL,r25);
-
- br r31, perfmon_success
-
-
-// requested to enable perf monitoring
-//;the following code can be greatly simplified for pass2, but should work fine as is.
-
-
-perfmon_enclr:
- lda r9, 1(r31) // set enclr flag
- br perfmon_en_cont
-
-perfmon_en:
- bis r31, r31, r9 // clear enclr flag
-
-perfmon_en_cont:
- mfpr r8, pt_pcbb // get PCB base
-//orig get_pmctr_ctl r25, r25
- mfpr r25, pt_impure
- lda r25, CNS_Q_IPR(r25)
- RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25);
-
- ldqp r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
- mfpr r14, ev5__pmctr // read ibox pmctr ipr
- srl r16, osfpcb_v_pme, r16 // get pme bit
- mfpr r13, icsr
- and r16, 1, r16 // isolate pme bit
-
- // this code only needed in pass2 and later
-//orig sget_addr r12, 1<<icsr_v_pmp, r31
- lda r12, 1<<icsr_v_pmp(r31) // pb
- bic r13, r12, r13 // clear pmp bit
- sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position
- or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear
- ev5_pass2 mtpr r13, icsr // update icsr
-
-#if ev5_p1 != 0
- lda r12, 1(r31)
- cmovlbc r25, r12, r16 // r16<0> set if either pme=1 or sprocess=0 (sprocess in bit 0 of r25)
-#else
- bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable)
-#endif
-
- sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions
- bis r14, r31, r13 // copy pmctr
-
-perfmon_en_ctr0: // and begin with ctr0
- blbc r17, perfmon_en_ctr1 // do not enable ctr0
-
- blbc r9, perfmon_en_noclr0 // enclr flag set, clear ctr0 field
- lda r8, 0xffff(r31)
- zapnot r8, 3, r8 // ctr0<15:0> mask
- sll r8, pmctr_v_ctr0, r8
- bic r14, r8, r14 // clear ctr bits
- bic r13, r8, r13 // clear ctr bits
-
-perfmon_en_noclr0:
-//orig get_addr r8, 3<<pmctr_v_ctl0, r31
- LDLI(r8, (3<<pmctr_v_ctl0))
- and r25, r8, r12 //isolate frequency select bits for ctr0
- bic r14, r8, r14 // clear ctl0 bits in preparation for enabling
- or r14,r12,r14 // or in new ctl0 bits
-
-perfmon_en_ctr1: // enable ctr1
- srl r17, 1, r17 // get ctr1 enable
- blbc r17, perfmon_en_ctr2 // do not enable ctr1
-
- blbc r9, perfmon_en_noclr1 // if enclr flag set, clear ctr1 field
- lda r8, 0xffff(r31)
- zapnot r8, 3, r8 // ctr1<15:0> mask
- sll r8, pmctr_v_ctr1, r8
- bic r14, r8, r14 // clear ctr bits
- bic r13, r8, r13 // clear ctr bits
-
-perfmon_en_noclr1:
-//orig get_addr r8, 3<<pmctr_v_ctl1, r31
- LDLI(r8, (3<<pmctr_v_ctl1))
- and r25, r8, r12 //isolate frequency select bits for ctr1
- bic r14, r8, r14 // clear ctl1 bits in preparation for enabling
- or r14,r12,r14 // or in new ctl1 bits
-
-perfmon_en_ctr2: // enable ctr2
- srl r17, 1, r17 // get ctr2 enable
- blbc r17, perfmon_en_return // do not enable ctr2 - return
-
- blbc r9, perfmon_en_noclr2 // if enclr flag set, clear ctr2 field
- lda r8, 0x3FFF(r31) // ctr2<13:0> mask
- sll r8, pmctr_v_ctr2, r8
- bic r14, r8, r14 // clear ctr bits
- bic r13, r8, r13 // clear ctr bits
-
-perfmon_en_noclr2:
-//orig get_addr r8, 3<<pmctr_v_ctl2, r31
- LDLI(r8, (3<<pmctr_v_ctl2))
- and r25, r8, r12 //isolate frequency select bits for ctr2
- bic r14, r8, r14 // clear ctl2 bits in preparation for enabling
- or r14,r12,r14 // or in new ctl2 bits
-
-perfmon_en_return:
- cmovlbs r16, r14, r13 // if pme enabled, move enables into pmctr
- // else only do the counter clears
- mtpr r13, ev5__pmctr // update pmctr ipr
-
-//;this code not needed for pass2 and later, but does not hurt to leave it in
- lda r8, 0x3F(r31)
-//orig get_pmctr_ctl r25, r12 // read pmctr ctl; r12=adjusted impure pointer
- mfpr r12, pt_impure
- lda r12, CNS_Q_IPR(r12)
- RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r12);
-
- sll r8, pmctr_v_ctl2, r8 // build ctl mask
- and r8, r14, r14 // isolate new ctl bits
- bic r25, r8, r25 // clear out old ctl value
- or r25, r14, r14 // create new pmctr_ctl
-//orig store_reg1 pmctr_ctl, r14, r12, ipr=1
- SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
-
- br r31, perfmon_success
-
-
-// options...
-perfmon_ctl:
-
-// set mode
-//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer
- mfpr r12, pt_impure
- lda r12, CNS_Q_IPR(r12)
- RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12);
-
-//orig get_addr r8, (1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk), r31 // build mode mask for pmctr register
- LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk)))
- mfpr r0, ev5__pmctr
- and r17, r8, r25 // isolate pmctr mode bits
- bic r0, r8, r0 // clear old mode bits
- or r0, r25, r25 // or in new mode bits
- mtpr r25, ev5__pmctr
-
-//;the following code will only be used in pass2, but should not hurt anything if run in pass1.
- mfpr r8, icsr
- lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0
- bic r8, r25, r8 // clear old pma bit
- cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1
- or r8, r25, r8
- ev5_pass2 mtpr r8, icsr // 4 bubbles to hw_rei
- mfpr r31, pt0 // pad icsr write
- mfpr r31, pt0 // pad icsr write
-
-//;the following code not needed for pass2 and later, but should work anyway.
- bis r14, 1, r14 // set for select processes
- blbs r17, perfmon_sp // branch if select processes
- bic r14, 1, r14 // all processes
-perfmon_sp:
-//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register
- SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
- br r31, perfmon_success
-
-// counter frequency select
-perfmon_freq:
-//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer
- mfpr r12, pt_impure
- lda r12, CNS_Q_IPR(r12)
- RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12);
-
- lda r8, 0x3F(r31)
-//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field
-// I guess this should be a shift of 4 bits from the above control register structure .. pb
-#define pmctr_ctl_v_frq2_SHIFT 4
- sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field
-
- and r8, r17, r17
- bic r14, r8, r14 // clear out old frequency select bits
-
- or r17, r14, r14 // or in new frequency select info
-//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register
- SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
-
- br r31, perfmon_success
-
-// read counters
-perfmon_rd:
- mfpr r0, ev5__pmctr
- or r0, 1, r0 // or in return status
- hw_rei // back to user
-
-// write counters
-perfmon_wr:
- mfpr r14, ev5__pmctr
- lda r8, 0x3FFF(r31) // ctr2<13:0> mask
- sll r8, pmctr_v_ctr2, r8
-
-//orig get_addr r9, 0xFFFFFFFF, r31, verify=0 // ctr2<15:0>,ctr1<15:0> mask
- LDLI(r9, (0xFFFFFFFF))
- sll r9, pmctr_v_ctr1, r9
- or r8, r9, r8 // or ctr2, ctr1, ctr0 mask
- bic r14, r8, r14 // clear ctr fields
- and r17, r8, r25 // clear all but ctr fields
- or r25, r14, r14 // write ctr fields
- mtpr r14, ev5__pmctr // update pmctr ipr
-
- mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy)
-
-perfmon_success:
- or r31, 1, r0 // set success
- hw_rei // back to user
-
-perfmon_unknown:
- or r31, r31, r0 // set fail
- hw_rei // back to user
-
-#else
-
-// end of "real code", start of debug code
-
-//+
-// Debug environment:
-// (in pass2, always set icsr<pma> to ensure master counter enable is on)
-// R16 = 0 Write to on-chip performance monitor ipr
-// r17 = on-chip ipr
-// r0 = return value of read of on-chip performance monitor ipr
-// R16 = 1 Setup Cbox mux selects
-// r17 = Cbox mux selects in same position as in bc_ctl ipr.
-// r0 = return value of read of on-chip performance monitor ipr
-//
-//-
-pal_perfmon_debug:
- mfpr r8, icsr
- lda r9, 1<<icsr_v_pma(r31)
- bis r8, r9, r8
- mtpr r8, icsr
-
- mfpr r0, ev5__pmctr // read old value
- bne r16, cbox_mux_sel
-
- mtpr r17, ev5__pmctr // update pmctr ipr
- br r31, end_pm
-
-cbox_mux_sel:
- // ok, now tackle cbox mux selects
- ldah r14, 0xfff0(r31)
- zap r14, 0xE0, r14 // Get Cbox IPR base
-//orig get_bc_ctl_shadow r16 // bc_ctl returned
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
-
- lda r8, 0x3F(r31) // build mux select mask
- sll r8, BC_CTL_V_PM_MUX_SEL, r8
-
- and r17, r8, r25 // isolate bc_ctl mux select bits
- bic r16, r8, r16 // isolate old mux select bits
- or r16, r25, r25 // create new bc_ctl
- mb // clear out cbox for future ipr write
- stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
- mb // clear out cbox for future ipr write
-//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
-
-end_pm: hw_rei
-
-#endif
-
-
-//;The following code is a workaround for a cpu bug where Istream prefetches to
-//;super-page address space in user mode may escape off-chip.
-#if spe_fix != 0
-
- ALIGN_BLOCK
-hw_rei_update_spe:
- mfpr r12, pt_misc // get previous mode
- srl r11, osfps_v_mode, r10 // isolate current mode bit
- and r10, 1, r10
- extbl r12, 7, r8 // get previous mode field
- and r8, 1, r8 // isolate previous mode bit
- cmpeq r10, r8, r8 // compare previous and current modes
- beq r8, hw_rei_update_spe_5_
- hw_rei // if same, just return
-
-hw_rei_update_spe_5_:
-
-#if fill_err_hack != 0
-
- fill_error_hack
-#endif
-
- mfpr r8, icsr // get current icsr value
- ldah r9, (2<<(icsr_v_spe-16))(r31) // get spe bit mask
- bic r8, r9, r8 // disable spe
- xor r10, 1, r9 // flip mode for new spe bit
- sll r9, icsr_v_spe+1, r9 // shift into position
- bis r8, r9, r8 // enable/disable spe
- lda r9, 1(r31) // now update our flag
- sll r9, pt_misc_v_cm, r9 // previous mode saved bit mask
- bic r12, r9, r12 // clear saved previous mode
- sll r10, pt_misc_v_cm, r9 // current mode saved bit mask
- bis r12, r9, r12 // set saved current mode
- mtpr r12, pt_misc // update pt_misc
- mtpr r8, icsr // update icsr
-
-#if osf_chm_fix != 0
-
-
- blbc r10, hw_rei_update_spe_10_ // branch if not user mode
-
- mb // ensure no outstanding fills
- lda r12, 1<<dc_mode_v_dc_ena(r31) // User mode
- mtpr r12, dc_mode // Turn on dcache
- mtpr r31, dc_flush // and flush it
- br r31, pal_ic_flush
-
-hw_rei_update_spe_10_: mfpr r9, pt_pcbb // Kernel mode
- ldqp r9, osfpcb_q_Fen(r9) // get FEN
- blbc r9, pal_ic_flush // return if FP disabled
- mb // ensure no outstanding fills
- mtpr r31, dc_mode // turn off dcache
-#endif
-
-
- br r31, pal_ic_flush // Pal restriction - must flush Icache if changing ICSR<SPE>
-#endif
-
-
-copypal_impl:
- mov r16, r0
- and r16, 63, r8
- and r17, 63, r9
- bis r8, r9, r8
- bne r8, cache_copy_done
- bic r18, 63, r8
- and r18, 63, r18
- beq r8, cache_copy_done
- cache_loop:
- ldf f17, 0(r16)
- stf f17, 0(r16)
- addq r17, 64, r17
- addq r16, 64, r16
- subq r8, 64, r8
- bne r8, cache_loop
-cache_copy_done:
- ble r18, finished #if len <=0 we are finished
- ldq_u r8, 0(r17)
- xor r17, r16, r9
- and r9, 7, r9
- and r16, 7, r10
- bne r9, unaligned
- beq r10, aligned
- ldq_u r9, 0(r16)
- addq r18, r10, r18
- mskqh r8, r17, r8
- mskql r9, r17, r9
- bis r8, r9, r8
-aligned:
- subq r18, 1, r10
- bic r10, 7, r10
- and r18, 7, r18
- beq r10, aligned_done
-loop:
- stq_u r8, 0(r16)
- ldq_u r8, 8(r17)
- subq r10, 8, r10
- lda r16,8(r16)
- lda r17,8(r17)
- bne r10, loop
-aligned_done:
- bne r18, few_left
- stq_u r8, 0(r16)
- br r31, finished
- few_left:
- mskql r8, r18, r10
- ldq_u r9, 0(r16)
- mskqh r9, r18, r9
- bis r10, r9, r10
- stq_u r10, 0(r16)
- br r31, finished
-unaligned:
- addq r17, r18, r25
- cmpule r18, 8, r9
- bne r9, unaligned_few_left
- beq r10, unaligned_dest_aligned
- and r16, 7, r10
- subq r31, r10, r10
- addq r10, 8, r10
- ldq_u r9, 7(r17)
- extql r8, r17, r8
- extqh r9, r17, r9
- bis r8, r9, r12
- insql r12, r16, r12
- ldq_u r13, 0(r16)
- mskql r13, r16, r13
- bis r12, r13, r12
- stq_u r12, 0(r16)
- addq r16, r10, r16
- addq r17, r10, r17
- subq r18, r10, r18
- ldq_u r8, 0(r17)
-unaligned_dest_aligned:
- subq r18, 1, r10
- bic r10, 7, r10
- and r18, 7, r18
- beq r10, unaligned_partial_left
-unaligned_loop:
- ldq_u r9, 7(r17)
- lda r17, 8(r17)
- extql r8, r17, r12
- extqh r9, r17, r13
- subq r10, 8, r10
- bis r12, r13, r13
- stq r13, 0(r16)
- lda r16, 8(r16)
- beq r10, unaligned_second_partial_left
- ldq_u r8, 7(r17)
- lda r17, 8(r17)
- extql r9, r17, r12
- extqh r8, r17, r13
- bis r12, r13, r13
- subq r10, 8, r10
- stq r13, 0(r16)
- lda r16, 8(r16)
- bne r10, unaligned_loop
-unaligned_partial_left:
- mov r8, r9
-unaligned_second_partial_left:
- ldq_u r8, -1(r25)
- extql r9, r17, r9
- extqh r8, r17, r8
- bis r8, r9, r8
- bne r18, few_left
- stq_u r8, 0(r16)
- br r31, finished
-unaligned_few_left:
- ldq_u r9, -1(r25)
- extql r8, r17, r8
- extqh r9, r17, r9
- bis r8, r9, r8
- insqh r8, r16, r9
- insql r8, r16, r8
- lda r12, -1(r31)
- mskql r12, r18, r13
- cmovne r13, r13, r12
- insqh r12, r16, r13
- insql r12, r16, r12
- addq r16, r18, r10
- ldq_u r14, 0(r16)
- ldq_u r25, -1(r10)
- bic r14, r12, r14
- bic r25, r13, r25
- and r8, r12, r8
- and r9, r13, r9
- bis r8, r14, r8
- bis r9, r25, r9
- stq_u r9, -1(r10)
- stq_u r8, 0(r16)
-finished:
- hw_rei
+++ /dev/null
-/*
- * Copyright (c) 2003, 2004
- * The Regents of The University of Michigan
- * All Rights Reserved
- *
- * This code is part of the M5 simulator, developed by Nathan Binkert,
- * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
- * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
- * Schultz.
- *
- * Permission is granted to use, copy, create derivative works and
- * redistribute this software and such derivative works for any
- * purpose, so long as the copyright notice above, this grant of
- * permission, and the disclaimer below appear in all copies made; and
- * so long as the name of The University of Michigan is not used in
- * any advertising or publicity pertaining to the use or distribution
- * of this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
- * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
- * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
- * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
- * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
- * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
- * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
- * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGES.
- */
-/*
-Copyright 1992, 1993, 1994, 1995 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl
-// since we don't have a mechanism to expand the data structures.... pb Nov/95
-
-// build_fixed_image: not sure what means
-// real_mm to be replaced during rewrite
-// remove_save_state remove_restore_state can be remooved to save space ??
-
-
-#include "ev5_defs.h"
-#include "ev5_impure.h"
-#include "ev5_alpha_defs.h"
-#include "ev5_paldef.h"
-#include "ev5_osfalpha_defs.h"
-#include "fromHudsonMacros.h"
-#include "fromHudsonOsf.h"
-#include "dc21164FromGasSources.h"
-
-#ifdef SIMOS
-#define DEBUGSTORE(c) nop
-#else
-#define DEBUGSTORE(c) \
- lda r13, c(zero) ; \
- bsr r25, debugstore
-#endif
-
-#define DEBUG_EXC_ADDR()\
- bsr r25, put_exc_addr; \
- DEBUGSTORE(13) ; \
- DEBUGSTORE(10)
-
-#define egore 0
-#define acore 0
-#define beh_model 0
-#define ev5_p2 1
-#define ev5_p1 0
-#define ldvpte_bug_fix 1
-#define osf_chm_fix 0
-
-// Do we want to do this?? pb
-#define spe_fix 0
-// Do we want to do this?? pb
-#define build_fixed_image 0
-
-#define ev5_pass2
-#define enable_p4_fixups 0
-#define osf_svmin 1
-#define enable_physical_console 0
-#define fill_err_hack 0
-#define icflush_on_tbix 0
-#define max_cpuid 1
-#define perfmon_debug 0
-#define rawhide_system 0
-#define rax_mode 0
-
-
-// This is the fix for the user-mode super page references causing the machine to crash.
-#if (spe_fix == 1) && (build_fixed_image==1)
-#define hw_rei_spe br r31, hw_rei_update_spe
-#else
-#define hw_rei_spe hw_rei
-#endif
-
-
-// redefine a few of the distribution-code names to match the Hudson gas names.
-// opcodes
-#define ldqp ldq_p
-#define stqp stq_p
-#define ldlp ldl_p
-#define stlp stl_p
-
-#define r0 $0
-#define r1 $1
-#define r2 $2
-#define r3 $3
-#define r4 $4
-#define r5 $5
-#define r6 $6
-#define r7 $7
-#define r8 $8
-#define r9 $9
-#define r10 $10
-#define r11 $11
-#define r12 $12
-#define r13 $13
-#define r14 $14
-#define r15 $15
-#define r16 $16
-#define r17 $17
-#define r18 $18
-#define r19 $19
-#define r20 $20
-#define r21 $21
-#define r22 $22
-#define r23 $23
-#define r24 $24
-#define r25 $25
-#define r26 $26
-#define r27 $27
-#define r28 $28
-#define r29 $29
-#define r30 $30
-#define r31 $31
-
-// .title "EV5 OSF PAL"
-// .ident "V1.18"
-//
-//****************************************************************************
-//* *
-//* Copyright (c) 1992, 1993, 1994, 1995 *
-//* by DIGITAL Equipment Corporation, Maynard, Mass. *
-//* *
-//* This software is furnished under a license and may be used and copied *
-//* only in accordance with the terms of such license and with the *
-//* inclusion of the above copyright notice. This software or any other *
-//* copies thereof may not be provided or otherwise made available to any *
-//* other person. No title to and ownership of the software is hereby *
-//* transferred. *
-//* *
-//* The information in this software is subject to change without notice *
-//* and should not be construed as a commitment by DIGITAL Equipment *
-//* Corporation. *
-//* *
-//* DIGITAL assumes no responsibility for the use or reliability of its *
-//* software on equipment which is not supplied by DIGITAL. *
-//* *
-//****************************************************************************
-
-// .sbttl "Edit History"
-//+
-// Who Rev When What
-// ------------ --- ----------- --------------------------------
-// DB 0.0 03-Nov-1992 Start
-// DB 0.1 28-Dec-1992 add swpctx
-// DB 0.2 05-Jan-1993 Bug: PVC found mtpr dtb_CM -> virt ref bug
-// DB 0.3 11-Jan-1993 rearrange trap entry points
-// DB 0.4 01-Feb-1993 add tbi
-// DB 0.5 04-Feb-1993 real MM, kludge reset flow, kludge swppal
-// DB 0.6 09-Feb-1993 Bug: several stack pushers used r16 for pc (should be r14)
-// DB 0.7 10-Feb-1993 Bug: pushed wrong PC (+8) on CALL_PAL OPCDEC
-// Bug: typo on register number for store in wrunique
-// Bug: rti to kern uses r16 as scratch
-// Bug: callsys saving wrong value in pt_usp
-// DB 0.8 16-Feb-1993 PVC: fix possible pt write->read bug in wrkgp, wrusp
-// DB 0.9 18-Feb-1993 Bug: invalid_dpte_handler shifted pte twice
-// Bug: rti stl_c could corrupt the stack
-// Bug: unaligned returning wrong value in r17 (or should be and)
-// DB 0.10 19-Feb-1993 Add draina, rd/wrmces, cflush, cserve, interrupt
-// DB 0.11 23-Feb-1993 Turn caches on in reset flow
-// DB 0.12 10-Mar-1993 Bug: wrong value for icsr for FEN in kern mode flow
-// DB 0.13 15-Mar-1993 Bug: wrong value pushed for PC in invalid_dpte_handler if stack push tbmisses
-// DB 0.14 23-Mar-1993 Add impure pointer paltemp, reshuffle some other paltemps to match VMS
-// DB 0.15 15-Apr-1993 Combine paltemps for WHAMI and MCES
-// DB 0.16 12-May-1993 Update reset
-// New restriction: no mfpr exc_addr in cycle 1 of call_pal flows
-// Bug: in wrmces, not clearing DPC, DSC
-// Update swppal
-// Add pal bugchecks, pal_save_state, pal_restore_state
-// DB 0.17 24-May-1993 Add dfault_in_pal flow; fixup stack builder to have common state for pc/ps.
-// New restriction: No hw_rei_stall in 0,1,2 after mtpr itb_asn
-// DB 0.18 26-May-1993 PVC fixes
-// JM 0.19 01-jul-1993 Bug: OSFPAL_CALPAL_OPCDEC, TRAP_OPCDEC -- move mt exc_addr after stores
-// JM 0.20 07-jul-1993 Update cns_ and mchk_ names for impure.mar conversion to .sdl
-// Bug: exc_addr was being loaded before stores that could dtb_miss in the following
-// routines: TRAP_FEN,FEN_TO_OPCDEC,CALL_PAL_CALLSYS,RTI_TO_KERN
-// JM 0.21 26-jul-1993 Bug: move exc_addr load after ALL stores in the following routines:
-// TRAP_IACCVIO::,TRAP_OPCDEC::,TRAP_ARITH::,TRAP_FEN::
-// dfault_trap_cont:,fen_to_opcdec:,invalid_dpte_handler:
-// osfpal_calpal_opcdec:,CALL_PAL_callsys::,TRAP_UNALIGN::
-// Bugs from PVC: trap_unalign - mt pt0 ->mf pt0 within 2 cycles
-// JM 0.22 28-jul-1993 Add WRIPIR instruction
-// JM 0.23 05-aug-1993 Bump version number for release
-// JM 0.24 11-aug-1993 Bug: call_pal_swpipl - palshadow write -> hw_rei violation
-// JM 0.25 09-sep-1993 Disable certain "hidden" pvc checks in call_pals;
-// New restriction: No hw_rei_stall in 0,1,2,3,4 after mtpr itb_asn - affects HALT(raxmode),
-// and SWPCTX
-// JM 0.26 07-oct-1993 Re-implement pal_version
-// JM 0.27 12-oct-1993 One more time: change pal_version format to conform to SRM
-// JM 0.28 14-oct-1993 Change ic_flush routine to pal_ic_flush
-// JM 0.29 19-oct-1993 BUG(?): dfault_in_pal: use exc_addr to check for dtbmiss,itbmiss check instead
-// of mm_stat<opcode>. mm_stat contains original opcode, not hw_ld.
-// JM 0.30 28-oct-1993 BUG: PVC violation - mf exc_addr in first cycles of call_pal in rti,retsys
-// JM 0.31 15-nov-1993 BUG: WRFEN trashing r0
-// JM 0.32 21-nov-1993 BUG: dtb_ldq,itb_ldq (used in dfault_in_pal) not defined when real_mm=0
-// JM 0.33 24-nov-1993 save/restore_state -
-// BUG: use ivptbr to restore mvptbr
-// BUG: adjust hw_ld/st base/offsets to accomodate 10-bit offset limit
-// CHANGE: Load 2 pages into dtb to accomodate compressed logout area/multiprocessors
-// JM 0.34 20-dec-1993 BUG: set r11<mode> to kernel for ksnv halt case
-// BUG: generate ksnv halt when tb miss on kernel stack accesses
-// save exc_addr in r14 for invalid_dpte stack builder
-// JM 0.35 30-dec-1993 BUG: PVC violation in trap_arith - mt exc_sum in shadow of store with mf exc_mask in
-// the same shadow
-// JM 0.36 6-jan-1994 BUG: fen_to_opcdec - savePC should be PC+4, need to save old PS, update new PS
-// New palcode restiction: mt icsr<fpe,hwe> --> 3 bubbles to hw_rei --affects wrfen
-// JM 0.37 25-jan-1994 BUG: PVC violations in restore_state - mt dc_mode/maf_mode ->mbox instructions
-// Hide impure area manipulations in macros
-// BUG: PVC violation in save and restore state-- move mt icsr out of shadow of ld/st
-// Add some pvc_violate statements
-// JM 0.38 1-feb-1994 Changes to save_state: save pt1; don't save r31,f31; update comments to reflect reality;
-// Changes to restore_state: restore pt1, icsr; don't restore r31,f31; update comments
-// Add code to ensure fen bit set in icsr before ldt
-// conditionally compile rax_more_reset out.
-// move ldqp,stqp macro definitions to ev5_pal_macros.mar and add .mcall's for them here
-// move rax reset stuff to ev5_osf_system_pal.m64
-// JM 0.39 7-feb-1994 Move impure pointer to pal scratch space. Use former pt_impure for bc_ctl shadow
-// and performance monitoring bits
-// Change to save_state routine to save more iprs.
-// JM 0.40 19-feb-1994 Change algorithm in save/restore_state routines; add f31,r31 back in
-// JM 0.41 21-feb-1994 Add flags to compile out save/restore state (not needed in some systems)
-// remove_save_state,remove_restore_state;fix new pvc violation in save_state
-// JM 0.42 22-feb-1994 BUG: save_state overwriting r3
-// JM 0.43 24-feb-1994 BUG: save_state saving wrong icsr
-// JM 0.44 28-feb-1994 Remove ic_flush from wr_tbix instructions
-// JM 0.45 15-mar-1994 BUG: call_pal_tbi trashes a0 prior to range check (instruction order problem)
-// New pal restriction in pal_restore_state: icsr<fpe>->floating instr = 3 bubbles
-// Add exc_sum and exc_mask to pal_save_state (not restore)
-// JM 0.46 22-apr-1994 Move impure pointer back into paltemp; Move bc_ctl shadow and pmctr_ctl into impure
-// area.
-// Add performance counter support to swpctx and wrperfmon
-// JM 0.47 9-may-1994 Bump version # (for ev5_osf_system_pal.m64 sys_perfmon fix)
-// JM 0.48 13-jun-1994 BUG: trap_interrupt --> put new ev5 ipl at 30 for all osfipl6 interrupts
-// JM 0.49 8-jul-1994 BUG: In the unlikely (impossible?) event that the branch to pal_pal_bug_check is
-// taken in the interrupt flow, stack is pushed twice.
-// SWPPAL - update to support ECO 59 to allow 0 as a valid address
-// Add itb flush to save/restore state routines
-// Change hw_rei to hw_rei_stall in ic_flush routine. Shouldn't be necessary, but
-// conforms to itbia restriction.
-// Added enable_physical_console flag (for enter/exit console routines only)
-// JM 0.50 29-jul-1994 Add code to dfault & invalid_dpte_handler to ignore exceptions on a
-// load to r31/f31. changed dfault_fetch_err to dfault_fetch_ldr31_err and
-// nmiss_fetch_err to nmiss_fetch_ldr31_err.
-// JM 1.00 1-aug-1994 Add pass2 support (swpctx)
-// JM 1.01 2-aug-1994 swppal now passes bc_ctl/bc_config in r1/r2
-// JM 1.02 15-sep-1994 BUG: swpctx missing shift of pme bit to correct position in icsr (pass2)
-// Moved perfmon code here from system file.
-// BUG: pal_perfmon - enable function not saving correct enables when pme not set (pass1)
-// JM 1.03 3-oct-1994 Added (pass2 only) code to wrperfmon enable function to look at pme bit.
-// JM 1.04 14-oct-1994 BUG: trap_interrupt - ISR read (and saved) before INTID -- INTID can change
-// after ISR read, but we won't catch the ISR update. reverse order
-// JM 1.05 17-nov-1994 Add code to dismiss UNALIGN trap if LD r31/F31
-// JM 1.06 28-nov-1994 BUG: missing mm_stat shift for store case in trap_unalign (new bug due to "dismiss" code)
-// JM 1.07 1-dec-1994 EV5 PASS1,2,3 BUG WORKAROUND: Add flag LDVPTE_BUG_FIX. In DTBMISS_DOUBLE, branch to
-// DTBMISS_SINGLE if not in palmode.
-// JM 1.08 9-jan-1995 Bump version number for change to EV5_OSF_SYSTEM_PAL.M64 - ei_stat fix in mchk logout frame
-// JM 1.09 2-feb-1995 Add flag "spe_fix" and accompanying code to workaround pre-pass4 bug: Disable Ibox
-// superpage mode in User mode and re-enable in kernel mode.
-// EV5_OSF_SYSTEM_PAL.M64 and EV5_PALDEF.MAR (added pt_misc_v_cm) also changed to support this.
-// JM 1.10 24-feb-1995 Set ldvpte_bug_fix regardless of ev5 pass. set default to ev5_p2
-// ES 1.11 10-mar-1995 Add flag "osf_chm_fix" to enable dcache in user mode only to avoid
-// cpu bug.
-// JM 1.12 17-mar-1995 BUG FIX: Fix F0 corruption problem in pal_restore_state
-// ES 1.13 17-mar-1995 Refine osf_chm_fix
-// ES 1.14 20-mar-1995 Don't need as many stalls before hw_rei_stall in chm_fix
-// ES 1.15 21-mar-1995 Add a stall to avoid a pvc violation in pal_restore_state
-// Force pvc checking of exit_console
-// ES 1.16 26-apr-1995 In the wrperfmon disable function, correct meaning of R17<2:0> to ctl2,ctl2,ctl0
-// ES 1.17 01-may-1995 In hw_rei_update_spe code, in the osf_chm fix, use bic and bis (self-correcting)
-// instead of xor to maintain previous mode in pt_misc
-// ES 1.18 14-jul-1995 In wrperfmon enable on pass2, update pmctr even if current process does
-// not have pme set. The bits in icsr maintain the master enable state.
-// In sys_reset, add icsr<17>=1 for ev56 byte/word eco enable
-//
-#define vmaj 1
-#define vmin 18
-#define vms_pal 1
-#define osf_pal 2
-#define pal_type osf_pal
-#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0))
-//-
-
-// .sbttl "PALtemp register usage"
-
-//+
-// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage
-// for these PALtemps:
-//
-// pt0 local scratch
-// pt1 local scratch
-// pt2 entUna pt_entUna
-// pt3 CPU specific impure area pointer pt_impure
-// pt4 memory management temp
-// pt5 memory management temp
-// pt6 memory management temp
-// pt7 entIF pt_entIF
-// pt8 intmask pt_intmask
-// pt9 entSys pt_entSys
-// pt10
-// pt11 entInt pt_entInt
-// pt12 entArith pt_entArith
-// pt13 reserved for system specific PAL
-// pt14 reserved for system specific PAL
-// pt15 reserved for system specific PAL
-// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami, pt_mces
-// pt17 sysval pt_sysval
-// pt18 usp pt_usp
-// pt19 ksp pt_ksp
-// pt20 PTBR pt_ptbr
-// pt21 entMM pt_entMM
-// pt22 kgp pt_kgp
-// pt23 PCBB pt_pcbb
-//
-//-
-
-// .sbttl "PALshadow register usage"
-//
-//+
-//
-// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1.
-// This maps the OSF PAL usage of R8 - R14 and R25:
-//
-// r8 ITBmiss/DTBmiss scratch
-// r9 ITBmiss/DTBmiss scratch
-// r10 ITBmiss/DTBmiss scratch
-// r11 PS
-// r12 local scratch
-// r13 local scratch
-// r14 local scratch
-// r25 local scratch
-//
-//
-//-
-
-// .sbttl "ALPHA symbol definitions"
-// _OSF_PSDEF GLOBAL
-// _OSF_PTEDEF GLOBAL
-// _OSF_VADEF GLOBAL
-// _OSF_PCBDEF GLOBAL
-// _OSF_SFDEF GLOBAL
-// _OSF_MMCSR_DEF GLOBAL
-// _SCBDEF GLOBAL
-// _FRMDEF GLOBAL
-// _EXSDEF GLOBAL
-// _OSF_A0_DEF GLOBAL
-// _MCESDEF GLOBAL
-
-// .sbttl "EV5 symbol definitions"
-
-// _EV5DEF
-// _PALTEMP
-// _MM_STAT_DEF
-// _EV5_MM
-// _EV5_IPLDEF
-
-// _HALT_CODES GLOBAL
-// _MCHK_CODES GLOBAL
-
-// _PAL_IMPURE
-// _PAL_LOGOUT
-
-
-
-
-// .sbttl "PALcode configuration options"
-
-// There are a number of options that may be assembled into this version of
-// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit
-// the following). The options that can be adjusted cause the resultant PALcode
-// to reflect the desired target system.
-
-
-#define osfpal 1 // This is the PALcode for OSF.
-
-#ifndef rawhide_system
-
-#define rawhide_system 0
-#endif
-
-
-#ifndef real_mm
-// Page table translation vs 1-1 mapping
-#define real_mm 1
-#endif
-
-
-#ifndef rax_mode
-
-#define rax_mode 0
-#endif
-
-#ifndef egore
-// End of reset flow starts a program at 200000(hex).
-#define egore 1
-#endif
-
-#ifndef acore
-// End of reset flow starts a program at 40000(hex).
-#define acore 0
-#endif
-
-
-// assume acore+egore+rax_mode lt 2 // Assertion checker
-
-#ifndef beh_model
-// EV5 behavioral model specific code
-#define beh_model 1
-#endif
-
-#ifndef init_cbox
-// Reset flow init of Bcache and Scache
-#define init_cbox 1
-#endif
-
-#ifndef disable_crd
-// Decides whether the reset flow will disable
-#define disable_crd 0
-#endif
-
- // correctable read interrupts via ICSR
-#ifndef perfmon_debug
-#define perfmon_debug 0
-#endif
-
-#ifndef icflush_on_tbix
-#define icflush_on_tbix 0
-#endif
-
-#ifndef remove_restore_state
-#define remove_restore_state 0
-#endif
-
-#ifndef remove_save_state
-#define remove_save_state 0
-#endif
-
-#ifndef enable_physical_console
-#define enable_physical_console 0
-#endif
-
-#ifndef ev5_p1
-#define ev5_p1 0
-#endif
-
-#ifndef ev5_p2
-#define ev5_p2 1
-#endif
-
-// assume ev5_p1+ev5_p2 eq 1
-
-#ifndef ldvpte_bug_fix
-#define ldvpte_bug_fix 1 // If set, fix ldvpte bug in dtbmiss_double flow.
-#endif
-
-#ifndef spe_fix
-// If set, disable super-page mode in user mode and re-enable
-#define spe_fix 0
-#endif
- // in kernel. Workaround for cpu bug.
-#ifndef build_fixed_image
-#define build_fixed_image 0
-#endif
-
-
-#ifndef fill_err_hack
-// If set, disable fill_error mode in user mode and re-enable
-#define fill_err_hack 0
-#endif
-
- // in kernel. Workaround for cpu bug.
-
-// .macro hw_rei_spe
-// .iif eq spe_fix, hw_rei
-//#if spe_fix != 0
-//
-//
-//#define hw_rei_chm_count hw_rei_chm_count + 1
-// p4_fixup_label \hw_rei_chm_count
-// .iif eq build_fixed_image, br r31, hw_rei_update_spe
-// .iif ne build_fixed_image, hw_rei
-//#endif
-//
-// .endm
-
-// Add flag "osf_chm_fix" to enable dcache in user mode only
-// to avoid cpu bug.
-
-#ifndef osf_chm_fix
-// If set, enable D-Cache in
-#define osf_chm_fix 0
-#endif
-
-#if osf_chm_fix != 0
-// user mode only.
-#define hw_rei_chm_count 0
-#endif
-
-#if osf_chm_fix != 0
-
-#define hw_rei_stall_chm_count 0
-#endif
-
-#ifndef enable_p4_fixups
-
-#define enable_p4_fixups 0
-#endif
-
- // If set, do EV5 Pass 4 fixups
-#if spe_fix == 0
-
-#define osf_chm_fix 0
-#endif
-
-#if spe_fix == 0
-
-#define enable_p4_fixups 0
-#endif
-
- // Only allow fixups if fix enabled
-
- //Turn off fill_errors and MEM_NEM in user mode
-// .macro fill_error_hack ?L10_, ?L20_, ?L30_, ?L40_
-// //save r22,r23,r24
-// stqp r22, 0x150(r31) //add
-// stqp r23, 0x158(r31) //contents
-// stqp r24, 0x160(r31) //bit mask
-//
-// lda r22, 0x82(r31)
-// ldah r22, 0x8740(r22)
-// sll r22, 8, r22
-// ldlp r23, 0x80(r22) // r23 <- contents of CIA_MASK
-// bis r23,r31,r23
-//
-// lda r24, 0x8(r31) // r24 <- MEM_NEM bit
-// beq r10, L10_ // IF user mode (r10<0> == 0) pal mode
-// bic r23, r24, r23 // set fillerr_en bit
-// br r31, L20_ // ELSE
-//L10_: bis r23, r24, r23 // clear fillerr_en bit
-//L20_: // ENDIF
-//
-// stlp r23, 0x80(r22) // write back the CIA_MASK register
-// mb
-// ldlp r23, 0x80(r22)
-// bis r23,r31,r23
-// mb
-//
-// lda r22, 1(r31) // r22 <- 87.4000.0100 ptr to CIA_CTRL
-// ldah r22, 0x8740(r22)
-// sll r22, 8, r22
-// ldlp r23, 0(r22) // r23 <- contents of CIA_CTRL
-// bis r23,r31,r23
-//
-//
-// lda r24, 0x400(r31) // r9 <- fillerr_en bit
-// beq r10, L30_ // IF user mode (r10<0> == 0) pal mode
-// bic r23, r24, r23 // set fillerr_en bit
-// br r31, L40_ // ELSE
-//L30_: bis r23, r24, r23 // clear fillerr_en bit
-//L40_: // ENDIF
-//
-// stlp r23, 0(r22) // write back the CIA_CTRL register
-// mb
-// ldlp r23, 0(r22)
-// bis r23,r31,r23
-// mb
-//
-// //restore r22,r23,r24
-// ldqp r22, 0x150(r31)
-// ldqp r23, 0x158(r31)
-// ldqp r24, 0x160(r31)
-//
-// .endm
-
-// multiprocessor support can be enabled for a max of n processors by
-// setting the following to the number of processors on the system.
-// Note that this is really the max cpuid.
-
-#ifndef max_cpuid
-#define max_cpuid 8
-#endif
-
-#ifndef osf_svmin // platform specific palcode version number
-#define osf_svmin 0
-#endif
-
-
-#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0))
-
-// .mcall ldqp // override macro64 definition with macro from library
-// .mcall stqp // override macro64 definition with macro from library
-
-
-// .psect _pal,mix
-// huh pb pal_base:
-// huh pb #define current_block_base . - pal_base
-
-// .sbttl "RESET - Reset Trap Entry Point"
-//+
-// RESET - offset 0000
-// Entry:
-// Vectored into via hardware trap on reset, or branched to
-// on swppal.
-//
-// r0 = whami
-// r1 = pal_base
-// r2 = base of scratch area
-// r3 = halt code
-//
-//
-// Function:
-//
-//-
-
- .text 0
- . = 0x0000
- .globl Pal_Base
-Pal_Base:
- HDW_VECTOR(PAL_RESET_ENTRY)
-Trap_Reset:
- nop
-#ifdef SIMOS
- /*
- * store into r1
- */
- br r1,sys_reset
-#else
- /* following is a srcmax change */
-
- DEBUGSTORE(0x41)
- /* The original code jumped using r1 as a linkage register to pass the base
- of PALcode to the platform specific code. We use r1 to pass a parameter
- from the SROM, so we hardcode the address of Pal_Base in platform.s
- */
- br r31, sys_reset
-#endif
-
- // Specify PAL version info as a constant
- // at a known location (reset + 8).
-
- .long osfpal_version_l // <pal_type@16> ! <vmaj@8> ! <vmin@0>
- .long osfpal_version_h // <max_cpuid@16> ! <osf_svmin@0>
- .long 0
- .long 0
-pal_impure_start:
- .quad 0
-pal_debug_ptr:
- .quad 0 // reserved for debug pointer ; 20
-#if beh_model == 0
-
-
-#if enable_p4_fixups != 0
-
-
- .quad 0
- .long p4_fixup_hw_rei_fixup_table
-#endif
-
-#else
-
- .quad 0 //
- .quad 0 //0x0030
- .quad 0
- .quad 0 //0x0040
- .quad 0
- .quad 0 //0x0050
- .quad 0
- .quad 0 //0x0060
- .quad 0
-pal_enter_cns_address:
- .quad 0 //0x0070 -- address to jump to from enter_console
- .long <<sys_exit_console-pal_base>+1> //0x0078 -- offset to sys_exit_console (set palmode bit)
-#endif
-
-
-
-
-// .sbttl "IACCVIO- Istream Access Violation Trap Entry Point"
-
-//+
-// IACCVIO - offset 0080
-// Entry:
-// Vectored into via hardware trap on Istream access violation or sign check error on PC.
-//
-// Function:
-// Build stack frame
-// a0 <- Faulting VA
-// a1 <- MMCSR (1 for ACV)
-// a2 <- -1 (for ifetch fault)
-// vector via entMM
-//-
-
- HDW_VECTOR(PAL_IACCVIO_ENTRY)
-Trap_Iaccvio:
- DEBUGSTORE(0x42)
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS
- bge r25, TRAP_IACCVIO_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r12 // Set new PS
- mfpr r30, pt_ksp
-
-TRAP_IACCVIO_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r16, osfsf_a0(sp) // save regs
- bic r14, 3, r16 // pass pc/va as a0
-
- stq r17, osfsf_a1(sp) // a1
- or r31, mmcsr_c_acv, r17 // pass mm_csr as a1
-
- stq r18, osfsf_a2(sp) // a2
- mfpr r13, pt_entmm // get entry point
-
- stq r11, osfsf_ps(sp) // save old ps
- bis r12, r31, r11 // update ps
-
- stq r16, osfsf_pc(sp) // save pc
- stq r29, osfsf_gp(sp) // save gp
-
- mtpr r13, exc_addr // load exc_addr with entMM
- // 1 cycle to hw_rei
- mfpr r29, pt_kgp // get the kgp
-
- subq r31, 1, r18 // pass flag of istream, as a2
- hw_rei_spe
-
-
-// .sbttl "INTERRUPT- Interrupt Trap Entry Point"
-
-//+
-// INTERRUPT - offset 0100
-// Entry:
-// Vectored into via trap on hardware interrupt
-//
-// Function:
-// check for halt interrupt
-// check for passive release (current ipl geq requestor)
-// if necessary, switch to kernel mode
-// push stack frame, update ps (including current mode and ipl copies), sp, and gp
-// pass the interrupt info to the system module
-//
-//-
-
-
- HDW_VECTOR(PAL_INTERRUPT_ENTRY)
-Trap_Interrupt:
- mfpr r13, ev5__intid // Fetch level of interruptor
- mfpr r25, ev5__isr // Fetch interrupt summary register
-
- srl r25, isr_v_hlt, r9 // Get HLT bit
- mfpr r14, ev5__ipl
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern
- blbs r9, sys_halt_interrupt // halt_interrupt if HLT bit set
-
- cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl
- bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl
-
- and r11, osfps_m_mode, r10 // get mode bit
- beq r10, TRAP_INTERRUPT_10_ // Skip stack swap in kernel
-
- mtpr r30, pt_usp // save user stack
- mfpr r30, pt_ksp // get kern stack
-
-TRAP_INTERRUPT_10_:
- lda sp, (0-osfsf_c_size)(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r11, osfsf_ps(sp) // save ps
- stq r14, osfsf_pc(sp) // save pc
-
- stq r29, osfsf_gp(sp) // push gp
- stq r16, osfsf_a0(sp) // a0
-
-// pvc_violate 354 // ps is cleared anyway, if store to stack faults.
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
- stq r17, osfsf_a1(sp) // a1
-
- stq r18, osfsf_a2(sp) // a2
- subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL
-
- srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7.
- subq r13, 0x1d, r9 // Check for 1d, 1e, 1f
-
- cmovge r9, r8, r12 // if .ge. 1d, then take shifted value
- bis r12, r31, r11 // set new ps
-
- mfpr r12, pt_intmask
- and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already)
-
-#ifdef SIMOS
- /*
- * Lance had space problems. We don't.
- */
- extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
- mfpr r29, pt_kgp // update gp
- mtpr r14, ev5__ipl // load the new IPL into Ibox
-#else
-// Moved the following three lines to sys_interrupt to make room for debug
-// extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
-// mfpr r29, pt_kgp // update gp
-
-// mtpr r14, ev5__ipl // load the new IPL into Ibox
-#endif
- br r31, sys_interrupt // Go handle interrupt
-
-
-
-// .sbttl "ITBMISS- Istream TBmiss Trap Entry Point"
-
-//+
-// ITBMISS - offset 0180
-// Entry:
-// Vectored into via hardware trap on Istream translation buffer miss.
-//
-// Function:
-// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid.
-// Can trap into DTBMISS_DOUBLE.
-// This routine can use the PALshadow registers r8, r9, and r10
-//
-//-
-
- HDW_VECTOR(PAL_ITB_MISS_ENTRY)
-Trap_Itbmiss:
-#if real_mm == 0
-
-
- // Simple 1-1 va->pa mapping
-
- nop // Pad to align to E1
- mfpr r8, exc_addr
-
- srl r8, page_offset_size_bits, r9
- sll r9, 32, r9
-
- lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
- mtpr r9, itb_pte // E1
-
- hw_rei_stall // Nital says I don't have to obey shadow wait rule here.
-#else
-
- // Real MM mapping
- nop
- mfpr r8, ev5__ifault_va_form // Get virtual address of PTE.
-
- nop
- mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss.
-
-pal_itb_ldq:
- ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss
- mtpr r10, exc_addr // Restore exc_address if there was a trap.
-
- mfpr r31, ev5__va // Unlock VA in case there was a double miss
- nop
-
- and r8, osfpte_m_foe, r25 // Look for FOE set.
- blbc r8, invalid_ipte_handler // PTE not valid.
-
- nop
- bne r25, foe_ipte_handler // FOE is set
-
- nop
- mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB.
-
- hw_rei_stall //
-
-#endif
-
-
-
-
-// .sbttl "DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point"
-
-//+
-// DTBMISS_SINGLE - offset 0200
-// Entry:
-// Vectored into via hardware trap on Dstream single translation buffer miss.
-//
-// Function:
-// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid.
-// Can trap into DTBMISS_DOUBLE.
-// This routine can use the PALshadow registers r8, r9, and r10
-//-
-
- HDW_VECTOR(PAL_DTB_MISS_ENTRY)
-Trap_Dtbmiss_Single:
-#if real_mm == 0
- // Simple 1-1 va->pa mapping
- mfpr r8, va // E0
- srl r8, page_offset_size_bits, r9
-
- sll r9, 32, r9
- lda r9, 0x3301(r9) // Make PTE, V set, all KRE, URE, KWE, UWE
-
- mtpr r9, dtb_pte // E0
- nop // Pad to align to E0
-
-
-
- mtpr r8, dtb_tag // E0
- nop
-
- nop // Pad tag write
- nop
-
- nop // Pad tag write
- nop
-
- hw_rei
-#else
- mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0.
- mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1.
-
-// DEBUGSTORE(0x45)
-// DEBUG_EXC_ADDR()
- // Real MM mapping
- mfpr r9, ev5__mm_stat // Get read/write bit. E0.
- mtpr r10, pt6 // Stash exc_addr away
-
-pal_dtb_ldq:
- ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss
- nop // Pad MF VA
-
- mfpr r10, ev5__va // Get original faulting VA for TB load. E0.
- nop
-
- mtpr r8, ev5__dtb_pte // Write DTB PTE part. E0.
- blbc r8, invalid_dpte_handler // Handle invalid PTE
-
- mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles.
- mfpr r10, pt6
-
- // Following 2 instructions take 2 cycles
- mtpr r10, exc_addr // Return linkage in case we trapped. E1.
- mfpr r31, pt0 // Pad the write to dtb_tag
-
- hw_rei // Done, return
-#endif
-
-
-
-
-// .sbttl "DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point"
-
-//+
-// DTBMISS_DOUBLE - offset 0280
-// Entry:
-// Vectored into via hardware trap on Double TBmiss from single miss flows.
-//
-// r8 - faulting VA
-// r9 - original MMstat
-// r10 - original exc_addr (both itb,dtb miss)
-// pt6 - original exc_addr (dtb miss flow only)
-// VA IPR - locked with original faulting VA
-//
-// Function:
-// Get PTE, if valid load TB and return.
-// If not valid then take TNV/ACV exception.
-//
-// pt4 and pt5 are reserved for this flow.
-//
-//
-//-
-
- HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY)
-Trap_Dtbmiss_double:
-#if ldvpte_bug_fix != 0
- mtpr r8, pt4 // save r8 to do exc_addr check
- mfpr r8, exc_addr
- blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy!
- mfpr r8, pt4 // restore r8
-#endif
- nop
- mtpr r22, pt5 // Get some scratch space. E1.
- // Due to virtual scheme, we can skip the first lookup and go
- // right to fetch of level 2 PTE
- sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA
- mtpr r21, pt4 // Get some scratch space. E1.
-
- srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8
- mfpr r21, pt_ptbr // Get physical address of the page table.
-
- nop
- addq r21, r22, r21 // Index into page table for level 2 PTE.
-
- sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA
- ldqp r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
-
- srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8
- blbc r21, double_pte_inv // Check for Invalid PTE.
-
- srl r21, 32, r21 // extract PFN from PTE
- sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to <seg3>*8
-
- addq r21, r22, r21 // Index into page table for level 3 PTE.
- nop
-
- ldqp r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
- blbc r21, double_pte_inv // Check for invalid PTE.
-
- mtpr r21, ev5__dtb_pte // Write the PTE. E0.
- mfpr r22, pt5 // Restore scratch register
-
- mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles.
- mfpr r21, pt4 // Restore scratch register
-
- nop // Pad write to tag.
- nop
-
- nop // Pad write to tag.
- nop
-
- hw_rei
-
-
-
-// .sbttl "UNALIGN -- Dstream unalign trap"
-//+
-// UNALIGN - offset 0300
-// Entry:
-// Vectored into via hardware trap on unaligned Dstream reference.
-//
-// Function:
-// Build stack frame
-// a0 <- Faulting VA
-// a1 <- Opcode
-// a2 <- src/dst register number
-// vector via entUna
-//-
-
- HDW_VECTOR(PAL_UNALIGN_ENTRY)
-Trap_Unalign:
-/* DEBUGSTORE(0x47)*/
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss
- mfpr r14, exc_addr // get pc
-
- srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits
- blbs r14, pal_pal_bug_check // Bugcheck if unaligned in PAL
-
- blbs r8, UNALIGN_NO_DISMISS // lsb only set on store or fetch_m
- // not set, must be a load
- and r13, 0x1F, r8 // isolate ra
-
- cmpeq r8, 0x1F, r8 // check for r31/F31
- bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault
-
-UNALIGN_NO_DISMISS:
- bis r11, r31, r12 // Save PS
- bge r25, UNALIGN_NO_DISMISS_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r12 // Set new PS
- mfpr r30, pt_ksp
-
-UNALIGN_NO_DISMISS_10_:
- mfpr r25, ev5__va // Unlock VA
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
-
- mtpr r25, pt0 // Stash VA
- stq r18, osfsf_a2(sp) // a2
-
- stq r11, osfsf_ps(sp) // save old ps
- srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode
-
- stq r29, osfsf_gp(sp) // save gp
- addq r14, 4, r14 // inc PC past the ld/st
-
- stq r17, osfsf_a1(sp) // a1
- and r25, mm_stat_m_opcode, r17// Clean opocde for a1
-
- stq r16, osfsf_a0(sp) // save regs
- mfpr r16, pt0 // a0 <- va/unlock
-
- stq r14, osfsf_pc(sp) // save pc
- mfpr r25, pt_entuna // get entry point
-
-
- bis r12, r31, r11 // update ps
- br r31, unalign_trap_cont
-
-
-
-
-// .sbttl "DFAULT - Dstream Fault Trap Entry Point"
-
-//+
-// DFAULT - offset 0380
-// Entry:
-// Vectored into via hardware trap on dstream fault or sign check error on DVA.
-//
-// Function:
-// Ignore faults on FETCH/FETCH_M
-// Check for DFAULT in PAL
-// Build stack frame
-// a0 <- Faulting VA
-// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW)
-// a2 <- R/W
-// vector via entMM
-//
-//-
- HDW_VECTOR(PAL_D_FAULT_ENTRY)
-Trap_Dfault:
-// DEBUGSTORE(0x48)
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r13, ev5__mm_stat // Get mmstat
- mfpr r8, exc_addr // get pc, preserve r14
-
- srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits
- blbs r8, dfault_in_pal
-
- bis r8, r31, r14 // move exc_addr to correct place
- bis r11, r31, r12 // Save PS
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- and r9, mm_stat_m_opcode, r9 // Clean all but opcode
-
- cmpeq r9, evx_opc_sync, r9 // Is the opcode fetch/fetchm?
- bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault
-
- //dismiss exception if load to r31/f31
- blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm
-
- // not a store or fetch, must be a load
- srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits
-
- and r9, 0x1F, r9 // isolate rnum
- nop
-
- cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31?
- bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault
-
-dfault_no_dismiss:
- and r13, 0xf, r13 // Clean extra bits in mm_stat
- bge r25, dfault_trap_cont // no stack swap needed if cm=kern
-
-
- mtpr r30, pt_usp // save user stack
- bis r31, r31, r12 // Set new PS
-
- mfpr r30, pt_ksp
- br r31, dfault_trap_cont
-
-
-
-
-
-// .sbttl "MCHK - Machine Check Trap Entry Point"
-
-//+
-// MCHK - offset 0400
-// Entry:
-// Vectored into via hardware trap on machine check.
-//
-// Function:
-//
-//-
-
- HDW_VECTOR(PAL_MCHK_ENTRY)
-Trap_Mchk:
- DEBUGSTORE(0x49)
- mtpr r31, ic_flush_ctl // Flush the Icache
- br r31, sys_machine_check
-
-
-
-
-// .sbttl "OPCDEC - Illegal Opcode Trap Entry Point"
-
-//+
-// OPCDEC - offset 0480
-// Entry:
-// Vectored into via hardware trap on illegal opcode.
-//
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-
- HDW_VECTOR(PAL_OPCDEC_ENTRY)
-Trap_Opcdec:
- DEBUGSTORE(0x4a)
-//simos DEBUG_EXC_ADDR()
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r14, exc_addr // get pc
- blbs r14, pal_pal_bug_check // check opcdec in palmode
-
- bis r11, r31, r12 // Save PS
- bge r25, TRAP_OPCDEC_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r12 // Set new PS
- mfpr r30, pt_ksp
-
-TRAP_OPCDEC_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- addq r14, 4, r14 // inc pc
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_opdec, r16 // set a0
-
- stq r11, osfsf_ps(sp) // save old ps
- mfpr r13, pt_entif // get entry point
-
- stq r18, osfsf_a2(sp) // a2
- stq r17, osfsf_a1(sp) // a1
-
- stq r29, osfsf_gp(sp) // save gp
- stq r14, osfsf_pc(sp) // save pc
-
- bis r12, r31, r11 // update ps
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei, E1
-
- mfpr r29, pt_kgp // get the kgp, E1
-
- hw_rei_spe // done, E1
-
-
-
-
-
-
-// .sbttl "ARITH - Arithmetic Exception Trap Entry Point"
-
-//+
-// ARITH - offset 0500
-// Entry:
-// Vectored into via hardware trap on arithmetic excpetion.
-//
-// Function:
-// Build stack frame
-// a0 <- exc_sum
-// a1 <- exc_mask
-// a2 <- unpred
-// vector via entArith
-//
-//-
- HDW_VECTOR(PAL_ARITH_ENTRY)
-Trap_Arith:
- DEBUGSTORE(0x4b)
- and r11, osfps_m_mode, r12 // get mode bit
- mfpr r31, ev5__va // unlock mbox
-
- bis r11, r31, r25 // save ps
- mfpr r14, exc_addr // get pc
-
- nop
- blbs r14, pal_pal_bug_check // arith trap from PAL
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- beq r12, TRAP_ARITH_10_ // if zero we are in kern now
-
- bis r31, r31, r25 // set the new ps
- mtpr r30, pt_usp // save user stack
-
- nop
- mfpr r30, pt_ksp // get kern stack
-
-TRAP_ARITH_10_: lda sp, 0-osfsf_c_size(sp) // allocate stack space
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- nop // Pad current mode write and stq
- mfpr r13, ev5__exc_sum // get the exc_sum
-
- mfpr r12, pt_entarith
- stq r14, osfsf_pc(sp) // save pc
-
- stq r17, osfsf_a1(sp)
- mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
-
- stq r11, osfsf_ps(sp) // save ps
- bis r25, r31, r11 // set new ps
-
- stq r16, osfsf_a0(sp) // save regs
- srl r13, exc_sum_v_swc, r16// shift data to correct position
-
- stq r18, osfsf_a2(sp)
-// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow
- mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask
-
- stq r29, osfsf_gp(sp)
- mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1
-
- mfpr r29, pt_kgp // get the kern gp - E1
- hw_rei_spe // done - E1
-
-
-
-
-
-
-// .sbttl "FEN - Illegal Floating Point Operation Trap Entry Point"
-
-//+
-// FEN - offset 0580
-// Entry:
-// Vectored into via hardware trap on illegal FP op.
-//
-// Function:
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-
- HDW_VECTOR(PAL_FEN_ENTRY)
-Trap_Fen:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r14, exc_addr // get pc
- blbs r14, pal_pal_bug_check // check opcdec in palmode
-
- mfpr r13, ev5__icsr
- nop
-
- bis r11, r31, r12 // Save PS
- bge r25, TRAP_FEN_10_ // no stack swap needed if cm=kern
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r12 // Set new PS
- mfpr r30, pt_ksp
-
-TRAP_FEN_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0
-
-
- stq r16, osfsf_a0(sp) // save regs
- mfpr r13, pt_entif // get entry point
-
- stq r18, osfsf_a2(sp) // a2
- stq r11, osfsf_ps(sp) // save old ps
-
- stq r29, osfsf_gp(sp) // save gp
- bis r12, r31, r11 // set new ps
-
- stq r17, osfsf_a1(sp) // a1
- blbs r25,fen_to_opcdec // If FP is enabled, this is really OPCDEC.
-
- bis r31, osf_a0_fen, r16 // set a0
- stq r14, osfsf_pc(sp) // save pc
-
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei -E1
-
- mfpr r29, pt_kgp // get the kgp -E1
-
- hw_rei_spe // done -E1
-
-// FEN trap was taken, but the fault is really opcdec.
- ALIGN_BRANCH
-fen_to_opcdec:
- addq r14, 4, r14 // save PC+4
- bis r31, osf_a0_opdec, r16 // set a0
-
- stq r14, osfsf_pc(sp) // save pc
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei
-
- mfpr r29, pt_kgp // get the kgp
- hw_rei_spe // done
-
-
-
-// .sbttl "Misc handlers"
- // Start area for misc code.
-//+
-//dfault_trap_cont
-// A dfault trap has been taken. The sp has been updated if necessary.
-// Push a stack frame a vector via entMM.
-//
-// Current state:
-// r12 - new PS
-// r13 - MMstat
-// VA - locked
-//
-//-
- ALIGN_BLOCK
-dfault_trap_cont:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r25, ev5__va // Fetch VA/unlock
-
- stq r18, osfsf_a2(sp) // a2
- and r13, 1, r18 // Clean r/w bit for a2
-
- stq r16, osfsf_a0(sp) // save regs
- bis r25, r31, r16 // a0 <- va
-
- stq r17, osfsf_a1(sp) // a1
- srl r13, 1, r17 // shift fault bits to right position
-
- stq r11, osfsf_ps(sp) // save old ps
- bis r12, r31, r11 // update ps
-
- stq r14, osfsf_pc(sp) // save pc
- mfpr r25, pt_entmm // get entry point
-
- stq r29, osfsf_gp(sp) // save gp
- cmovlbs r17, 1, r17 // a2. acv overrides fox.
-
- mtpr r25, exc_addr // load exc_addr with entMM
- // 1 cycle to hw_rei
- mfpr r29, pt_kgp // get the kgp
-
- hw_rei_spe // done
-
-//+
-//unalign_trap_cont
-// An unalign trap has been taken. Just need to finish up a few things.
-//
-// Current state:
-// r25 - entUna
-// r13 - shifted MMstat
-//
-//-
- ALIGN_BLOCK
-unalign_trap_cont:
- mtpr r25, exc_addr // load exc_addr with entUna
- // 1 cycle to hw_rei
-
-
- mfpr r29, pt_kgp // get the kgp
- and r13, mm_stat_m_ra, r18 // Clean Ra for a2
-
- hw_rei_spe // done
-
-
-
-//+
-// dfault_in_pal
-// Dfault trap was taken, exc_addr points to a PAL PC.
-// r9 - mmstat<opcode> right justified
-// r8 - exception address
-//
-// These are the cases:
-// opcode was STQ -- from a stack builder, KSP not valid halt
-// r14 - original exc_addr
-// r11 - original PS
-// opcode was STL_C -- rti or retsys clear lock_flag by stack write,
-// KSP not valid halt
-// r11 - original PS
-// r14 - original exc_addr
-// opcode was LDQ -- retsys or rti stack read, KSP not valid halt
-// r11 - original PS
-// r14 - original exc_addr
-// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables
-// r10 - original exc_addr
-// r11 - original PS
-//
-//
-//-
- ALIGN_BLOCK
-dfault_in_pal:
- DEBUGSTORE(0x50)
- bic r8, 3, r8 // Clean PC
- mfpr r9, pal_base
-
- mfpr r31, va // unlock VA
-#if real_mm != 0
- // if not real_mm, should never get here from miss flows
-
- subq r9, r8, r8 // pal_base - offset
-
- lda r9, pal_itb_ldq-pal_base(r8)
- nop
-
- beq r9, dfault_do_bugcheck
- lda r9, pal_dtb_ldq-pal_base(r8)
-
- beq r9, dfault_do_bugcheck
-#endif
-
-//
-// KSP invalid halt case --
-ksp_inval_halt:
- DEBUGSTORE(76)
- bic r11, osfps_m_mode, r11 // set ps to kernel mode
- mtpr r0, pt0
-
- mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode
- mtpr r31, ips
-
- mtpr r14, exc_addr // Set PC to instruction that caused trouble
-//orig pvc_jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
-
- lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt
- br r31, sys_enter_console // enter the console
-
- ALIGN_BRANCH
-dfault_do_bugcheck:
- bis r10, r31, r14 // bugcheck expects exc_addr in r14
- br r31, pal_pal_bug_check
-
-
- ALIGN_BLOCK
-//+
-// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31
-// On entry -
-// r14 - exc_addr
-// VA is locked
-//
-//-
-dfault_fetch_ldr31_err:
- mtpr r11, ev5__dtb_cm
- mtpr r11, ev5__ps // Make sure ps hasn't changed
-
- mfpr r31, va // unlock the mbox
- addq r14, 4, r14 // inc the pc to skip the fetch
-
- mtpr r14, exc_addr // give ibox new PC
- mfpr r31, pt0 // pad exc_addr write
-
- hw_rei
-
-
-
- ALIGN_BLOCK
-//+
-// sys_from_kern
-// callsys from kernel mode - OS bugcheck machine check
-//
-//-
-sys_from_kern:
- mfpr r14, exc_addr // PC points to call_pal
- subq r14, 4, r14
-
- lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code
- br r31, pal_pal_mchk
-
-
-// .sbttl "Continuation of long call_pal flows"
- ALIGN_BLOCK
-//+
-// wrent_tbl
-// Table to write *int in paltemps.
-// 4 instructions/entry
-// r16 has new value
-//
-//-
-wrent_tbl:
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entint
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entarith
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entmm
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entif
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entuna
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
-
-//orig pvc_jsr wrent, dest=1
- nop
- mtpr r16, pt_entsys
-
- mfpr r31, pt0 // Pad for mt->mf paltemp rule
- hw_rei
-
- ALIGN_BLOCK
-//+
-// tbi_tbl
-// Table to do tbi instructions
-// 4 instructions per entry
-//-
-tbi_tbl:
- // -2 tbia
-//orig pvc_jsr tbi, dest=1
- mtpr r31, ev5__dtb_ia // Flush DTB
- mtpr r31, ev5__itb_ia // Flush ITB
-
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush // Flush Icache
-#else
-
- hw_rei_stall
-#endif
-
- nop // Pad table
-
- // -1 tbiap
-//orig pvc_jsr tbi, dest=1
- mtpr r31, ev5__dtb_iap // Flush DTB
- mtpr r31, ev5__itb_iap // Flush ITB
-
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush // Flush Icache
-#else
-
- hw_rei_stall
-#endif
-
- nop // Pad table
-
-
- // 0 unused
-//orig pvc_jsr tbi, dest=1
- hw_rei // Pad table
- nop
- nop
- nop
-
-
- // 1 tbisi
-//orig pvc_jsr tbi, dest=1
-#if icflush_on_tbix != 0
-
-
-
- nop
- br r31, pal_ic_flush_and_tbisi // Flush Icache
- nop
- nop // Pad table
-#else
-
- nop
- nop
- mtpr r17, ev5__itb_is // Flush ITB
- hw_rei_stall
-#endif
-
-
-
- // 2 tbisd
-//orig pvc_jsr tbi, dest=1
- mtpr r17, ev5__dtb_is // Flush DTB.
- nop
-
- nop
- hw_rei_stall
-
-
- // 3 tbis
-//orig pvc_jsr tbi, dest=1
- mtpr r17, ev5__dtb_is // Flush DTB
-#if icflush_on_tbix != 0
-
-
- br r31, pal_ic_flush_and_tbisi // Flush Icache and ITB
-#else
- br r31, tbi_finish
- ALIGN_BRANCH
-tbi_finish:
- mtpr r17, ev5__itb_is // Flush ITB
- hw_rei_stall
-#endif
-
-
-
- ALIGN_BLOCK
-//+
-// bpt_bchk_common:
-// Finish up the bpt/bchk instructions
-//-
-bpt_bchk_common:
- stq r18, osfsf_a2(sp) // a2
- mfpr r13, pt_entif // get entry point
-
- stq r12, osfsf_ps(sp) // save old ps
- stq r14, osfsf_pc(sp) // save pc
-
- stq r29, osfsf_gp(sp) // save gp
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei
-
- mfpr r29, pt_kgp // get the kgp
-
-
- hw_rei_spe // done
-
-
- ALIGN_BLOCK
-//+
-// rti_to_user
-// Finish up the rti instruction
-//-
-rti_to_user:
- mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
- mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
-
- mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles
- mtpr r25, pt_ksp // save off incase RTI to user
-
- mfpr r30, pt_usp
- hw_rei_spe // and back
-
-
- ALIGN_BLOCK
-//+
-// rti_to_kern
-// Finish up the rti instruction
-//-
-rti_to_kern:
- and r12, osfps_m_ipl, r11 // clean ps
- mfpr r12, pt_intmask // get int mask
-
- extbl r12, r11, r12 // get mask for this ipl
- mtpr r25, pt_ksp // save off incase RTI to user
-
- mtpr r12, ev5__ipl // set the new ipl.
- or r25, r31, sp // sp
-
-// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals
- hw_rei
-
- ALIGN_BLOCK
-//+
-// swpctx_cont
-// Finish up the swpctx instruction
-//-
-
-swpctx_cont:
-#if ev5_p1 != 0
-
-
- bic r25, r24, r25 // clean icsr<FPE>
- get_impure r8 // get impure pointer
-
- sll r12, icsr_v_fpe, r12 // shift new fen to pos
- fix_impure_ipr r8 // adjust impure pointer
-
- restore_reg1 pmctr_ctl, r8, r8, ipr=1 // "ldqp" - get pmctr_ctl bits
- srl r23, 32, r24 // move asn to low asn pos
-
- ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
- srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
-
- or r25, r12, r25 // icsr with new fen
- sll r24, itb_asn_v_asn, r12
-
-#else
-
- bic r25, r24, r25 // clean icsr<FPE,PMP>
- sll r12, icsr_v_fpe, r12 // shift new fen to pos
-
- ldqp r14, osfpcb_q_mmptr(r16)// get new mmptr
- srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
-
- or r25, r12, r25 // icsr with new fen
- srl r23, 32, r24 // move asn to low asn pos
-
- and r22, 1, r22
- sll r24, itb_asn_v_asn, r12
-
- sll r22, icsr_v_pmp, r22
- nop
-
- or r25, r22, r25 // icsr with new pme
-#endif
-
- sll r24, dtb_asn_v_asn, r24
-
- subl r23, r13, r13 // gen new cc offset
- mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4
-
- mtpr r24, dtb_asn // Load up new ASN
- mtpr r25, icsr // write the icsr
-
- sll r14, page_offset_size_bits, r14 // Move PTBR into internal position.
- ldqp r25, osfpcb_q_usp(r16) // get new usp
-
- insll r13, 4, r13 // >> 32
-// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
- mtpr r14, pt_ptbr // load the new ptbr
-
- mtpr r13, cc // set new offset
- ldqp r30, osfpcb_q_ksp(r16) // get new ksp
-
-// pvc_violate 379 // ldqp can't trap except replay. only problem if mf same ipr in same shadow
- mtpr r25, pt_usp // save usp
-
-#if ev5_p1 != 0
-
-
- blbc r8, no_pm_change // if monitoring all processes -- no need to change pm
-
- // otherwise, monitoring select processes - update pm
- lda r25, 0x3F(r31)
- cmovlbc r22, r31, r8 // if pme set, disable counters, otherwise use saved encodings
-
- sll r25, pmctr_v_ctl2, r25 // create ctl field bit mask
- mfpr r22, ev5__pmctr
-
- and r8, r25, r8 // mask new ctl value
- bic r22, r25, r22 // clear ctl field in pmctr
-
- or r8, r22, r8
- mtpr r8, ev5__pmctr
-
-no_pm_change:
-#endif
-
-
-#if osf_chm_fix != 0
-
-
- p4_fixup_hw_rei_stall // removes this section for Pass 4 by placing a hw_rei_stall here
-
-#if build_fixed_image != 0
-
-
- hw_rei_stall
-#else
-
- mfpr r9, pt_pcbb // get FEN
-#endif
-
- ldqp r9, osfpcb_q_fen(r9)
- blbc r9, no_pm_change_10_ // skip if FEN disabled
-
- mb // ensure no outstanding fills
- lda r12, 1<<dc_mode_v_dc_ena(r31)
- mtpr r12, dc_mode // turn dcache on so we can flush it
- nop // force correct slotting
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
- mfpr r31, pt0 // no mbox instructions in 1,2,3,4
-
- lda r8, 0(r31) // flood the dcache with junk data
-no_pm_change_5_: ldqp r31, 0(r8)
- lda r8, 0x20(r8) // touch each cache block
- srl r8, 13, r9
- blbc r9, no_pm_change_5_
-
- mb // ensure no outstanding fills
- mtpr r31, dc_mode // turn the dcache back off
- nop // force correct slotting
- mfpr r31, pt0 // no hw_rei_stall in 0,1
-#endif
-
-
-no_pm_change_10_: hw_rei_stall // back we go
-
- ALIGN_BLOCK
-//+
-// swppal_cont - finish up the swppal call_pal
-//-
-
-swppal_cont:
- mfpr r2, pt_misc // get misc bits
- sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit
- or r2, r0, r2 // set the bit
- mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel)
- mtpr r2, pt_misc // update the chip
-
- or r3, r31, r4
- mfpr r3, pt_impure // pass pointer to the impure area in r3
-//orig fix_impure_ipr r3 // adjust impure pointer for ipr read
-//orig restore_reg1 bc_ctl, r1, r3, ipr=1 // pass cns_bc_ctl in r1
-//orig restore_reg1 bc_config, r2, r3, ipr=1 // pass cns_bc_config in r2
-//orig unfix_impure_ipr r3 // restore impure pointer
- lda r3, CNS_Q_IPR(r3)
- RESTORE_SHADOW(r1,CNS_Q_BC_CTL,r3);
- RESTORE_SHADOW(r1,CNS_Q_BC_CFG,r3);
- lda r3, -CNS_Q_IPR(r3)
-
- or r31, r31, r0 // set status to success
-// pvc_violate 1007
- jmp r31, (r4) // and call our friend, it's her problem now
-
-
-swppal_fail:
- addq r0, 1, r0 // set unknown pal or not loaded
- hw_rei // and return
-
-
-// .sbttl "Memory management"
-
- ALIGN_BLOCK
-//+
-//foe_ipte_handler
-// IFOE detected on level 3 pte, sort out FOE vs ACV
-//
-// on entry:
-// with
-// R8 = pte
-// R10 = pc
-//
-// Function
-// Determine TNV vs ACV vs FOE. Build stack and dispatch
-// Will not be here if TNV.
-//-
-
-foe_ipte_handler:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
- srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
- nop
-
-foe_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0>
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
-
- or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack
- mfpr r13, pt_entmm // get entry point
-
- stq r16, osfsf_a0(sp) // a0
- or r14, r31, r16 // pass pc/va as a0
-
- stq r17, osfsf_a1(sp) // a1
- nop
-
- stq r18, osfsf_a2(sp) // a2
- lda r17, mmcsr_c_acv(r31) // assume ACV
-
- stq r16, osfsf_pc(sp) // save pc
- cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE
-
- stq r12, osfsf_ps(sp) // save ps
- subq r31, 1, r18 // pass flag of istream as a2
-
- stq r29, osfsf_gp(sp)
- mtpr r13, exc_addr // set vector address
-
- mfpr r29, pt_kgp // load kgp
- hw_rei_spe // out to exec
-
- ALIGN_BLOCK
-//+
-//invalid_ipte_handler
-// TNV detected on level 3 pte, sort out TNV vs ACV
-//
-// on entry:
-// with
-// R8 = pte
-// R10 = pc
-//
-// Function
-// Determine TNV vs ACV. Build stack and dispatch.
-//-
-
-invalid_ipte_handler:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
- srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
- nop
-
-invalid_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0>
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
-
- or r10, r31, r14 // Save pc/va in case TBmiss on stack
- mfpr r13, pt_entmm // get entry point
-
- stq r16, osfsf_a0(sp) // a0
- or r14, r31, r16 // pass pc/va as a0
-
- stq r17, osfsf_a1(sp) // a1
- nop
-
- stq r18, osfsf_a2(sp) // a2
- and r25, 1, r17 // Isolate kre
-
- stq r16, osfsf_pc(sp) // save pc
- xor r17, 1, r17 // map to acv/tnv as a1
-
- stq r12, osfsf_ps(sp) // save ps
- subq r31, 1, r18 // pass flag of istream as a2
-
- stq r29, osfsf_gp(sp)
- mtpr r13, exc_addr // set vector address
-
- mfpr r29, pt_kgp // load kgp
- hw_rei_spe // out to exec
-
-
-
-
- ALIGN_BLOCK
-//+
-//invalid_dpte_handler
-// INVALID detected on level 3 pte, sort out TNV vs ACV
-//
-// on entry:
-// with
-// R10 = va
-// R8 = pte
-// R9 = mm_stat
-// PT6 = pc
-//
-// Function
-// Determine TNV vs ACV. Build stack and dispatch
-//-
-
-
-invalid_dpte_handler:
- mfpr r12, pt6
- blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode
-
- bis r12, r31, r14 // save PC in case of tbmiss or fault
- srl r9, mm_stat_v_opcode, r25 // shift opc to <0>
-
- mtpr r11, pt0 // Save PS for stack write
- and r25, mm_stat_m_opcode, r25 // isolate opcode
-
- cmpeq r25, evx_opc_sync, r25 // is it FETCH/FETCH_M?
- blbs r25, nmiss_fetch_ldr31_err // yes
-
- //dismiss exception if load to r31/f31
- blbs r9, invalid_dpte_no_dismiss // mm_stat<0> set on store or fetchm
-
- // not a store or fetch, must be a load
- srl r9, mm_stat_v_ra, r25 // Shift rnum to low bits
-
- and r25, 0x1F, r25 // isolate rnum
- nop
-
- cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31?
- bne r25, nmiss_fetch_ldr31_err // Yes, dismiss the fault
-
-invalid_dpte_no_dismiss:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- bge r25, invalid_dpte_no_dismiss_10_ // no stack swap needed if cm=kern
-
- srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-invalid_dpte_no_dismiss_10_: srl r8, osfpte_v_kre, r12 // get kre to <0>
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
-
- or r10, r31, r25 // Save va in case TBmiss on stack
- and r9, 1, r13 // save r/w flag
-
- stq r16, osfsf_a0(sp) // a0
- or r25, r31, r16 // pass va as a0
-
- stq r17, osfsf_a1(sp) // a1
- or r31, mmcsr_c_acv, r17 // assume acv
-
- srl r12, osfpte_v_kwe-osfpte_v_kre, r25 // get write enable to <0>
- stq r29, osfsf_gp(sp)
-
- stq r18, osfsf_a2(sp) // a2
- cmovlbs r13, r25, r12 // if write access move acv based on write enable
-
- or r13, r31, r18 // pass flag of dstream access and read vs write
- mfpr r25, pt0 // get ps
-
- stq r14, osfsf_pc(sp) // save pc
- mfpr r13, pt_entmm // get entry point
-
- stq r25, osfsf_ps(sp) // save ps
- mtpr r13, exc_addr // set vector address
-
- mfpr r29, pt_kgp // load kgp
- cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv
-
- hw_rei_spe // out to exec
-
-//+
-//
-// We come here if we are erring on a dtb_miss, and the instr is a
-// fetch, fetch_m, of load to r31/f31.
-// The PC is incremented, and we return to the program.
-// essentially ignoring the instruction and error.
-//
-//-
- ALIGN_BLOCK
-nmiss_fetch_ldr31_err:
- mfpr r12, pt6
- addq r12, 4, r12 // bump pc to pc+4
-
- mtpr r12, exc_addr // and set entry point
- mfpr r31, pt0 // pad exc_addr write
-
- hw_rei //
-
- ALIGN_BLOCK
-//+
-// double_pte_inv
-// We had a single tbmiss which turned into a double tbmiss which found
-// an invalid PTE. Return to single miss with a fake pte, and the invalid
-// single miss flow will report the error.
-//
-// on entry:
-// r21 PTE
-// r22 available
-// VA IPR locked with original fault VA
-// pt4 saved r21
-// pt5 saved r22
-// pt6 original exc_addr
-//
-// on return to tbmiss flow:
-// r8 fake PTE
-//
-//
-//-
-double_pte_inv:
- srl r21, osfpte_v_kre, r21 // get the kre bit to <0>
- mfpr r22, exc_addr // get the pc
-
- lda r22, 4(r22) // inc the pc
- lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set
-
- cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0
- mtpr r22, exc_addr // set for rei
-
- mfpr r21, pt4 // restore regs
- mfpr r22, pt5 // restore regs
-
- hw_rei // back to tb miss
-
- ALIGN_BLOCK
-//+
-//tnv_in_pal
-// The only places in pal that ld or store are the
-// stack builders, rti or retsys. Any of these mean we
-// need to take a ksp not valid halt.
-//
-//-
-tnv_in_pal:
-
-
- br r31, ksp_inval_halt
-
-
-// .sbttl "Icache flush routines"
-
- ALIGN_BLOCK
-//+
-// Common Icache flush routine.
-//
-//
-//-
-pal_ic_flush:
- nop
- mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
- nop
- nop
-
-// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20)
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 10
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 20
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 30
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 40
-
- nop
- nop
-
-one_cycle_and_hw_rei:
- nop
- nop
-
- hw_rei_stall
-
-#if icflush_on_tbix != 0
-
-
- ALIGN_BLOCK
-
-//+
-// Common Icache flush and ITB invalidate single routine.
-// ITBIS and hw_rei_stall must be in same octaword.
-// r17 - has address to invalidate
-//
-//-
-PAL_IC_FLUSH_AND_TBISI:
- nop
- mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
- nop
- nop
-
-// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20)
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 10
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 20
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 30
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop // 40
-
-
- nop
- nop
-
- nop
- nop
-
- // A quadword is 64 bits, so an octaword is 128 bits -> 16 bytes -> 4 instructions
- // 44 nops plus 4 instructions before it is 48 instructions.
- // Since this routine started on a 32-byte (8 instruction) boundary,
- // the following 2 instructions will be in the same octword as required.
-// ALIGN_BRANCH
- mtpr r17, ev5__itb_is // Flush ITB
- hw_rei_stall
-
-#endif
-
- ALIGN_BLOCK
-//+
-//osfpal_calpal_opcdec
-// Here for all opcdec CALL_PALs
-//
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-
-osfpal_calpal_opcdec:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r14, exc_addr // get pc
- nop
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, osfpal_calpal_opcdec_10_ // no stack swap needed if cm=kern
-
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-osfpal_calpal_opcdec_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- nop
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_opdec, r16 // set a0
-
- stq r18, osfsf_a2(sp) // a2
- mfpr r13, pt_entif // get entry point
-
- stq r12, osfsf_ps(sp) // save old ps
- stq r17, osfsf_a1(sp) // a1
-
- stq r14, osfsf_pc(sp) // save pc
- nop
-
- stq r29, osfsf_gp(sp) // save gp
- mtpr r13, exc_addr // load exc_addr with entIF
- // 1 cycle to hw_rei
-
- mfpr r29, pt_kgp // get the kgp
-
-
- hw_rei_spe // done
-
-
-
-
-
-//+
-//pal_update_pcb
-// Update the PCB with the current SP, AST, and CC info
-//
-// r0 - return linkage
-//-
- ALIGN_BLOCK
-
-pal_update_pcb:
- mfpr r12, pt_pcbb // get pcbb
- and r11, osfps_m_mode, r25 // get mode
- beq r25, pal_update_pcb_10_ // in kern? no need to update user sp
- mtpr r30, pt_usp // save user stack
- stqp r30, osfpcb_q_usp(r12) // store usp
- br r31, pal_update_pcb_20_ // join common
-pal_update_pcb_10_: stqp r30, osfpcb_q_ksp(r12) // store ksp
-pal_update_pcb_20_: rpcc r13 // get cyccounter
- srl r13, 32, r14 // move offset
- addl r13, r14, r14 // merge for new time
- stlp r14, osfpcb_l_cc(r12) // save time
-
-//orig pvc_jsr updpcb, bsr=1, dest=1
- ret r31, (r0)
-
-
-
-#if remove_save_state == 0
-
-// .sbttl "PAL_SAVE_STATE"
-//+
-//
-// Pal_save_state
-//
-// Function
-// All chip state saved, all PT's, SR's FR's, IPR's
-//
-//
-// Regs' on entry...
-//
-// R0 = halt code
-// pt0 = r0
-// R1 = pointer to impure
-// pt4 = r1
-// R3 = return addr
-// pt5 = r3
-//
-// register usage:
-// r0 = halt_code
-// r1 = addr of impure area
-// r3 = return_address
-// r4 = scratch
-//
-//-
-
-
- ALIGN_BLOCK
- .globl pal_save_state
-pal_save_state:
-//
-//
-// start of implementation independent save routine
-//
-// the impure area is larger than the addressibility of hw_ld and hw_st
-// therefore, we need to play some games: The impure area
-// is informally divided into the "machine independent" part and the
-// "machine dependent" part. The state that will be saved in the
-// "machine independent" part are gpr's, fpr's, hlt, flag, mchkflag (use (un)fix_impure_gpr macros).
-// All others will be in the "machine dependent" part (use (un)fix_impure_ipr macros).
-// The impure pointer will need to be adjusted by a different offset for each. The store/restore_reg
-// macros will automagically adjust the offset correctly.
-//
-
-// The distributed code is commented out and followed by corresponding SRC code.
-// Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0)
-
-//orig fix_impure_gpr r1 // adjust impure area pointer for stores to "gpr" part of impure area
- lda r1, 0x200(r1) // Point to center of CPU segment
-//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag
- SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag
-//orig store_reg1 hlt, r0, r1, ipr=1
- SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code
-
- mfpr r0, pt0 // get r0 back //orig
-//orig store_reg1 0, r0, r1 // save r0
- SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0
-
- mfpr r0, pt4 // get r1 back //orig
-//orig store_reg1 1, r0, r1 // save r1
- SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1
-
-//orig store_reg 2 // save r2
- SAVE_GPR(r2,CNS_Q_GPR+0x10,r1) // Save r2
-
- mfpr r0, pt5 // get r3 back //orig
-//orig store_reg1 3, r0, r1 // save r3
- SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3
-
- // reason code has been saved
- // r0 has been saved
- // r1 has been saved
- // r2 has been saved
- // r3 has been saved
- // pt0, pt4, pt5 have been lost
-
- //
- // Get out of shadow mode
- //
-
- mfpr r2, icsr // Get icsr //orig
-//orig ldah r0, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
- ldah r0, (1<<(icsr_v_sde-16))(r31)
- bic r2, r0, r0 // ICSR with SDE clear //orig
- mtpr r0, icsr // Turn off SDE //orig
-
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
-
-
- // save integer regs R4-r31
-//orig #define t 4
-//orig .repeat 28
-//orig store_reg \t
-//orig #define t t + 1
-//orig .endr
- SAVE_GPR(r4,CNS_Q_GPR+0x20,r1)
- SAVE_GPR(r5,CNS_Q_GPR+0x28,r1)
- SAVE_GPR(r6,CNS_Q_GPR+0x30,r1)
- SAVE_GPR(r7,CNS_Q_GPR+0x38,r1)
- SAVE_GPR(r8,CNS_Q_GPR+0x40,r1)
- SAVE_GPR(r9,CNS_Q_GPR+0x48,r1)
- SAVE_GPR(r10,CNS_Q_GPR+0x50,r1)
- SAVE_GPR(r11,CNS_Q_GPR+0x58,r1)
- SAVE_GPR(r12,CNS_Q_GPR+0x60,r1)
- SAVE_GPR(r13,CNS_Q_GPR+0x68,r1)
- SAVE_GPR(r14,CNS_Q_GPR+0x70,r1)
- SAVE_GPR(r15,CNS_Q_GPR+0x78,r1)
- SAVE_GPR(r16,CNS_Q_GPR+0x80,r1)
- SAVE_GPR(r17,CNS_Q_GPR+0x88,r1)
- SAVE_GPR(r18,CNS_Q_GPR+0x90,r1)
- SAVE_GPR(r19,CNS_Q_GPR+0x98,r1)
- SAVE_GPR(r20,CNS_Q_GPR+0xA0,r1)
- SAVE_GPR(r21,CNS_Q_GPR+0xA8,r1)
- SAVE_GPR(r22,CNS_Q_GPR+0xB0,r1)
- SAVE_GPR(r23,CNS_Q_GPR+0xB8,r1)
- SAVE_GPR(r24,CNS_Q_GPR+0xC0,r1)
- SAVE_GPR(r25,CNS_Q_GPR+0xC8,r1)
- SAVE_GPR(r26,CNS_Q_GPR+0xD0,r1)
- SAVE_GPR(r27,CNS_Q_GPR+0xD8,r1)
- SAVE_GPR(r28,CNS_Q_GPR+0xE0,r1)
- SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1)
- SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1)
- SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1)
-
- // save all paltemp regs except pt0
-
-//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores
-//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores
-//orig #define t 1
-//orig .repeat 23
-//orig store_reg \t , pal=1
-//orig #define t t + 1
-//orig .endr
-
- lda r1, -0x200(r1) // Restore the impure base address.
- lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area.
- SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle
- SAVE_IPR(pt1,CNS_Q_PT+0x08,r1)
- SAVE_IPR(pt2,CNS_Q_PT+0x10,r1)
- SAVE_IPR(pt3,CNS_Q_PT+0x18,r1)
- SAVE_IPR(pt4,CNS_Q_PT+0x20,r1)
- SAVE_IPR(pt5,CNS_Q_PT+0x28,r1)
- SAVE_IPR(pt6,CNS_Q_PT+0x30,r1)
- SAVE_IPR(pt7,CNS_Q_PT+0x38,r1)
- SAVE_IPR(pt8,CNS_Q_PT+0x40,r1)
- SAVE_IPR(pt9,CNS_Q_PT+0x48,r1)
- SAVE_IPR(pt10,CNS_Q_PT+0x50,r1)
- SAVE_IPR(pt11,CNS_Q_PT+0x58,r1)
- SAVE_IPR(pt12,CNS_Q_PT+0x60,r1)
- SAVE_IPR(pt13,CNS_Q_PT+0x68,r1)
- SAVE_IPR(pt14,CNS_Q_PT+0x70,r1)
- SAVE_IPR(pt15,CNS_Q_PT+0x78,r1)
- SAVE_IPR(pt16,CNS_Q_PT+0x80,r1)
- SAVE_IPR(pt17,CNS_Q_PT+0x88,r1)
- SAVE_IPR(pt18,CNS_Q_PT+0x90,r1)
- SAVE_IPR(pt19,CNS_Q_PT+0x98,r1)
- SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1)
- SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1)
- SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1)
- SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1)
-
- // Restore shadow mode
- mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write) //orig
- mfpr r31, pt0 //orig
- mtpr r2, icsr // Restore original ICSR //orig
-
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
-
- // save all integer shadow regs
-
-//orig #define t 8
-//orig .repeat 7
-//orig store_reg \t, shadow=1
-//orig #define t t + 1
-//orig .endr
-//orig store_reg 25, shadow=1
-
- SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code
- SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1)
- SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1)
- SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1)
- SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1)
- SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1)
- SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1)
- SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1)
-
-//orig store_reg exc_addr, ipr=1 // save ipr
-//orig store_reg pal_base, ipr=1 // save ipr
-//orig store_reg mm_stat, ipr=1 // save ipr
-//orig store_reg va, ipr=1 // save ipr
-//orig store_reg icsr, ipr=1 // save ipr
-//orig store_reg ipl, ipr=1 // save ipr
-//orig store_reg ps, ipr=1 // save ipr
-//orig store_reg itb_asn, ipr=1 // save ipr
-//orig store_reg aster, ipr=1 // save ipr
-//orig store_reg astrr, ipr=1 // save ipr
-//orig store_reg sirr, ipr=1 // save ipr
-//orig store_reg isr, ipr=1 // save ipr
-//orig store_reg ivptbr, ipr=1 // save ipr
-//orig store_reg mcsr, ipr=1 // save ipr
-//orig store_reg dc_mode, ipr=1 // save ipr
-
- SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1)
- SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1)
- SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1)
- SAVE_IPR(va,CNS_Q_VA,r1)
- SAVE_IPR(icsr,CNS_Q_ICSR,r1)
- SAVE_IPR(ipl,CNS_Q_IPL,r1)
- SAVE_IPR(ips,CNS_Q_IPS,r1)
- SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1)
- SAVE_IPR(aster,CNS_Q_ASTER,r1)
- SAVE_IPR(astrr,CNS_Q_ASTRR,r1)
- SAVE_IPR(sirr,CNS_Q_SIRR,r1)
- SAVE_IPR(isr,CNS_Q_ISR,r1)
- SAVE_IPR(iVptBr,CNS_Q_IVPTBR,r1)
- SAVE_IPR(mcsr,CNS_Q_MCSR,r1)
- SAVE_IPR(dcMode,CNS_Q_DC_MODE,r1)
-
-//orig pvc_violate 379 // mf maf_mode after a store ok (pvc doesn't distinguish ld from st)
-//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for
-//orig // PVC violation applies only to
-pvc$osf35$379: // loads. HW_ST ok here, so ignore
- SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2
-
-
- //the following iprs are informational only -- will not be restored
-
-//orig store_reg icperr_stat, ipr=1
-//orig store_reg pmctr, ipr=1
-//orig store_reg intid, ipr=1
-//orig store_reg exc_sum, ipr=1
-//orig store_reg exc_mask, ipr=1
-//orig ldah r14, 0xfff0(r31)
-//orig zap r14, 0xE0, r14 // Get Cbox IPR base
-//orig nop // pad mf dcperr_stat out of shadow of last store
-//orig nop
-//orig nop
-//orig store_reg dcperr_stat, ipr=1
-
- SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1)
- SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1)
- SAVE_IPR(intId,CNS_Q_INT_ID,r1)
- SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1)
- SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1)
- ldah r14, 0xFFF0(zero)
- zap r14, 0xE0, r14 // Get base address of CBOX IPRs
- NOP // Pad mfpr dcPerr out of shadow of
- NOP // last store
- NOP
- SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1)
-
- // read cbox ipr state
-
-//orig mb
-//orig ldqp r2, ev5__sc_ctl(r14)
-//orig ldqp r13, ld_lock(r14)
-//orig ldqp r4, ev5__sc_addr(r14)
-//orig ldqp r5, ev5__ei_addr(r14)
-//orig ldqp r6, ev5__bc_tag_addr(r14)
-//orig ldqp r7, ev5__fill_syn(r14)
-//orig bis r5, r4, r31
-//orig bis r7, r6, r31 // make sure previous loads finish before reading stat registers which unlock them
-//orig ldqp r8, ev5__sc_stat(r14) // unlocks sc_stat,sc_addr
-//orig ldqp r9, ev5__ei_stat(r14) // may unlock ei_*, bc_tag_addr, fill_syn
-//orig ldqp r31, ev5__ei_stat(r14) // ensures it is really unlocked
-//orig mb
-
-#ifndef SIMOS
- mb
- ldq_p r2, scCtl(r14)
- ldq_p r13, ldLock(r14)
- ldq_p r4, scAddr(r14)
- ldq_p r5, eiAddr(r14)
- ldq_p r6, bcTagAddr(r14)
- ldq_p r7, fillSyn(r14)
- bis r5, r4, zero // Make sure all loads complete before
- bis r7, r6, zero // reading registers that unlock them.
- ldq_p r8, scStat(r14) // Unlocks scAddr.
- ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn.
- ldq_p zero, eiStat(r14) // Make sure it is really unlocked.
- mb
-#endif
-//orig // save cbox ipr state
-//orig store_reg1 sc_ctl, r2, r1, ipr=1
-//orig store_reg1 ld_lock, r13, r1, ipr=1
-//orig store_reg1 sc_addr, r4, r1, ipr=1
-//orig store_reg1 ei_addr, r5, r1, ipr=1
-//orig store_reg1 bc_tag_addr, r6, r1, ipr=1
-//orig store_reg1 fill_syn, r7, r1, ipr=1
-//orig store_reg1 sc_stat, r8, r1, ipr=1
-//orig store_reg1 ei_stat, r9, r1, ipr=1
-//orig //bc_config? sl_rcv?
-
- SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1);
- SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1);
- SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1);
- SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1);
- SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1);
- SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1);
- SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1);
- SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1);
-
-// restore impure base //orig
-//orig unfix_impure_ipr r1
- lda r1, -CNS_Q_IPR(r1)
-
-// save all floating regs //orig
- mfpr r0, icsr // get icsr //orig
- or r31, 1, r2 // get a one //orig
-//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot //orig
- sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position
- or r2, r0, r0 // set FEN on //orig
- mtpr r0, icsr // write to icsr, enabling FEN //orig
-
-// map the save area virtually
-// orig mtpr r31, dtb_ia // clear the dtb
-// orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
-// orig sll r0, 32, r0 // shift to PFN field
-// orig lda r2, 0xff(r31) // all read enable and write enable bits set
-// orig sll r2, 8, r2 // move to PTE location
-// orig addq r0, r2, r0 // combine with PFN
-// orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-// orig mtpr r1, dtb_tag // write TB tag
-
- mtpr r31, dtbIa // Clear all DTB entries
- srl r1, va_s_off, r0 // Clean off byte-within-page offset
- sll r0, pte_v_pfn, r0 // Shift to form PFN
- lda r0, pte_m_prot(r0) // Set all read/write enable bits
- mtpr r0, dtbPte // Load the PTE and set valid
- mtpr r1, dtbTag // Write the PTE and tag into the DTB
-
-
-//orig // map the next page too - in case the impure area crosses a page boundary
-//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
-//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r4, dtb_tag // write TB tag
-
- lda r4, (1<<va_s_off)(r1) // Generate address for next page
- srl r4, va_s_off, r0 // Clean off byte-within-page offset
- sll r0, pte_v_pfn, r0 // Shift to form PFN
- lda r0, pte_m_prot(r0) // Set all read/write enable bits
- mtpr r0, dtbPte // Load the PTE and set valid
- mtpr r4, dtbTag // Write the PTE and tag into the DTB
-
- sll r31, 0, r31 // stall cycle 1 // orig
- sll r31, 0, r31 // stall cycle 2 // orig
- sll r31, 0, r31 // stall cycle 3 // orig
- nop // orig
-
-//orig // add offset for saving fpr regs
-//orig fix_impure_gpr r1
-
- lda r1, 0x200(r1) // Point to center of CPU segment
-
-// now save the regs - F0-F31
-
-//orig #define t 0
-//orig .repeat 32
-//orig store_reg \t , fpu=1
-//orig #define t t + 1
-//orig .endr
-
- mf_fpcr f0 // original
-
- SAVE_FPR(f0,CNS_Q_FPR+0x00,r1)
- SAVE_FPR(f1,CNS_Q_FPR+0x08,r1)
- SAVE_FPR(f2,CNS_Q_FPR+0x10,r1)
- SAVE_FPR(f3,CNS_Q_FPR+0x18,r1)
- SAVE_FPR(f4,CNS_Q_FPR+0x20,r1)
- SAVE_FPR(f5,CNS_Q_FPR+0x28,r1)
- SAVE_FPR(f6,CNS_Q_FPR+0x30,r1)
- SAVE_FPR(f7,CNS_Q_FPR+0x38,r1)
- SAVE_FPR(f8,CNS_Q_FPR+0x40,r1)
- SAVE_FPR(f9,CNS_Q_FPR+0x48,r1)
- SAVE_FPR(f10,CNS_Q_FPR+0x50,r1)
- SAVE_FPR(f11,CNS_Q_FPR+0x58,r1)
- SAVE_FPR(f12,CNS_Q_FPR+0x60,r1)
- SAVE_FPR(f13,CNS_Q_FPR+0x68,r1)
- SAVE_FPR(f14,CNS_Q_FPR+0x70,r1)
- SAVE_FPR(f15,CNS_Q_FPR+0x78,r1)
- SAVE_FPR(f16,CNS_Q_FPR+0x80,r1)
- SAVE_FPR(f17,CNS_Q_FPR+0x88,r1)
- SAVE_FPR(f18,CNS_Q_FPR+0x90,r1)
- SAVE_FPR(f19,CNS_Q_FPR+0x98,r1)
- SAVE_FPR(f20,CNS_Q_FPR+0xA0,r1)
- SAVE_FPR(f21,CNS_Q_FPR+0xA8,r1)
- SAVE_FPR(f22,CNS_Q_FPR+0xB0,r1)
- SAVE_FPR(f23,CNS_Q_FPR+0xB8,r1)
- SAVE_FPR(f24,CNS_Q_FPR+0xC0,r1)
- SAVE_FPR(f25,CNS_Q_FPR+0xC8,r1)
- SAVE_FPR(f26,CNS_Q_FPR+0xD0,r1)
- SAVE_FPR(f27,CNS_Q_FPR+0xD8,r1)
- SAVE_FPR(f28,CNS_Q_FPR+0xE0,r1)
- SAVE_FPR(f29,CNS_Q_FPR+0xE8,r1)
- SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1)
- SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1)
-
-//orig //switch impure offset from gpr to ipr---
-//orig unfix_impure_gpr r1
-//orig fix_impure_ipr r1
-//orig store_reg1 fpcsr, f0, r1, fpcsr=1
-
- SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach// pb
- lda r1, -0x200(r1) // Restore the impure base address
-
-//orig // and back to gpr ---
-//orig unfix_impure_ipr r1
-//orig fix_impure_gpr r1
-
-//orig lda r0, cns_mchksize(r31) // get size of mchk area
-//orig store_reg1 mchkflag, r0, r1, ipr=1
-//orig mb
-
- lda r1, CNS_Q_IPR(r1) // Point to base of IPR area again
- // save this using the IPR base (it is closer) not the GRP base as they used...pb
- lda r0, MACHINE_CHECK_SIZE(r31) // get size of mchk area
- SAVE_SHADOW(r0,CNS_Q_MCHK,r1);
- mb
-
-//orig or r31, 1, r0 // get a one
-//orig store_reg1 flag, r0, r1, ipr=1 // set dump area flag
-//orig mb
-
- lda r1, -CNS_Q_IPR(r1) // back to the base
- lda r1, 0x200(r1) // Point to center of CPU segment
- or r31, 1, r0 // get a one
- SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag
- mb
-
-//orig // restore impure area base
-//orig unfix_impure_gpr r1
- lda r1, -0x200(r1) // Point to center of CPU segment
-
- mtpr r31, dtb_ia // clear the dtb //orig
- mtpr r31, itb_ia // clear the itb //orig
-
-//orig pvc_jsr savsta, bsr=1, dest=1
- ret r31, (r3) // and back we go
-#endif
-
-
-#if remove_restore_state == 0
-
-
-// .sbttl "PAL_RESTORE_STATE"
-//+
-//
-// Pal_restore_state
-//
-//
-// register usage:
-// r1 = addr of impure area
-// r3 = return_address
-// all other regs are scratchable, as they are about to
-// be reloaded from ram.
-//
-// Function:
-// All chip state restored, all SRs, FRs, PTs, IPRs
-// *** except R1, R3, PT0, PT4, PT5 ***
-//
-//-
- ALIGN_BLOCK
-pal_restore_state:
-
-//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so.
-
-//orig // map the console io area virtually
-//orig mtpr r31, dtb_ia // clear the dtb
-//orig srl r1, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r1, dtb_tag // write TB tag
-//orig
-
- mtpr r31, dtbIa // Clear all DTB entries
- srl r1, va_s_off, r0 // Clean off byte-within-page offset
- sll r0, pte_v_pfn, r0 // Shift to form PFN
- lda r0, pte_m_prot(r0) // Set all read/write enable bits
- mtpr r0, dtbPte // Load the PTE and set valid
- mtpr r1, dtbTag // Write the PTE and tag into the DTB
-
-
-//orig // map the next page too, in case impure area crosses page boundary
-//orig lda r4, 1@page_offset_size_bits(r1) // generate address for next page
-//orig srl r4, page_offset_size_bits, r0 // Clean off low bits of VA
-//orig sll r0, 32, r0 // shift to PFN field
-//orig lda r2, 0xff(r31) // all read enable and write enable bits set
-//orig sll r2, 8, r2 // move to PTE location
-//orig addq r0, r2, r0 // combine with PFN
-//orig
-//orig mtpr r0, dtb_pte // Load PTE and set TB valid bit
-//orig mtpr r4, dtb_tag // write TB tag - no virtual mbox instruction for 3 cycles
-
- lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page
- srl r4, va_s_off, r0 // Clean off byte-within-page offset
- sll r0, pte_v_pfn, r0 // Shift to form PFN
- lda r0, pte_m_prot(r0) // Set all read/write enable bits
- mtpr r0, dtbPte // Load the PTE and set valid
- mtpr r4, dtbTag // Write the PTE and tag into the DTB
-
-//orig // save all floating regs
-//orig mfpr r0, icsr // get icsr
-//orig// assume ICSR_V_SDE gt <ICSR_V_FPE> // assertion checker
-//orig or r31, <<1@<ICSR_V_SDE-ICSR_V_FPE>> ! 1>, r2 // set SDE and FPE
-//orig sll r2, #icsr_v_fpe, r2 // shift for fpu spot
-//orig or r2, r0, r0 // set FEN on
-//orig mtpr r0, icsr // write to icsr, enabling FEN and SDE. 3 bubbles to floating instr.
-
- mfpr r0, icsr // Get current ICSR
- bis zero, 1, r2 // Get a '1'
- or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2
- sll r2, icsr_v_fpe, r2 // Shift bits into position
- bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE>
- mtpr r0, icsr // Update the chip
-
- mfpr r31, pt0 // FPE bubble cycle 1 //orig
- mfpr r31, pt0 // FPE bubble cycle 2 //orig
- mfpr r31, pt0 // FPE bubble cycle 3 //orig
-
-//orig fix_impure_ipr r1
-//orig restore_reg1 fpcsr, f0, r1, fpcsr=1
-//orig mt_fpcr f0
-//orig
-//orig unfix_impure_ipr r1
-//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access
-//orig
-//orig // restore all floating regs
-//orig#define t 0
-//orig .repeat 32
-//orig restore_reg \t , fpu=1
-//orig#define t t + 1
-//orig .endr
-
- lda r1, 200(r1) // Point to base of IPR area again
- RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb
- mt_fpcr f0 // original
-
- lda r1, 0x200(r1) // point to center of CPU segment
- RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1)
- RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1)
- RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1)
- RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1)
- RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1)
- RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1)
- RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1)
- RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1)
- RESTORE_FPR(f8,CNS_Q_FPR+0x40,r1)
- RESTORE_FPR(f9,CNS_Q_FPR+0x48,r1)
- RESTORE_FPR(f10,CNS_Q_FPR+0x50,r1)
- RESTORE_FPR(f11,CNS_Q_FPR+0x58,r1)
- RESTORE_FPR(f12,CNS_Q_FPR+0x60,r1)
- RESTORE_FPR(f13,CNS_Q_FPR+0x68,r1)
- RESTORE_FPR(f14,CNS_Q_FPR+0x70,r1)
- RESTORE_FPR(f15,CNS_Q_FPR+0x78,r1)
- RESTORE_FPR(f16,CNS_Q_FPR+0x80,r1)
- RESTORE_FPR(f17,CNS_Q_FPR+0x88,r1)
- RESTORE_FPR(f18,CNS_Q_FPR+0x90,r1)
- RESTORE_FPR(f19,CNS_Q_FPR+0x98,r1)
- RESTORE_FPR(f20,CNS_Q_FPR+0xA0,r1)
- RESTORE_FPR(f21,CNS_Q_FPR+0xA8,r1)
- RESTORE_FPR(f22,CNS_Q_FPR+0xB0,r1)
- RESTORE_FPR(f23,CNS_Q_FPR+0xB8,r1)
- RESTORE_FPR(f24,CNS_Q_FPR+0xC0,r1)
- RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1)
- RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1)
- RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1)
- RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1)
- RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1)
- RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1)
- RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1)
-
-//orig // switch impure pointer from gpr to ipr area --
-//orig unfix_impure_gpr r1
-//orig fix_impure_ipr r1
-//orig
-//orig // restore all pal regs
-//orig#define t 1
-//orig .repeat 23
-//orig restore_reg \t , pal=1
-//orig#define t t + 1
-//orig .endr
-
- lda r1, -0x200(r1) // Restore base address of impure area.
- lda r1, CNS_Q_IPR(r1) // Point to base of IPR area.
- RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle
- RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1)
- RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1)
- RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1)
- RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1)
- RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1)
- RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1)
- RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1)
- RESTORE_IPR(pt8,CNS_Q_PT+0x40,r1)
- RESTORE_IPR(pt9,CNS_Q_PT+0x48,r1)
- RESTORE_IPR(pt10,CNS_Q_PT+0x50,r1)
- RESTORE_IPR(pt11,CNS_Q_PT+0x58,r1)
- RESTORE_IPR(pt12,CNS_Q_PT+0x60,r1)
- RESTORE_IPR(pt13,CNS_Q_PT+0x68,r1)
- RESTORE_IPR(pt14,CNS_Q_PT+0x70,r1)
- RESTORE_IPR(pt15,CNS_Q_PT+0x78,r1)
- RESTORE_IPR(pt16,CNS_Q_PT+0x80,r1)
- RESTORE_IPR(pt17,CNS_Q_PT+0x88,r1)
- RESTORE_IPR(pt18,CNS_Q_PT+0x90,r1)
- RESTORE_IPR(pt19,CNS_Q_PT+0x98,r1)
- RESTORE_IPR(pt20,CNS_Q_PT+0xA0,r1)
- RESTORE_IPR(pt21,CNS_Q_PT+0xA8,r1)
- RESTORE_IPR(pt22,CNS_Q_PT+0xB0,r1)
- RESTORE_IPR(pt23,CNS_Q_PT+0xB8,r1)
-
-
-//orig restore_reg exc_addr, ipr=1 // restore ipr
-//orig restore_reg pal_base, ipr=1 // restore ipr
-//orig restore_reg ipl, ipr=1 // restore ipr
-//orig restore_reg ps, ipr=1 // restore ipr
-//orig mtpr r0, dtb_cm // set current mode in mbox too
-//orig restore_reg itb_asn, ipr=1
-//orig srl r0, itb_asn_v_asn, r0
-//orig sll r0, dtb_asn_v_asn, r0
-//orig mtpr r0, dtb_asn // set ASN in Mbox too
-//orig restore_reg ivptbr, ipr=1
-//orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr
-//orig restore_reg mcsr, ipr=1
-//orig restore_reg aster, ipr=1
-//orig restore_reg astrr, ipr=1
-//orig restore_reg sirr, ipr=1
-//orig restore_reg maf_mode, ipr=1 // no mbox instruction for 3 cycles
-//orig mfpr r31, pt0 // (may issue with mt maf_mode)
-//orig mfpr r31, pt0 // bubble cycle 1
-//orig mfpr r31, pt0 // bubble cycle 2
-//orig mfpr r31, pt0 // bubble cycle 3
-//orig mfpr r31, pt0 // (may issue with following ld)
-
- // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag)
- RESTORE_IPR(excAddr,CNS_Q_EXC_ADDR,r1)
- RESTORE_IPR(palBase,CNS_Q_PAL_BASE,r1)
- RESTORE_IPR(ipl,CNS_Q_IPL,r1)
- RESTORE_IPR(ips,CNS_Q_IPS,r1)
- mtpr r0, dtbCm // Set Mbox current mode too.
- RESTORE_IPR(itbAsn,CNS_Q_ITB_ASN,r1)
- srl r0, 4, r0
- sll r0, 57, r0
- mtpr r0, dtbAsn // Set Mbox ASN too
- RESTORE_IPR(iVptBr,CNS_Q_IVPTBR,r1)
- mtpr r0, mVptBr // Set Mbox VptBr too
- RESTORE_IPR(mcsr,CNS_Q_MCSR,r1)
- RESTORE_IPR(aster,CNS_Q_ASTER,r1)
- RESTORE_IPR(astrr,CNS_Q_ASTRR,r1)
- RESTORE_IPR(sirr,CNS_Q_SIRR,r1)
- RESTORE_IPR(mafMode,CNS_Q_MAF_MODE,r1)
- STALL
- STALL
- STALL
- STALL
- STALL
-
-
- // restore all integer shadow regs
-//orig#define t 8
-//orig .repeat 7
-//orig restore_reg \t, shadow=1
-//orig#define t t + 1
-//orig .endr
-//orig restore_reg 25, shadow=1
-//orig restore_reg dc_mode, ipr=1 // no mbox instructions for 4 cycles
-
- RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code
- RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1)
- RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1)
- RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1)
- RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1)
- RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1)
- RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1)
- RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1)
- RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1)
-
- //
- // Get out of shadow mode
- //
-
- mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway) //orig
- mfpr r31, pt0 // "" //orig
- mfpr r0, icsr // Get icsr //orig
-//orig ldah r2, <1@<icsr_v_sde-16>>(r31) // Get a one in SHADOW_ENABLE bit location
- ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location //orig
- bic r0, r2, r2 // ICSR with SDE clear //orig
- mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles //orig
-
- mfpr r31, pt0 // SDE bubble cycle 1 //orig
- mfpr r31, pt0 // SDE bubble cycle 2 //orig
- mfpr r31, pt0 // SDE bubble cycle 3 //orig
- nop //orig
-
-//orig // switch impure pointer from ipr to gpr area --
-//orig unfix_impure_ipr r1
-//orig fix_impure_gpr r1
-//orig // restore all integer regs
-//orig#define t 4
-//orig .repeat 28
-//orig restore_reg \t
-//orig#define t t + 1
-//orig .endr
-
-// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ...
-
- lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area
- lda r1, 0x200(r1) // Point to center of CPU segment
-
- RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1)
- RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1)
- RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1)
- RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1)
- RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1)
- RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1)
- RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1)
- RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1)
- RESTORE_GPR(r12,CNS_Q_GPR+0x60,r1)
- RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1)
- RESTORE_GPR(r14,CNS_Q_GPR+0x70,r1)
- RESTORE_GPR(r15,CNS_Q_GPR+0x78,r1)
- RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1)
- RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1)
- RESTORE_GPR(r18,CNS_Q_GPR+0x90,r1)
- RESTORE_GPR(r19,CNS_Q_GPR+0x98,r1)
- RESTORE_GPR(r20,CNS_Q_GPR+0xA0,r1)
- RESTORE_GPR(r21,CNS_Q_GPR+0xA8,r1)
- RESTORE_GPR(r22,CNS_Q_GPR+0xB0,r1)
- RESTORE_GPR(r23,CNS_Q_GPR+0xB8,r1)
- RESTORE_GPR(r24,CNS_Q_GPR+0xC0,r1)
- RESTORE_GPR(r25,CNS_Q_GPR+0xC8,r1)
- RESTORE_GPR(r26,CNS_Q_GPR+0xD0,r1)
- RESTORE_GPR(r27,CNS_Q_GPR+0xD8,r1)
- RESTORE_GPR(r28,CNS_Q_GPR+0xE0,r1)
- RESTORE_GPR(r29,CNS_Q_GPR+0xE8,r1)
- RESTORE_GPR(r30,CNS_Q_GPR+0xF0,r1)
- RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1)
-
-//orig // switch impure pointer from gpr to ipr area --
-//orig unfix_impure_gpr r1
-//orig fix_impure_ipr r1
-//orig restore_reg icsr, ipr=1 // restore original icsr- 4 bubbles to hw_rei
-
- lda t0, -0x200(t0) // Restore base address of impure area.
- lda t0, CNS_Q_IPR(t0) // Point to base of IPR area again.
- RESTORE_IPR(icsr,CNS_Q_ICSR,r1)
-
-//orig // and back again --
-//orig unfix_impure_ipr r1
-//orig fix_impure_gpr r1
-//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag
-//orig mb
-
- lda t0, -CNS_Q_IPR(t0) // Back to base of impure area again,
- lda t0, 0x200(t0) // and back to center of CPU segment
- SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag
- mb
-
-//orig // and back we go
-//orig// restore_reg 3
-//orig restore_reg 2
-//orig// restore_reg 1
-//orig restore_reg 0
-//orig // restore impure area base
-//orig unfix_impure_gpr r1
-
- RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1)
- RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1)
- lda r1, -0x200(r1) // Restore impure base address
-
- mfpr r31, pt0 // stall for ldqp above //orig
-
- mtpr r31, dtb_ia // clear the tb //orig
- mtpr r31, itb_ia // clear the itb //orig
-
-//orig pvc_jsr rststa, bsr=1, dest=1
- ret r31, (r3) // back we go //orig
-#endif
-
-
-//+
-// pal_pal_bug_check -- code has found a bugcheck situation.
-// Set things up and join common machine check flow.
-//
-// Input:
-// r14 - exc_addr
-//
-// On exit:
-// pt0 - saved r0
-// pt1 - saved r1
-// pt4 - saved r4
-// pt5 - saved r5
-// pt6 - saved r6
-// pt10 - saved exc_addr
-// pt_misc<47:32> - mchk code
-// pt_misc<31:16> - scb vector
-// r14 - base of Cbox IPRs in IO space
-// MCES<mchk> is set
-//-
-
- ALIGN_BLOCK
- .globl pal_pal_bug_check_from_int
-pal_pal_bug_check_from_int:
- DEBUGSTORE(0x79)
-//simos DEBUG_EXC_ADDR()
- DEBUGSTORE(0x20)
-//simos bsr r25, put_hex
- lda r25, mchk_c_bugcheck(r31)
- addq r25, 1, r25 // set flag indicating we came from interrupt and stack is already pushed
- br r31, pal_pal_mchk
- nop
-
-pal_pal_bug_check:
- lda r25, mchk_c_bugcheck(r31)
-
-pal_pal_mchk:
- sll r25, 32, r25 // Move mchk code to position
-
- mtpr r14, pt10 // Stash exc_addr
- mtpr r14, exc_addr
-
- mfpr r12, pt_misc // Get MCES and scratch
- zap r12, 0x3c, r12
-
- or r12, r25, r12 // Combine mchk code
- lda r25, scb_v_procmchk(r31) // Get SCB vector
-
- sll r25, 16, r25 // Move SCBv to position
- or r12, r25, r25 // Combine SCBv
-
- mtpr r0, pt0 // Stash for scratch
- bis r25, mces_m_mchk, r25 // Set MCES<MCHK> bit
-
- mtpr r25, pt_misc // Save mchk code!scbv!whami!mces
- ldah r14, 0xfff0(r31)
-
- mtpr r1, pt1 // Stash for scratch
- zap r14, 0xE0, r14 // Get Cbox IPR base
-
- mtpr r4, pt4
- mtpr r5, pt5
-
- mtpr r6, pt6
- blbs r12, sys_double_machine_check // MCHK halt if double machine check
-
- br r31, sys_mchk_collect_iprs // Join common machine check flow
-
-// align_to_call_pal_section // Align to address of first call_pal entry point - 2000
-
-// .sbttl "HALT - PALcode for HALT instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// GO to console code
-//
-//-
-
- .text 1
-// . = 0x2000
- CALL_PAL_PRIV(PAL_HALT_ENTRY)
-call_pal_halt:
-#if rax_mode == 0
- mfpr r31, pt0 // Pad exc_addr read
- mfpr r31, pt0
-
- mfpr r12, exc_addr // get PC
- subq r12, 4, r12 // Point to the HALT
-
- mtpr r12, exc_addr
- mtpr r0, pt0
-
-//orig pvc_jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
- lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt
- br r31, sys_enter_console // enter the console
-
-#else // RAX mode
- mb
- mb
- mtpr r9, ev5__dtb_asn // no Dstream virtual ref for next 3 cycles.
- mtpr r9, ev5__itb_asn // E1. Update ITB ASN. No hw_rei for 5 cycles.
- mtpr r8, exc_addr // no HW_REI for 1 cycle.
- blbc r9, not_begin_case
- mtpr r31, ev5__dtb_ia // clear DTB. No Dstream virtual ref for 2 cycles.
- mtpr r31, ev5__itb_ia // clear ITB.
-
-not_begin_case:
- nop
- nop
-
- nop
- nop // pad mt itb_asn ->hw_rei_stall
-
- hw_rei_stall
-#endif
-
-// .sbttl "CFLUSH- PALcode for CFLUSH instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// R16 - contains the PFN of the page to be flushed
-//
-// Function:
-// Flush all Dstream caches of 1 entire page
-// The CFLUSH routine is in the system specific module.
-//
-//-
-
- CALL_PAL_PRIV(PAL_CFLUSH_ENTRY)
-Call_Pal_Cflush:
- br r31, sys_cflush
-
-// .sbttl "DRAINA - PALcode for DRAINA instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-// Implicit TRAPB performed by hardware.
-//
-// Function:
-// Stall instruction issue until all prior instructions are guaranteed to
-// complete without incurring aborts. For the EV5 implementation, this
-// means waiting until all pending DREADS are returned.
-//
-//-
-
- CALL_PAL_PRIV(PAL_DRAINA_ENTRY)
-Call_Pal_Draina:
- ldah r14, 0x100(r31) // Init counter. Value?
- nop
-
-DRAINA_LOOP:
- subq r14, 1, r14 // Decrement counter
- mfpr r13, ev5__maf_mode // Fetch status bit
-
- srl r13, maf_mode_v_dread_pending, r13
- ble r14, DRAINA_LOOP_TOO_LONG
-
- nop
- blbs r13, DRAINA_LOOP // Wait until all DREADS clear
-
- hw_rei
-
-DRAINA_LOOP_TOO_LONG:
- br r31, call_pal_halt
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_PRIV(0x0003)
-CallPal_OpcDec03:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0004)
-CallPal_OpcDec04:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0005)
-CallPal_OpcDec05:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0006)
-CallPal_OpcDec06:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0007)
-CallPal_OpcDec07:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0008)
-CallPal_OpcDec08:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "CSERVE- PALcode for CSERVE instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Various functions for private use of console software
-//
-// option selector in r0
-// arguments in r16....
-// The CSERVE routine is in the system specific module.
-//
-//-
-
- CALL_PAL_PRIV(PAL_CSERVE_ENTRY)
-Call_Pal_Cserve:
- br r31, sys_cserve
-
-// .sbttl "swppal - PALcode for swppal instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-// Vectored into via hardware PALcode instruction dispatch.
-// R16 contains the new PAL identifier
-// R17:R21 contain implementation-specific entry parameters
-//
-// R0 receives status:
-// 0 success (PAL was switched)
-// 1 unknown PAL variant
-// 2 known PAL variant, but PAL not loaded
-//
-//
-// Function:
-// Swap control to another PAL.
-//-
-
- CALL_PAL_PRIV(PAL_SWPPAL_ENTRY)
-Call_Pal_Swppal:
- cmpule r16, 255, r0 // see if a kibble was passed
- cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59)
-
- or r16, r31, r3 // set r3 incase this is a address
- blbc r0, swppal_cont // nope, try it as an address
-
- cmpeq r16, 2, r0 // is it our friend OSF?
- blbc r0, swppal_fail // nope, don't know this fellow
-
- br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF
-
-// .global osfpal_hw_entry_reset
-// .weak osfpal_hw_entry_reset
-// .long <osfpal_hw_entry_reset-pal_start>
-//orig halt // don't know how to get the address here - kludge ok, load pal at 0
- .long 0 // ?? hack upon hack...pb
-
-CALL_PAL_SWPPAL_10_: ldlp r3, 0(r2) // fetch target addr
-// ble r3, swppal_fail ; if OSF not linked in say not loaded.
- mfpr r2, pal_base // fetch pal base
-
- addq r2, r3, r3 // add pal base
- lda r2, 0x3FFF(r31) // get pal base checker mask
-
- and r3, r2, r2 // any funky bits set?
- cmpeq r2, 0, r0 //
-
- blbc r0, swppal_fail // return unknown if bad bit set.
- br r31, swppal_cont
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_PRIV(0x000B)
-CallPal_OpcDec0B:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x000C)
-CallPal_OpcDec0C:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "wripir- PALcode for wripir instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-// r16 = processor number to interrupt
-//
-// Function:
-// IPIR <- R16
-// Handled in system-specific code
-//
-// Exit:
-// interprocessor interrupt is recorded on the target processor
-// and is initiated when the proper enabling conditions are present.
-//-
-
- CALL_PAL_PRIV(PAL_WRIPIR_ENTRY)
-Call_Pal_Wrpir:
- br r31, sys_wripir
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_PRIV(0x000E)
-CallPal_OpcDec0E:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x000F)
-CallPal_OpcDec0F:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "rdmces- PALcode for rdmces instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// R0 <- ZEXT(MCES)
-//-
-
- CALL_PAL_PRIV(PAL_RDMCES_ENTRY)
-Call_Pal_Rdmces:
- mfpr r0, pt_mces // Read from PALtemp
- and r0, mces_m_all, r0 // Clear other bits
-
- hw_rei
-
-// .sbttl "wrmces- PALcode for wrmces instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK)
-// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE)
-// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE)
-// MCES<3> <- R16<3> (DPC)
-// MCES<4> <- R16<4> (DSC)
-//
-//-
-
- CALL_PAL_PRIV(PAL_WRMCES_ENTRY)
-Call_Pal_Wrmces:
- and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE
- mfpr r14, pt_mces // Get current value
-
- ornot r31, r13, r13 // Flip all the bits
- and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17
-
- and r14, r13, r1 // Update MCHK, SCE, PCE
- bic r1, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r1 // Clear old DPC, DSC
-
- or r1, r17, r1 // Update DPC and DSC
- mtpr r1, pt_mces // Write MCES back
-
-#if rawhide_system == 0
- nop // Pad to fix PT write->read restriction
-#else
- blbs r16, RAWHIDE_clear_mchk_lock // Clear logout from lock
-#endif
-
- nop
- hw_rei
-
-
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_PRIV(0x0012)
-CallPal_OpcDec12:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0013)
-CallPal_OpcDec13:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0014)
-CallPal_OpcDec14:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0015)
-CallPal_OpcDec15:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0016)
-CallPal_OpcDec16:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0017)
-CallPal_OpcDec17:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0018)
-CallPal_OpcDec18:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0019)
-CallPal_OpcDec19:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001A)
-CallPal_OpcDec1A:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001B)
-CallPal_OpcDec1B:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001C)
-CallPal_OpcDec1C:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001D)
-CallPal_OpcDec1D:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001E)
-CallPal_OpcDec1E:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x001F)
-CallPal_OpcDec1F:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0020)
-CallPal_OpcDec20:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0021)
-CallPal_OpcDec21:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0022)
-CallPal_OpcDec22:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0023)
-CallPal_OpcDec23:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0024)
-CallPal_OpcDec24:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0025)
-CallPal_OpcDec25:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0026)
-CallPal_OpcDec26:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0027)
-CallPal_OpcDec27:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0028)
-CallPal_OpcDec28:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x0029)
-CallPal_OpcDec29:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x002A)
-CallPal_OpcDec2A:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "wrfen - PALcode for wrfen instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// a0<0> -> ICSR<FPE>
-// Store new FEN in PCB
-// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16) are UNPREDICTABLE
-//
-// Issue: What about pending FP loads when FEN goes from on->off????
-//-
-
- CALL_PAL_PRIV(PAL_WRFEN_ENTRY)
-Call_Pal_Wrfen:
- or r31, 1, r13 // Get a one
- mfpr r1, ev5__icsr // Get current FPE
-
- sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0
- and r16, 1, r16 // clean new fen
-
- sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position
- bic r1, r13, r1 // zero icsr<fpe>
-
- or r1, r12, r1 // Or new FEN into ICSR
- mfpr r12, pt_pcbb // Get PCBB - E1
-
- mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI
- stlp r16, osfpcb_q_fen(r12) // Store FEN in PCB.
-
- mfpr r31, pt0 // Pad ICSR<FPE> write.
- mfpr r31, pt0
-
- mfpr r31, pt0
-// pvc_violate 225 // cuz PVC can't distinguish which bits changed
- hw_rei
-
-
- CALL_PAL_PRIV(0x002C)
-CallPal_OpcDec2C:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "wrvptpr - PALcode for wrvptpr instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// vptptr <- a0 (r16)
-//-
-
- CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY)
-Call_Pal_Wrvptptr:
- mtpr r16, ev5__mvptbr // Load Mbox copy
- mtpr r16, ev5__ivptbr // Load Ibox copy
- nop // Pad IPR write
- nop
- hw_rei
-
- CALL_PAL_PRIV(0x002E)
-CallPal_OpcDec2E:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_PRIV(0x002F)
-CallPal_OpcDec2F:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "swpctx- PALcode for swpctx instruction"
-
-//+
-//
-// Entry:
-// hardware dispatch via callPal instruction
-// R16 -> new pcb
-//
-// Function:
-// dynamic state moved to old pcb
-// new state loaded from new pcb
-// pcbb pointer set
-// old pcbb returned in R0
-//
-// Note: need to add perf monitor stuff
-//-
-
- CALL_PAL_PRIV(PAL_SWPCTX_ENTRY)
-Call_Pal_Swpctx:
- rpcc r13 // get cyccounter
- mfpr r0, pt_pcbb // get pcbb
-
- ldqp r22, osfpcb_q_fen(r16) // get new fen/pme
- ldqp r23, osfpcb_l_cc(r16) // get new asn
-
- srl r13, 32, r25 // move offset
- mfpr r24, pt_usp // get usp
-
- stqp r30, osfpcb_q_ksp(r0) // store old ksp
-// pvc_violate 379 // stqp can't trap except replay. only problem if mf same ipr in same shadow.
- mtpr r16, pt_pcbb // set new pcbb
-
- stqp r24, osfpcb_q_usp(r0) // store usp
- addl r13, r25, r25 // merge for new time
-
- stlp r25, osfpcb_l_cc(r0) // save time
- ldah r24, (1<<(icsr_v_fpe-16))(r31)
-
- and r22, 1, r12 // isolate fen
- mfpr r25, icsr // get current icsr
-
- ev5_pass2 lda r24, (1<<icsr_v_pmp)(r24)
- br r31, swpctx_cont
-
-// .sbttl "wrval - PALcode for wrval instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// sysvalue <- a0 (r16)
-//-
-
- CALL_PAL_PRIV(PAL_WRVAL_ENTRY)
-Call_Pal_Wrval:
- nop
- mtpr r16, pt_sysval // Pad paltemp write
- nop
- nop
- hw_rei
-
-
-// .sbttl "rdval - PALcode for rdval instruction"
-
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- sysvalue
-//-
-
- CALL_PAL_PRIV(PAL_RDVAL_ENTRY)
-Call_Pal_Rdval:
- nop
- mfpr r0, pt_sysval
- nop
- hw_rei
-
-// .sbttl "tbi - PALcode for tbi instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// TB invalidate
-// r16/a0 = TBI type
-// r17/a1 = Va for TBISx instructions
-//-
-
- CALL_PAL_PRIV(PAL_TBI_ENTRY)
-Call_Pal_Tbi:
- addq r16, 2, r16 // change range to 0-2
- br r23, CALL_PAL_tbi_10_ // get our address
-
-CALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range
- lda r23, tbi_tbl-CALL_PAL_tbi_10_(r23) // set base to start of table
- sll r16, 4, r16 // * 16
- blbc r22, CALL_PAL_tbi_30_ // go rei, if not
-
- addq r23, r16, r23 // addr of our code
-//orig pvc_jsr tbi
- jmp r31, (r23) // and go do it
-
-CALL_PAL_tbi_30_:
- hw_rei
- nop
-
-// .sbttl "wrent - PALcode for wrent instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Update ent* in paltemps
-// r16/a0 = Address of entry routine
-// r17/a1 = Entry Number 0..5
-//
-// r22, r23 trashed
-//-
-
- CALL_PAL_PRIV(PAL_WRENT_ENTRY)
-Call_Pal_Wrent:
- cmpult r17, 6, r22 // see if in range
- br r23, CALL_PAL_wrent_10_ // get our address
-
-CALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc
- blbc r22, CALL_PAL_wrent_30_ // go rei, if not in range
-
- lda r23, wrent_tbl-CALL_PAL_wrent_10_(r23) // set base to start of table
- sll r17, 4, r17 // *16
-
- addq r17, r23, r23 // Get address in table
-//orig pvc_jsr wrent
- jmp r31, (r23) // and go do it
-
-CALL_PAL_wrent_30_:
- hw_rei // out of range, just return
-
-// .sbttl "swpipl - PALcode for swpipl instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- PS<IPL>
-// PS<IPL> <- a0<2:0> (r16)
-//
-// t8 (r22) is scratch
-//-
-
- CALL_PAL_PRIV(PAL_SWPIPL_ENTRY)
-Call_Pal_Swpipl:
- and r16, osfps_m_ipl, r16 // clean New ipl
- mfpr r22, pt_intmask // get int mask
-
- extbl r22, r16, r22 // get mask for this ipl
- bis r11, r31, r0 // return old ipl
-
- bis r16, r31, r11 // set new ps
- mtpr r22, ev5__ipl // set new mask
-
- mfpr r31, pt0 // pad ipl write
- mfpr r31, pt0 // pad ipl write
-
- hw_rei // back
-
-// .sbttl "rdps - PALcode for rdps instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- ps
-//-
-
- CALL_PAL_PRIV(PAL_RDPS_ENTRY)
-Call_Pal_Rdps:
- bis r11, r31, r0 // Fetch PALshadow PS
- nop // Must be 2 cycles long
- hw_rei
-
-// .sbttl "wrkgp - PALcode for wrkgp instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// kgp <- a0 (r16)
-//-
-
- CALL_PAL_PRIV(PAL_WRKGP_ENTRY)
-Call_Pal_Wrkgp:
- nop
- mtpr r16, pt_kgp
- nop // Pad for pt write->read restriction
- nop
- hw_rei
-
-// .sbttl "wrusp - PALcode for wrusp instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// usp <- a0 (r16)
-//-
-
- CALL_PAL_PRIV(PAL_WRUSP_ENTRY)
-Call_Pal_Wrusp:
- nop
- mtpr r16, pt_usp
- nop // Pad possible pt write->read restriction
- nop
- hw_rei
-
-// .sbttl "wrperfmon - PALcode for wrperfmon instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-//
-// Function:
-// Various control functions for the onchip performance counters
-//
-// option selector in r16
-// option argument in r17
-// returned status in r0
-//
-//
-// r16 = 0 Disable performance monitoring for one or more cpu's
-// r17 = 0 disable no counters
-// r17 = bitmask disable counters specified in bit mask (1=disable)
-//
-// r16 = 1 Enable performance monitoring for one or more cpu's
-// r17 = 0 enable no counters
-// r17 = bitmask enable counters specified in bit mask (1=enable)
-//
-// r16 = 2 Mux select for one or more cpu's
-// r17 = Mux selection (cpu specific)
-// <24:19> bc_ctl<pm_mux_sel> field (see spec)
-// <31>,<7:4>,<3:0> pmctr <sel0>,<sel1>,<sel2> fields (see spec)
-//
-// r16 = 3 Options
-// r17 = (cpu specific)
-// <0> = 0 log all processes
-// <0> = 1 log only selected processes
-// <30,9,8> mode select - ku,kp,kk
-//
-// r16 = 4 Interrupt frequency select
-// r17 = (cpu specific) indicates interrupt frequencies desired for each
-// counter, with "zero interrupts" being an option
-// frequency info in r17 bits as defined by PMCTR_CTL<FRQx> below
-//
-// r16 = 5 Read Counters
-// r17 = na
-// r0 = value (same format as ev5 pmctr)
-// <0> = 0 Read failed
-// <0> = 1 Read succeeded
-//
-// r16 = 6 Write Counters
-// r17 = value (same format as ev5 pmctr; all counters written simultaneously)
-//
-// r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0
-// r17 = 0 enable no counters
-// r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear)
-//
-//=============================================================================
-//Assumptions:
-//PMCTR_CTL:
-//
-// <15:14> CTL0 -- encoded frequency select and enable - CTR0
-// <13:12> CTL1 -- " - CTR1
-// <11:10> CTL2 -- " - CTR2
-//
-// <9:8> FRQ0 -- frequency select for CTR0 (no enable info)
-// <7:6> FRQ1 -- frequency select for CTR1
-// <5:4> FRQ2 -- frequency select for CTR2
-//
-// <0> all vs. select processes (0=all,1=select)
-//
-// where
-// FRQx<1:0>
-// 0 1 disable interrupt
-// 1 0 frequency = 65536 (16384 for ctr2)
-// 1 1 frequency = 256
-// note: FRQx<1:0> = 00 will keep counters from ever being enabled.
-//
-//=============================================================================
-//
- CALL_PAL_PRIV(0x0039)
-// unsupported in Hudson code .. pboyle Nov/95
-CALL_PAL_Wrperfmon:
-#if perfmon_debug == 0
- // "real" performance monitoring code
- cmpeq r16, 1, r0 // check for enable
- bne r0, perfmon_en // br if requested to enable
-
- cmpeq r16, 2, r0 // check for mux ctl
- bne r0, perfmon_muxctl // br if request to set mux controls
-
- cmpeq r16, 3, r0 // check for options
- bne r0, perfmon_ctl // br if request to set options
-
- cmpeq r16, 4, r0 // check for interrupt frequency select
- bne r0, perfmon_freq // br if request to change frequency select
-
- cmpeq r16, 5, r0 // check for counter read request
- bne r0, perfmon_rd // br if request to read counters
-
- cmpeq r16, 6, r0 // check for counter write request
- bne r0, perfmon_wr // br if request to write counters
-
- cmpeq r16, 7, r0 // check for counter clear/enable request
- bne r0, perfmon_enclr // br if request to clear/enable counters
-
- beq r16, perfmon_dis // br if requested to disable (r16=0)
- br r31, perfmon_unknown // br if unknown request
-#else
-
- br r31, pal_perfmon_debug
-#endif
-
-// .sbttl "rdusp - PALcode for rdusp instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- usp
-//-
-
- CALL_PAL_PRIV(PAL_RDUSP_ENTRY)
-Call_Pal_Rdusp:
- nop
- mfpr r0, pt_usp
- hw_rei
-
-
- CALL_PAL_PRIV(0x003B)
-CallPal_OpcDec3B:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "whami - PALcode for whami instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- whami
-//-
- CALL_PAL_PRIV(PAL_WHAMI_ENTRY)
-Call_Pal_Whami:
- nop
- mfpr r0, pt_whami // Get Whami
- extbl r0, 1, r0 // Isolate just whami bits
- hw_rei
-
-// .sbttl "retsys - PALcode for retsys instruction"
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-// 00(sp) contains return pc
-// 08(sp) contains r29
-//
-// Function:
-// Return from system call.
-// mode switched from kern to user.
-// stacks swapped, ugp, upc restored.
-// r23, r25 junked
-//-
-
- CALL_PAL_PRIV(PAL_RETSYS_ENTRY)
-Call_Pal_Retsys:
- lda r25, osfsf_c_size(sp) // pop stack
- bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr
-
- mfpr r14, exc_addr // save exc_addr in case of fault
- ldq r23, osfsf_pc(sp) // get pc
-
- ldq r29, osfsf_gp(sp) // get gp
- stl_c r31, -4(sp) // clear lock_flag
-
- lda r11, 1<<osfps_v_mode(r31)// new PS:mode=user
- mfpr r30, pt_usp // get users stack
-
- bic r23, 3, r23 // clean return pc
- mtpr r31, ev5__ipl // zero ibox IPL - 2 bubbles to hw_rei
-
- mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
- mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
-
- mtpr r23, exc_addr // set return address - 1 bubble to hw_rei
- mtpr r25, pt_ksp // save kern stack
-
- rc r31 // clear inter_flag
-// pvc_violate 248 // possible hidden mt->mf pt violation ok in callpal
- hw_rei_spe // and back
-
-
- CALL_PAL_PRIV(0x003E)
-CallPal_OpcDec3E:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "rti - PALcode for rti instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// 00(sp) -> ps
-// 08(sp) -> pc
-// 16(sp) -> r29 (gp)
-// 24(sp) -> r16 (a0)
-// 32(sp) -> r17 (a1)
-// 40(sp) -> r18 (a3)
-//-
-
- CALL_PAL_PRIV(PAL_RTI_ENTRY)
-#ifdef SIMOS
- /* called once by platform_tlaser */
- .globl Call_Pal_Rti
-#endif
-Call_Pal_Rti:
- lda r25, osfsf_c_size(sp) // get updated sp
- bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr
-
- mfpr r14, exc_addr // save PC in case of fault
- rc r31 // clear intr_flag
-
- ldq r12, -6*8(r25) // get ps
- ldq r13, -5*8(r25) // pc
-
- ldq r18, -1*8(r25) // a2
- ldq r17, -2*8(r25) // a1
-
- ldq r16, -3*8(r25) // a0
- ldq r29, -4*8(r25) // gp
-
- bic r13, 3, r13 // clean return pc
- stl_c r31, -4(r25) // clear lock_flag
-
- and r12, osfps_m_mode, r11 // get mode
- mtpr r13, exc_addr // set return address
-
- beq r11, rti_to_kern // br if rti to Kern
- br r31, rti_to_user // out of call_pal space
-
-
-// .sbttl "Start the Unprivileged CALL_PAL Entry Points"
-// .sbttl "bpt- PALcode for bpt instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-//
- .text 1
-// . = 0x3000
- CALL_PAL_UNPRIV(PAL_BPT_ENTRY)
-Call_Pal_Bpt:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, CALL_PAL_bpt_10_ // no stack swap needed if cm=kern
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-CALL_PAL_bpt_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_bpt, r16 // set a0
-
- stq r17, osfsf_a1(sp) // a1
- br r31, bpt_bchk_common // out of call_pal space
-
-
-// .sbttl "bugchk- PALcode for bugchk instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-//
- CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY)
-Call_Pal_Bugchk:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, CALL_PAL_bugchk_10_ // no stack swap needed if cm=kern
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-CALL_PAL_bugchk_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_bugchk, r16 // set a0
-
- stq r17, osfsf_a1(sp) // a1
- br r31, bpt_bchk_common // out of call_pal space
-
-
- CALL_PAL_UNPRIV(0x0082)
-CallPal_OpcDec82:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "callsys - PALcode for callsys instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Switch mode to kernel and build a callsys stack frame.
-// sp = ksp
-// gp = kgp
-// t8 - t10 (r22-r24) trashed
-//
-//-
-//
- CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY)
-Call_Pal_Callsys:
-
- and r11, osfps_m_mode, r24 // get mode
- mfpr r22, pt_ksp // get ksp
-
- beq r24, sys_from_kern // sysCall from kern is not allowed
- mfpr r12, pt_entsys // get address of callSys routine
-
-//+
-// from here on we know we are in user going to Kern
-//-
- mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
- mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
-
- bis r31, r31, r11 // PS=0 (mode=kern)
- mfpr r23, exc_addr // get pc
-
- mtpr r30, pt_usp // save usp
- lda sp, 0-osfsf_c_size(r22)// set new sp
-
- stq r29, osfsf_gp(sp) // save user gp/r29
- stq r24, osfsf_ps(sp) // save ps
-
- stq r23, osfsf_pc(sp) // save pc
- mtpr r12, exc_addr // set address
- // 1 cycle to hw_rei
-
- mfpr r29, pt_kgp // get the kern gp/r29
-
- hw_rei_spe // and off we go!
-
-
- CALL_PAL_UNPRIV(0x0084)
-CallPal_OpcDec84:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0085)
-CallPal_OpcDec85:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "imb - PALcode for imb instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Flush the writebuffer and flush the Icache
-//
-//-
-//
- CALL_PAL_UNPRIV(PAL_IMB_ENTRY)
-Call_Pal_Imb:
- mb // Clear the writebuffer
- mfpr r31, ev5__mcsr // Sync with clear
- nop
- nop
- br r31, pal_ic_flush // Flush Icache
-
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_UNPRIV(0x0087)
-CallPal_OpcDec87:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0088)
-CallPal_OpcDec88:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0089)
-CallPal_OpcDec89:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008A)
-CallPal_OpcDec8A:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008B)
-CallPal_OpcDec8B:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008C)
-CallPal_OpcDec8C:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008D)
-CallPal_OpcDec8D:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008E)
-CallPal_OpcDec8E:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x008F)
-CallPal_OpcDec8F:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0090)
-CallPal_OpcDec90:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0091)
-CallPal_OpcDec91:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0092)
-CallPal_OpcDec92:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0093)
-CallPal_OpcDec93:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0094)
-CallPal_OpcDec94:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0095)
-CallPal_OpcDec95:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0096)
-CallPal_OpcDec96:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0097)
-CallPal_OpcDec97:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0098)
-CallPal_OpcDec98:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x0099)
-CallPal_OpcDec99:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x009A)
-CallPal_OpcDec9A:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x009B)
-CallPal_OpcDec9B:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x009C)
-CallPal_OpcDec9C:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x009D)
-CallPal_OpcDec9D:
- br r31, osfpal_calpal_opcdec
-
-// .sbttl "rdunique - PALcode for rdunique instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// v0 (r0) <- unique
-//
-//-
-//
- CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY)
-CALL_PALrdunique_:
- mfpr r0, pt_pcbb // get pcb pointer
- ldqp r0, osfpcb_q_unique(r0) // get new value
-
- hw_rei
-
-// .sbttl "wrunique - PALcode for wrunique instruction"
-//+
-//
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// unique <- a0 (r16)
-//
-//-
-//
-CALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY)
-CALL_PAL_Wrunique:
- nop
- mfpr r12, pt_pcbb // get pcb pointer
- stqp r16, osfpcb_q_unique(r12)// get new value
- nop // Pad palshadow write
- hw_rei // back
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_UNPRIV(0x00A0)
-CallPal_OpcDecA0:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A1)
-CallPal_OpcDecA1:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A2)
-CallPal_OpcDecA2:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A3)
-CallPal_OpcDecA3:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A4)
-CallPal_OpcDecA4:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A5)
-CallPal_OpcDecA5:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A6)
-CallPal_OpcDecA6:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A7)
-CallPal_OpcDecA7:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A8)
-CallPal_OpcDecA8:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00A9)
-CallPal_OpcDecA9:
- br r31, osfpal_calpal_opcdec
-
-
-// .sbttl "gentrap - PALcode for gentrap instruction"
-//+
-// CALL_PAL_gentrap:
-// Entry:
-// Vectored into via hardware PALcode instruction dispatch.
-//
-// Function:
-// Build stack frame
-// a0 <- code
-// a1 <- unpred
-// a2 <- unpred
-// vector via entIF
-//
-//-
-
- CALL_PAL_UNPRIV(0x00AA)
-// unsupported in Hudson code .. pboyle Nov/95
-CALL_PAL_gentrap:
- sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- bis r11, r31, r12 // Save PS for stack write
- bge r25, CALL_PAL_gentrap_10_ // no stack swap needed if cm=kern
-
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r30, pt_usp // save user stack
-
- bis r31, r31, r11 // Set new PS
- mfpr r30, pt_ksp
-
-CALL_PAL_gentrap_10_:
- lda sp, 0-osfsf_c_size(sp)// allocate stack space
- mfpr r14, exc_addr // get pc
-
- stq r16, osfsf_a0(sp) // save regs
- bis r31, osf_a0_gentrap, r16// set a0
-
- stq r17, osfsf_a1(sp) // a1
- br r31, bpt_bchk_common // out of call_pal space
-
-
-// .sbttl "CALL_PAL OPCDECs"
-
- CALL_PAL_UNPRIV(0x00AB)
-CallPal_OpcDecAB:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00AC)
-CallPal_OpcDecAC:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00AD)
-CallPal_OpcDecAD:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00AE)
-CallPal_OpcDecAE:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00AF)
-CallPal_OpcDecAF:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B0)
-CallPal_OpcDecB0:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B1)
-CallPal_OpcDecB1:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B2)
-CallPal_OpcDecB2:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B3)
-CallPal_OpcDecB3:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B4)
-CallPal_OpcDecB4:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B5)
-CallPal_OpcDecB5:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B6)
-CallPal_OpcDecB6:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B7)
-CallPal_OpcDecB7:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B8)
-CallPal_OpcDecB8:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00B9)
-CallPal_OpcDecB9:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BA)
-CallPal_OpcDecBA:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BB)
-CallPal_OpcDecBB:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BC)
-CallPal_OpcDecBC:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BD)
-CallPal_OpcDecBD:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BE)
-CallPal_OpcDecBE:
- br r31, osfpal_calpal_opcdec
-
- CALL_PAL_UNPRIV(0x00BF)
-CallPal_OpcDecBF:
- // MODIFIED BY EGH 2/25/04
- br r31, copypal_impl
-
-
-/*======================================================================*/
-/* OSF/1 CALL_PAL CONTINUATION AREA */
-/*======================================================================*/
-
- .text 2
-
- . = 0x4000
-
-
-// .sbttl "Continuation of MTPR_PERFMON"
- ALIGN_BLOCK
-#if perfmon_debug == 0
- // "real" performance monitoring code
-// mux ctl
-perfmon_muxctl:
- lda r8, 1(r31) // get a 1
- sll r8, pmctr_v_sel0, r8 // move to sel0 position
- or r8, ((0xf<<pmctr_v_sel1) | (0xf<<pmctr_v_sel2)), r8 // build mux select mask
- and r17, r8, r25 // isolate pmctr mux select bits
- mfpr r0, ev5__pmctr
- bic r0, r8, r0 // clear old mux select bits
- or r0,r25, r25 // or in new mux select bits
- mtpr r25, ev5__pmctr
-
- // ok, now tackle cbox mux selects
- ldah r14, 0xfff0(r31)
- zap r14, 0xE0, r14 // Get Cbox IPR base
-//orig get_bc_ctl_shadow r16 // bc_ctl returned in lower longword
-// adapted from ev5_pal_macros.mar
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
-
- lda r8, 0x3F(r31) // build mux select mask
- sll r8, bc_ctl_v_pm_mux_sel, r8
-
- and r17, r8, r25 // isolate bc_ctl mux select bits
- bic r16, r8, r16 // isolate old mux select bits
- or r16, r25, r25 // create new bc_ctl
- mb // clear out cbox for future ipr write
- stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
- mb // clear out cbox for future ipr write
-
-//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
-// adapted from ev5_pal_macros.mar
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
-
- br r31, perfmon_success
-
-
-// requested to disable perf monitoring
-perfmon_dis:
- mfpr r14, ev5__pmctr // read ibox pmctr ipr
-perfmon_dis_ctr0: // and begin with ctr0
- blbc r17, perfmon_dis_ctr1 // do not disable ctr0
- lda r8, 3(r31)
- sll r8, pmctr_v_ctl0, r8
- bic r14, r8, r14 // disable ctr0
-perfmon_dis_ctr1:
- srl r17, 1, r17
- blbc r17, perfmon_dis_ctr2 // do not disable ctr1
- lda r8, 3(r31)
- sll r8, pmctr_v_ctl1, r8
- bic r14, r8, r14 // disable ctr1
-perfmon_dis_ctr2:
- srl r17, 1, r17
- blbc r17, perfmon_dis_update // do not disable ctr2
- lda r8, 3(r31)
- sll r8, pmctr_v_ctl2, r8
- bic r14, r8, r14 // disable ctr2
-perfmon_dis_update:
- mtpr r14, ev5__pmctr // update pmctr ipr
-//;the following code is not needed for ev5 pass2 and later, but doesn't hurt anything to leave in
-// adapted from ev5_pal_macros.mar
-//orig get_pmctr_ctl r8, r25 // pmctr_ctl bit in r8. adjusted impure pointer in r25
- mfpr r25, pt_impure
- lda r25, CNS_Q_IPR(r25)
- RESTORE_SHADOW(r8,CNS_Q_PM_CTL,r25);
-
- lda r17, 0x3F(r31) // build mask
- sll r17, pmctr_v_ctl2, r17 // shift mask to correct position
- and r14, r17, r14 // isolate ctl bits
- bic r8, r17, r8 // clear out old ctl bits
- or r14, r8, r14 // create shadow ctl bits
-//orig store_reg1 pmctr_ctl, r14, r25, ipr=1 // update pmctr_ctl register
-//adjusted impure pointer still in r25
- SAVE_SHADOW(r14,CNS_Q_PM_CTL,r25);
-
- br r31, perfmon_success
-
-
-// requested to enable perf monitoring
-//;the following code can be greatly simplified for pass2, but should work fine as is.
-
-
-perfmon_enclr:
- lda r9, 1(r31) // set enclr flag
- br perfmon_en_cont
-
-perfmon_en:
- bis r31, r31, r9 // clear enclr flag
-
-perfmon_en_cont:
- mfpr r8, pt_pcbb // get PCB base
-//orig get_pmctr_ctl r25, r25
- mfpr r25, pt_impure
- lda r25, CNS_Q_IPR(r25)
- RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25);
-
- ldqp r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
- mfpr r14, ev5__pmctr // read ibox pmctr ipr
- srl r16, osfpcb_v_pme, r16 // get pme bit
- mfpr r13, icsr
- and r16, 1, r16 // isolate pme bit
-
- // this code only needed in pass2 and later
-//orig sget_addr r12, 1<<icsr_v_pmp, r31
- lda r12, 1<<icsr_v_pmp(r31) // pb
- bic r13, r12, r13 // clear pmp bit
- sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position
- or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear
- ev5_pass2 mtpr r13, icsr // update icsr
-
-#if ev5_p1 != 0
- lda r12, 1(r31)
- cmovlbc r25, r12, r16 // r16<0> set if either pme=1 or sprocess=0 (sprocess in bit 0 of r25)
-#else
- bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable)
-#endif
-
- sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions
- bis r14, r31, r13 // copy pmctr
-
-perfmon_en_ctr0: // and begin with ctr0
- blbc r17, perfmon_en_ctr1 // do not enable ctr0
-
- blbc r9, perfmon_en_noclr0 // enclr flag set, clear ctr0 field
- lda r8, 0xffff(r31)
- zapnot r8, 3, r8 // ctr0<15:0> mask
- sll r8, pmctr_v_ctr0, r8
- bic r14, r8, r14 // clear ctr bits
- bic r13, r8, r13 // clear ctr bits
-
-perfmon_en_noclr0:
-//orig get_addr r8, 3<<pmctr_v_ctl0, r31
- LDLI(r8, (3<<pmctr_v_ctl0))
- and r25, r8, r12 //isolate frequency select bits for ctr0
- bic r14, r8, r14 // clear ctl0 bits in preparation for enabling
- or r14,r12,r14 // or in new ctl0 bits
-
-perfmon_en_ctr1: // enable ctr1
- srl r17, 1, r17 // get ctr1 enable
- blbc r17, perfmon_en_ctr2 // do not enable ctr1
-
- blbc r9, perfmon_en_noclr1 // if enclr flag set, clear ctr1 field
- lda r8, 0xffff(r31)
- zapnot r8, 3, r8 // ctr1<15:0> mask
- sll r8, pmctr_v_ctr1, r8
- bic r14, r8, r14 // clear ctr bits
- bic r13, r8, r13 // clear ctr bits
-
-perfmon_en_noclr1:
-//orig get_addr r8, 3<<pmctr_v_ctl1, r31
- LDLI(r8, (3<<pmctr_v_ctl1))
- and r25, r8, r12 //isolate frequency select bits for ctr1
- bic r14, r8, r14 // clear ctl1 bits in preparation for enabling
- or r14,r12,r14 // or in new ctl1 bits
-
-perfmon_en_ctr2: // enable ctr2
- srl r17, 1, r17 // get ctr2 enable
- blbc r17, perfmon_en_return // do not enable ctr2 - return
-
- blbc r9, perfmon_en_noclr2 // if enclr flag set, clear ctr2 field
- lda r8, 0x3FFF(r31) // ctr2<13:0> mask
- sll r8, pmctr_v_ctr2, r8
- bic r14, r8, r14 // clear ctr bits
- bic r13, r8, r13 // clear ctr bits
-
-perfmon_en_noclr2:
-//orig get_addr r8, 3<<pmctr_v_ctl2, r31
- LDLI(r8, (3<<pmctr_v_ctl2))
- and r25, r8, r12 //isolate frequency select bits for ctr2
- bic r14, r8, r14 // clear ctl2 bits in preparation for enabling
- or r14,r12,r14 // or in new ctl2 bits
-
-perfmon_en_return:
- cmovlbs r16, r14, r13 // if pme enabled, move enables into pmctr
- // else only do the counter clears
- mtpr r13, ev5__pmctr // update pmctr ipr
-
-//;this code not needed for pass2 and later, but does not hurt to leave it in
- lda r8, 0x3F(r31)
-//orig get_pmctr_ctl r25, r12 // read pmctr ctl; r12=adjusted impure pointer
- mfpr r12, pt_impure
- lda r12, CNS_Q_IPR(r12)
- RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r12);
-
- sll r8, pmctr_v_ctl2, r8 // build ctl mask
- and r8, r14, r14 // isolate new ctl bits
- bic r25, r8, r25 // clear out old ctl value
- or r25, r14, r14 // create new pmctr_ctl
-//orig store_reg1 pmctr_ctl, r14, r12, ipr=1
- SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
-
- br r31, perfmon_success
-
-
-// options...
-perfmon_ctl:
-
-// set mode
-//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer
- mfpr r12, pt_impure
- lda r12, CNS_Q_IPR(r12)
- RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12);
-
-//orig get_addr r8, (1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk), r31 // build mode mask for pmctr register
- LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk)))
- mfpr r0, ev5__pmctr
- and r17, r8, r25 // isolate pmctr mode bits
- bic r0, r8, r0 // clear old mode bits
- or r0, r25, r25 // or in new mode bits
- mtpr r25, ev5__pmctr
-
-//;the following code will only be used in pass2, but should not hurt anything if run in pass1.
- mfpr r8, icsr
- lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0
- bic r8, r25, r8 // clear old pma bit
- cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1
- or r8, r25, r8
- ev5_pass2 mtpr r8, icsr // 4 bubbles to hw_rei
- mfpr r31, pt0 // pad icsr write
- mfpr r31, pt0 // pad icsr write
-
-//;the following code not needed for pass2 and later, but should work anyway.
- bis r14, 1, r14 // set for select processes
- blbs r17, perfmon_sp // branch if select processes
- bic r14, 1, r14 // all processes
-perfmon_sp:
-//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register
- SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
- br r31, perfmon_success
-
-// counter frequency select
-perfmon_freq:
-//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer
- mfpr r12, pt_impure
- lda r12, CNS_Q_IPR(r12)
- RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12);
-
- lda r8, 0x3F(r31)
-//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field
-// I guess this should be a shift of 4 bits from the above control register structure .. pb
-#define pmctr_ctl_v_frq2_SHIFT 4
- sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field
-
- and r8, r17, r17
- bic r14, r8, r14 // clear out old frequency select bits
-
- or r17, r14, r14 // or in new frequency select info
-//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register
- SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
-
- br r31, perfmon_success
-
-// read counters
-perfmon_rd:
- mfpr r0, ev5__pmctr
- or r0, 1, r0 // or in return status
- hw_rei // back to user
-
-// write counters
-perfmon_wr:
- mfpr r14, ev5__pmctr
- lda r8, 0x3FFF(r31) // ctr2<13:0> mask
- sll r8, pmctr_v_ctr2, r8
-
-//orig get_addr r9, 0xFFFFFFFF, r31, verify=0 // ctr2<15:0>,ctr1<15:0> mask
- LDLI(r9, (0xFFFFFFFF))
- sll r9, pmctr_v_ctr1, r9
- or r8, r9, r8 // or ctr2, ctr1, ctr0 mask
- bic r14, r8, r14 // clear ctr fields
- and r17, r8, r25 // clear all but ctr fields
- or r25, r14, r14 // write ctr fields
- mtpr r14, ev5__pmctr // update pmctr ipr
-
- mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy)
-
-perfmon_success:
- or r31, 1, r0 // set success
- hw_rei // back to user
-
-perfmon_unknown:
- or r31, r31, r0 // set fail
- hw_rei // back to user
-
-#else
-
-// end of "real code", start of debug code
-
-//+
-// Debug environment:
-// (in pass2, always set icsr<pma> to ensure master counter enable is on)
-// R16 = 0 Write to on-chip performance monitor ipr
-// r17 = on-chip ipr
-// r0 = return value of read of on-chip performance monitor ipr
-// R16 = 1 Setup Cbox mux selects
-// r17 = Cbox mux selects in same position as in bc_ctl ipr.
-// r0 = return value of read of on-chip performance monitor ipr
-//
-//-
-pal_perfmon_debug:
- mfpr r8, icsr
- lda r9, 1<<icsr_v_pma(r31)
- bis r8, r9, r8
- mtpr r8, icsr
-
- mfpr r0, ev5__pmctr // read old value
- bne r16, cbox_mux_sel
-
- mtpr r17, ev5__pmctr // update pmctr ipr
- br r31, end_pm
-
-cbox_mux_sel:
- // ok, now tackle cbox mux selects
- ldah r14, 0xfff0(r31)
- zap r14, 0xE0, r14 // Get Cbox IPR base
-//orig get_bc_ctl_shadow r16 // bc_ctl returned
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
-
- lda r8, 0x3F(r31) // build mux select mask
- sll r8, BC_CTL_V_PM_MUX_SEL, r8
-
- and r17, r8, r25 // isolate bc_ctl mux select bits
- bic r16, r8, r16 // isolate old mux select bits
- or r16, r25, r25 // create new bc_ctl
- mb // clear out cbox for future ipr write
- stqp r25, ev5__bc_ctl(r14) // store to cbox ipr
- mb // clear out cbox for future ipr write
-//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
- mfpr r16, pt_impure
- lda r16, CNS_Q_IPR(r16)
- SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
-
-end_pm: hw_rei
-
-#endif
-
-
-//;The following code is a workaround for a cpu bug where Istream prefetches to
-//;super-page address space in user mode may escape off-chip.
-#if spe_fix != 0
-
- ALIGN_BLOCK
-hw_rei_update_spe:
- mfpr r12, pt_misc // get previous mode
- srl r11, osfps_v_mode, r10 // isolate current mode bit
- and r10, 1, r10
- extbl r12, 7, r8 // get previous mode field
- and r8, 1, r8 // isolate previous mode bit
- cmpeq r10, r8, r8 // compare previous and current modes
- beq r8, hw_rei_update_spe_5_
- hw_rei // if same, just return
-
-hw_rei_update_spe_5_:
-
-#if fill_err_hack != 0
-
- fill_error_hack
-#endif
-
- mfpr r8, icsr // get current icsr value
- ldah r9, (2<<(icsr_v_spe-16))(r31) // get spe bit mask
- bic r8, r9, r8 // disable spe
- xor r10, 1, r9 // flip mode for new spe bit
- sll r9, icsr_v_spe+1, r9 // shift into position
- bis r8, r9, r8 // enable/disable spe
- lda r9, 1(r31) // now update our flag
- sll r9, pt_misc_v_cm, r9 // previous mode saved bit mask
- bic r12, r9, r12 // clear saved previous mode
- sll r10, pt_misc_v_cm, r9 // current mode saved bit mask
- bis r12, r9, r12 // set saved current mode
- mtpr r12, pt_misc // update pt_misc
- mtpr r8, icsr // update icsr
-
-#if osf_chm_fix != 0
-
-
- blbc r10, hw_rei_update_spe_10_ // branch if not user mode
-
- mb // ensure no outstanding fills
- lda r12, 1<<dc_mode_v_dc_ena(r31) // User mode
- mtpr r12, dc_mode // Turn on dcache
- mtpr r31, dc_flush // and flush it
- br r31, pal_ic_flush
-
-hw_rei_update_spe_10_: mfpr r9, pt_pcbb // Kernel mode
- ldqp r9, osfpcb_q_Fen(r9) // get FEN
- blbc r9, pal_ic_flush // return if FP disabled
- mb // ensure no outstanding fills
- mtpr r31, dc_mode // turn off dcache
-#endif
-
-
- br r31, pal_ic_flush // Pal restriction - must flush Icache if changing ICSR<SPE>
-#endif
-
-
-copypal_impl:
- mov r16, r0
- bic r18, 63, r8
- and r18, 63, r18
- beq r8, cache_copy_done
-cache_loop:
- ldf f17, 0(r16)
- stf f17, 0(r16)
- addq r17, 64, r17
- addq r16, 64, r16
- subq r8, 64, r8
- bne r8, cache_loop
-cache_copy_done:
- ble r18, finished #if len <=0 we are finished
- ldq_u r8, 0(r17)
- xor r17, r16, r9
- and r9, 7, r9
- and r16, 7, r10
- bne r9, unaligned
- beq r10, aligned
- ldq_u r9, 0(r16)
- addq r18, r10, r18
- mskqh r8, r17, r8
- mskql r9, r17, r9
- bis r8, r9, r8
-aligned:
- subq r18, 1, r10
- bic r10, 7, r10
- and r18, 7, r18
- beq r10, aligned_done
-loop:
- stq_u r8, 0(r16)
- ldq_u r8, 8(r17)
- subq r10, 8, r10
- lda r16,8(r16)
- lda r17,8(r17)
- bne r10, loop
-aligned_done:
- bne r18, few_left
- stq_u r8, 0(r16)
- br r31, finished
- few_left:
- mskql r8, r18, r10
- ldq_u r9, 0(r16)
- mskqh r9, r18, r9
- bis r10, r9, r10
- stq_u r10, 0(r16)
- br r31, finished
-unaligned:
- addq r17, r18, r25
- cmpule r18, 8, r9
- bne r9, unaligned_few_left
- beq r10, unaligned_dest_aligned
- and r16, 7, r10
- subq r31, r10, r10
- addq r10, 8, r10
- ldq_u r9, 7(r17)
- extql r8, r17, r8
- extqh r9, r17, r9
- bis r8, r9, r12
- insql r12, r16, r12
- ldq_u r13, 0(r16)
- mskql r13, r16, r13
- bis r12, r13, r12
- stq_u r12, 0(r16)
- addq r16, r10, r16
- addq r17, r10, r17
- subq r18, r10, r18
- ldq_u r8, 0(r17)
-unaligned_dest_aligned:
- subq r18, 1, r10
- bic r10, 7, r10
- and r18, 7, r18
- beq r10, unaligned_partial_left
-unaligned_loop:
- ldq_u r9, 7(r17)
- lda r17, 8(r17)
- extql r8, r17, r12
- extqh r9, r17, r13
- subq r10, 8, r10
- bis r12, r13, r13
- stq r13, 0(r16)
- lda r16, 8(r16)
- beq r10, unaligned_second_partial_left
- ldq_u r8, 7(r17)
- lda r17, 8(r17)
- extql r9, r17, r12
- extqh r8, r17, r13
- bis r12, r13, r13
- subq r10, 8, r10
- stq r13, 0(r16)
- lda r16, 8(r16)
- bne r10, unaligned_loop
-unaligned_partial_left:
- mov r8, r9
-unaligned_second_partial_left:
- ldq_u r8, -1(r25)
- extql r9, r17, r9
- extqh r8, r17, r8
- bis r8, r9, r8
- bne r18, few_left
- stq_u r8, 0(r16)
- br r31, finished
-unaligned_few_left:
- ldq_u r9, -1(r25)
- extql r8, r17, r8
- extqh r9, r17, r9
- bis r8, r9, r8
- insqh r8, r16, r9
- insql r8, r16, r8
- lda r12, -1(r31)
- mskql r12, r18, r13
- cmovne r13, r13, r12
- insqh r12, r16, r13
- insql r12, r16, r12
- addq r16, r18, r10
- ldq_u r14, 0(r16)
- ldq_u r25, -1(r10)
- bic r14, r12, r14
- bic r25, r13, r25
- and r8, r12, r8
- and r9, r13, r9
- bis r8, r14, r8
- bis r9, r25, r9
- stq_u r9, -1(r10)
- stq_u r8, 0(r16)
-finished:
- hw_rei
--- /dev/null
+/*
+ * Copyright (c) 2003, 2004, 2005
+ * The Regents of The University of Michigan
+ * All Rights Reserved
+ *
+ * This code is part of the M5 simulator, developed by Nathan Binkert,
+ * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
+ * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
+ * Schultz.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * redistribute this software and such derivative works for any
+ * purpose, so long as the copyright notice above, this grant of
+ * permission, and the disclaimer below appear in all copies made; and
+ * so long as the name of The University of Michigan is not used in
+ * any advertising or publicity pertaining to the use or distribution
+ * of this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+ * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
+ * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
+ * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
+ * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
+ * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
+ * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
+ * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGES.
+ */
+
+/*
+ * Copyright 1993 Hewlett-Packard Development Company, L.P.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#define max_cpuid 1
+#define hw_rei_spe hw_rei
+
+#include "ev5_defs.h"
+#include "ev5_impure.h"
+#include "ev5_alpha_defs.h"
+#include "ev5_paldef.h"
+#include "ev5_osfalpha_defs.h"
+#include "fromHudsonMacros.h"
+#include "fromHudsonOsf.h"
+#include "dc21164FromGasSources.h"
+#include "cserve.h"
+#include "tlaser.h"
+
+#define pt_entInt pt_entint
+#define pt_entArith pt_entarith
+#define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8)
+#define mchk_flag CNS_Q_FLAG
+#define mchk_sys_base 56
+#define mchk_cpu_base (CNS_Q_LD_LOCK + 8)
+#define mchk_offsets CNS_Q_EXC_ADDR
+#define mchk_mchk_code 8
+#define mchk_ic_perr_stat CNS_Q_ICPERR_STAT
+#define mchk_dc_perr_stat CNS_Q_DCPERR_STAT
+#define mchk_sc_addr CNS_Q_SC_ADDR
+#define mchk_sc_stat CNS_Q_SC_STAT
+#define mchk_ei_addr CNS_Q_EI_ADDR
+#define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR
+#define mchk_fill_syn CNS_Q_FILL_SYN
+#define mchk_ei_stat CNS_Q_EI_STAT
+#define mchk_exc_addr CNS_Q_EXC_ADDR
+#define mchk_ld_lock CNS_Q_LD_LOCK
+#define osfpcb_q_Ksp pcb_q_ksp
+#define pal_impure_common_size ((0x200 + 7) & 0xfff8)
+
+#if defined(BIG_TSUNAMI)
+#define MAXPROC 0x3f
+#define IPIQ_addr 0x800
+#define IPIQ_shift 0
+#define IPIR_addr 0x840
+#define IPIR_shift 0
+#define RTC_addr 0x880
+#define RTC_shift 0
+#define DIR_addr 0xa2
+#elif defined(TSUNAMI)
+#define MAXPROC 0x3
+#define IPIQ_addr 0x080
+#define IPIQ_shift 12
+#define IPIR_addr 0x080
+#define IPIR_shift 8
+#define RTC_addr 0x080
+#define RTC_shift 4
+#define DIR_addr 0xa0
+#elif defined(TLASER)
+#define MAXPROC 0xf
+#else
+#error Must define BIG_TSUNAMI, TSUNAMI, or TLASER
+#endif
+
+#define ALIGN_BLOCK \
+ .align 5
+
+#define ALIGN_BRANCH \
+ .align 3
+
+#define EXPORT(_x) \
+ .align 5; \
+ .globl _x; \
+_x:
+
+// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+// XXX the following is 'made up'
+// XXX bugnion
+
+// XXX bugnion not sure how to align 'quad'
+#define ALIGN_QUAD \
+ .align 3
+
+#define ALIGN_128 \
+ .align 7
+
+
+#define GET_IMPURE(_r) mfpr _r,pt_impure
+#define GET_ADDR(_r1,_off,_r2) lda _r1,_off(_r2)
+
+
+#define BIT(_x) (1<<(_x))
+
+
+// System specific code - beh model version
+//
+//
+// Entry points
+// SYS_CFLUSH - Cache flush
+// SYS_CSERVE - Console service
+// SYS_WRIPIR - interprocessor interrupts
+// SYS_HALT_INTERRUPT - Halt interrupt
+// SYS_PASSIVE_RELEASE - Interrupt, passive release
+// SYS_INTERRUPT - Interrupt
+// SYS_RESET - Reset
+// SYS_ENTER_CONSOLE
+//
+//
+// Macro to read TLINTRSUMx
+//
+// Based on the CPU_NUMBER, read either the TLINTRSUM0 or TLINTRSUM1 register
+//
+// Assumed register usage:
+// rsum TLINTRSUMx contents
+// raddr node space address
+// scratch scratch register
+//
+#define Read_TLINTRSUMx(_rsum, _raddr, _scratch) \
+ nop; \
+ mfpr _scratch, pt_whami; /* Get our whami (VID) */ \
+ extbl _scratch, 1, _scratch; /* shift down to bit 0 */ \
+ lda _raddr, 0xff88(zero); /* Get base node space address bits */ \
+ sll _raddr, 24, _raddr; /* Shift up to proper position */ \
+ srl _scratch, 1, _rsum; /* Shift off the cpu number */ \
+ sll _rsum, 22, _rsum; /* Get our node offset */ \
+ addq _raddr, _rsum, _raddr; /* Get our base node space address */ \
+ blbs _scratch, 1f; \
+ lda _raddr, 0x1180(_raddr); \
+ br r31, 2f; \
+1: lda _raddr, 0x11c0(_raddr); \
+2: ldl_p _rsum, 0(_raddr) /* read the right tlintrsum reg */
+
+//
+// Macro to write TLINTRSUMx
+//
+// Based on the CPU_NUMBER, write either the TLINTRSUM0 or TLINTRSUM1 register
+//
+// Assumed register usage:
+// rsum TLINTRSUMx write data
+// raddr node space address
+// scratch scratch register
+//
+#define Write_TLINTRSUMx(_rsum,_raddr,_whami) \
+ nop; \
+ mfpr _whami, pt_whami; /* Get our whami (VID) */ \
+ extbl _whami, 1, _whami; /* shift down to bit 0 */ \
+ lda _raddr, 0xff88(zero); /* Get base node space address bits */ \
+ sll _raddr, 24, _raddr; /* Shift up to proper position */ \
+ blbs _whami, 1f; \
+ lda _raddr, 0x1180(_raddr); \
+ br zero, 2f; \
+1: lda _raddr, 0x11c0(_raddr); \
+2: srl _whami, 1, _whami; /* Get our node offset */ \
+ addq _raddr, _whami, _raddr; /* Get our base node space address */ \
+ mb; \
+ stq_p _rsum, 0(_raddr); /* write the right tlintrsum reg */ \
+ ldq_p _rsum, 0(_raddr); /* dummy read to tlintrsum */ \
+ bis _rsum, _rsum, _rsum /* needed to complete the ldqp above */
+
+
+//
+// Macro to determine highest priority TIOP Node ID from interrupt pending mask
+//
+// Assumed register usage:
+// rmask - TLINTRSUMx contents, shifted to isolate IOx bits
+// rid - TLSB Node ID of highest TIOP
+//
+#define Intr_Find_TIOP(_rmask,_rid) \
+ srl _rmask,3,_rid; /* check IOP8 */ \
+ blbc _rid,1f; /* not IOP8 */ \
+ lda _rid,8(zero); /* IOP8 */ \
+ br zero,6f; \
+1: srl _rmask,3,_rid; /* check IOP7 */ \
+ blbc _rid, 2f; /* not IOP7 */ \
+ lda _rid, 7(r31); /* IOP7 */ \
+ br r31, 6f; \
+2: srl _rmask, 2, _rid; /* check IOP6 */ \
+ blbc _rid, 3f; /* not IOP6 */ \
+ lda _rid, 6(r31); /* IOP6 */ \
+ br r31, 6f; \
+3: srl _rmask, 1, _rid; /* check IOP5 */ \
+ blbc _rid, 4f; /* not IOP5 */ \
+ lda _rid, 5(r31); /* IOP5 */ \
+ br r31, 6f; \
+4: srl _rmask, 0, _rid; /* check IOP4 */ \
+ blbc _rid, 5f; /* not IOP4 */ \
+ lda r14, 4(r31); /* IOP4 */ \
+ br r31, 6f; \
+5: lda r14, 0(r31); /* passive release */ \
+6:
+
+//
+// Macro to calculate base node space address for given node id
+//
+// Assumed register usage:
+// rid - TLSB node id
+// raddr - base node space address
+#define Get_TLSB_Node_Address(_rid,_raddr) \
+ sll _rid, 22, _rid; \
+ lda _raddr, 0xff88(zero); \
+ sll _raddr, 24, _raddr; \
+ addq _raddr, _rid, _raddr
+
+
+#define OSFmchk_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
+ lda _rs1, tlep_##_tlepreg(zero); \
+ or _rs1, _nodebase, _rs1; \
+ ldl_p _rs1, 0(_rs1); \
+ stl_p _rs, mchk_##_tlepreg(_rlog) /* store in frame */
+
+#define OSFmchk_TLEPstore(_tlepreg) \
+ OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
+
+#define OSFcrd_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
+ lda _rs1, tlep_##_tlepreg(zero); \
+ or _rs1, _nodebase, _rs1; \
+ ldl_p _rs1, 0(_rs1); \
+ stl_p _rs, mchk_crd_##_tlepreg(_rlog)
+
+#define OSFcrd_TLEPstore_tlsb_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
+ lda _rs1, tlsb_##_tlepreg(zero); \
+ or _rs1, _nodebase, _rs1; \
+ ldl_p _rs1, 0(_rs1); \
+ stl_p _rs,mchk_crd_##_tlepreg(_rlog)
+
+#define OSFcrd_TLEPstore_tlsb_clr_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
+ lda _rs1,tlsb_##_tlepreg(zero); \
+ or _rs1, _nodebase,_rs1; \
+ ldl_p _rs1, 0(_rs1); \
+ stl_p _rs, mchk_crd_##_tlepreg(_rlog); \
+ stl_p _rs, 0(_rs1)
+
+#define OSFcrd_TLEPstore(_tlepreg) \
+ OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
+#define OSFcrd_TLEPstore_tlsb(_tlepreg) \
+ OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg)
+#define OSFcrd_TLEPstore_tlsb_clr(_tlepreg) \
+ OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg)
+
+
+#define save_pcia_intr(_irq) \
+ and r13, 0xf, r25; /* isolate low 4 bits */ \
+ addq r14, 4, r14; /* format the TIOP Node id field */ \
+ sll r14, 4, r14; /* shift the TIOP Node id */ \
+ or r14, r25, r10; /* merge Node id/hose/HPC */ \
+ mfpr r14, pt14; /* get saved value */ \
+ extbl r14, _irq, r25; /* confirm none outstanding */ \
+ bne r25, sys_machine_check_while_in_pal; \
+ insbl r10, _irq, r10; /* align new info */ \
+ or r14, r10, r14; /* merge info */ \
+ mtpr r14, pt14; /* save it */ \
+ bic r13, 0xf, r13 /* clear low 4 bits of vector */
+
+
+// wripir - PALcode for wripir instruction
+// R16 has the processor number.
+//
+ ALIGN_BLOCK
+EXPORT(sys_wripir)
+ //
+ // Convert the processor number to a CPU mask
+ //
+ and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported
+ bis r31, 0x1, r16 // get a one
+ sll r16, r14, r14 // shift the bit to the right place
+
+ //
+ // Build the Broadcast Space base address
+ //
+ lda r13, 0xff8e(r31) // Load the upper address bits
+ sll r13, 24, r13 // shift them to the top
+
+ //
+ // Send out the IP Intr
+ //
+ stq_p r14, 0x40(r13) // Write to TLIPINTR reg
+ wmb // Push out the store
+ hw_rei
+
+
+// cflush - PALcode for CFLUSH instruction
+//
+// SYS_CFLUSH
+// Entry:
+// R16 - contains the PFN of the page to be flushed
+//
+// Function:
+// Flush all Dstream caches of 1 entire page
+//
+//
+ ALIGN_BLOCK
+EXPORT(sys_cflush)
+
+// #convert pfn to addr, and clean off <63:20>
+// #sll r16, <page_offset_size_bits>+<63-20>>, r12
+ sll r16, page_offset_size_bits+(63-20),r12
+
+// #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16>
+// # stolen from srcmax code. XXX bugnion
+ lda r13, 0x10(r31) // assume 16Mbytes of cache
+ sll r13, 20, r13 // convert to bytes
+
+
+ srl r12, 63-20, r12 // shift back to normal position
+ xor r12, r13, r12 // xor addr<18>
+
+ or r31, 8192/(32*8), r13 // get count of loads
+ nop
+
+cflush_loop:
+ subq r13, 1, r13 // decr counter
+ mfpr r25, ev5__intid // Fetch level of interruptor
+
+ ldq_p r31, 32*0(r12) // do a load
+ ldq_p r31, 32*1(r12) // do next load
+
+ ldq_p r31, 32*2(r12) // do next load
+ ldq_p r31, 32*3(r12) // do next load
+
+ ldq_p r31, 32*4(r12) // do next load
+ ldq_p r31, 32*5(r12) // do next load
+
+ ldq_p r31, 32*6(r12) // do next load
+ ldq_p r31, 32*7(r12) // do next load
+
+ mfpr r14, ev5__ipl // Fetch current level
+ lda r12, (32*8)(r12) // skip to next cache block addr
+
+ cmple r25, r14, r25 // R25 = 1 if intid .less than or eql ipl
+ beq r25, 1f // if any int's pending, re-queue CFLUSH -- need to check for hlt interrupt???
+
+ bne r13, cflush_loop // loop till done
+ hw_rei // back to user
+
+ ALIGN_BRANCH
+1: // Here if interrupted
+ mfpr r12, exc_addr
+ subq r12, 4, r12 // Backup PC to point to CFLUSH
+
+ mtpr r12, exc_addr
+ nop
+
+ mfpr r31, pt0 // Pad exc_addr write
+ hw_rei
+
+
+ ALIGN_BLOCK
+//
+// sys_cserve - PALcode for CSERVE instruction
+//
+// Function:
+// Various functions for private use of console software
+//
+// option selector in r0
+// arguments in r16....
+//
+//
+// r0 = 0 unknown
+//
+// r0 = 1 ldq_p
+// r0 = 2 stq_p
+// args, are as for normal STQ_P/LDQ_P in VMS PAL
+//
+// r0 = 3 dump_tb's
+// r16 = detination PA to dump tb's to.
+//
+// r0<0> = 1, success
+// r0<0> = 0, failure, or option not supported
+// r0<63:1> = (generally 0, but may be function dependent)
+// r0 - load data on ldq_p
+//
+//
+EXPORT(sys_cserve)
+
+ /* taken from scrmax */
+ cmpeq r18, CSERVE_K_RD_IMPURE, r0
+ bne r0, Sys_Cserve_Rd_Impure
+
+ cmpeq r18, CSERVE_K_JTOPAL, r0
+ bne r0, Sys_Cserve_Jtopal
+ call_pal 0
+
+ or r31, r31, r0
+ hw_rei // and back we go
+
+Sys_Cserve_Rd_Impure:
+ mfpr r0, pt_impure // Get base of impure scratch area.
+ hw_rei
+
+ ALIGN_BRANCH
+
+Sys_Cserve_Jtopal:
+ bic a0, 3, t8 // Clear out low 2 bits of address
+ bis t8, 1, t8 // Or in PAL mode bit
+ mtpr t8,exc_addr
+ hw_rei
+
+ // ldq_p
+ ALIGN_QUAD
+1:
+ ldq_p r0,0(r17) // get the data
+ nop // pad palshadow write
+
+ hw_rei // and back we go
+
+
+ // stq_p
+ ALIGN_QUAD
+2:
+ stq_p r18, 0(r17) // store the data
+ lda r0,17(r31) // bogus
+ hw_rei // and back we go
+
+
+ ALIGN_QUAD
+csrv_callback:
+ ldq r16, 0(r17) // restore r16
+ ldq r17, 8(r17) // restore r17
+ lda r0, hlt_c_callback(r31)
+ br r31, sys_enter_console
+
+
+csrv_identify:
+ mfpr r0, pal_base
+ ldq_p r0, 8(r0)
+ hw_rei
+
+
+// dump tb's
+ ALIGN_QUAD
+0:
+ // DTB PTEs - 64 entries
+ addq r31, 64, r0 // initialize loop counter
+ nop
+
+1: mfpr r12, ev5__dtb_pte_temp // read out next pte to temp
+ mfpr r12, ev5__dtb_pte // read out next pte to reg file
+
+ subq r0, 1, r0 // decrement loop counter
+ nop // Pad - no Mbox instr in cycle after mfpr
+
+ stq_p r12, 0(r16) // store out PTE
+ addq r16, 8 ,r16 // increment pointer
+
+ bne r0, 1b
+
+ ALIGN_BRANCH
+ // ITB PTEs - 48 entries
+ addq r31, 48, r0 // initialize loop counter
+ nop
+
+2: mfpr r12, ev5__itb_pte_temp // read out next pte to temp
+ mfpr r12, ev5__itb_pte // read out next pte to reg file
+
+ subq r0, 1, r0 // decrement loop counter
+ nop //
+
+ stq_p r12, 0(r16) // store out PTE
+ addq r16, 8 ,r16 // increment pointer
+
+ bne r0, 2b
+ or r31, 1, r0 // set success
+
+ hw_rei // and back we go
+
+
+//
+// SYS_INTERRUPT - Interrupt processing code
+//
+// Current state:
+// Stack is pushed
+// ps, sp and gp are updated
+// r12, r14 - available
+// r13 - INTID (new EV5 IPL)
+// r25 - ISR
+// r16, r17, r18 - available
+//
+//
+EXPORT(sys_interrupt)
+ cmpeq r13, 31, r12 // Check for level 31 interrupt
+ bne r12, sys_int_mchk_or_crd // machine check or crd
+
+ cmpeq r13, 30, r12 // Check for level 30 interrupt
+ bne r12, sys_int_powerfail // powerfail
+
+ cmpeq r13, 29, r12 // Check for level 29 interrupt
+ bne r12, sys_int_perf_cnt // performance counters
+
+ cmpeq r13, 23, r12 // Check for level 23 interrupt
+ bne r12, sys_int_23 // IPI in Tsunami
+
+ cmpeq r13, 22, r12 // Check for level 22 interrupt
+ bne r12, sys_int_22 // timer interrupt
+
+ cmpeq r13, 21, r12 // Check for level 21 interrupt
+ bne r12, sys_int_21 // I/O
+
+ cmpeq r13, 20, r12 // Check for level 20 interrupt
+ bne r12, sys_int_20 // system error interrupt
+ // (might be corrected)
+
+ mfpr r14, exc_addr // ooops, something is wrong
+ br r31, pal_pal_bug_check_from_int
+
+
+//
+//sys_int_2*
+// Routines to handle device interrupts at IPL 23-20.
+// System specific method to ack/clear the interrupt, detect passive
+// release, detect interprocessor (22), interval clock (22), corrected
+// system error (20)
+//
+// Current state:
+// Stack is pushed
+// ps, sp and gp are updated
+// r12, r14 - available
+// r13 - INTID (new EV5 IPL)
+// r25 - ISR
+//
+// On exit:
+// Interrupt has been ack'd/cleared
+// a0/r16 - signals IO device interrupt
+// a1/r17 - contains interrupt vector
+// exit to ent_int address
+//
+//
+
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ ALIGN_BRANCH
+sys_int_23:
+ or r31,0,r16 // IPI interrupt A0 = 0
+ lda r12,0xf01(r31) // build up an address for the MISC register
+ sll r12,16,r12
+ lda r12,0xa000(r12)
+ sll r12,16,r12
+ lda r12,IPIR_addr(r12)
+
+ mfpr r10, pt_whami // get CPU ID
+ extbl r10, 1, r10 // Isolate just whami bits
+ or r31,0x1,r14 // load r14 with bit to clear
+ sll r14,r10,r14 // left shift by CPU ID
+ sll r14,IPIR_shift,r14
+ stq_p r14, 0(r12) // clear the ipi interrupt
+
+ br r31, pal_post_interrupt // Notify the OS
+
+
+ ALIGN_BRANCH
+sys_int_22:
+ or r31,1,r16 // a0 means it is a clock interrupt
+ lda r12,0xf01(r31) // build up an address for the MISC register
+ sll r12,16,r12
+ lda r12,0xa000(r12)
+ sll r12,16,r12
+ lda r12,RTC_addr(r12)
+
+ mfpr r10, pt_whami // get CPU ID
+ extbl r10, 1, r10 // Isolate just whami bits
+ or r31,0x1,r14 // load r14 with bit to clear
+ sll r14,r10,r14 // left shift by CPU ID
+ sll r14,RTC_shift,r14 // put the bits in the right position
+ stq_p r14, 0(r12) // clear the rtc interrupt
+
+ br r31, pal_post_interrupt // Tell the OS
+
+
+ ALIGN_BRANCH
+sys_int_20:
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ srl r13, 12, r13 // shift down to examine IPL15
+
+ Intr_Find_TIOP(r13,r14)
+ beq r14, 1f
+
+ Get_TLSB_Node_Address(r14,r10)
+ lda r10, 0xa40(r10) // Get base TLILID address
+
+ ldl_p r13, 0(r10) // Read the TLILID register
+ bne r13, pal_post_dev_interrupt
+ beq r13, 1f
+
+ and r13, 0x3, r10 // check for PCIA bits
+ beq r10, pal_post_dev_interrupt // done if nothing set
+ save_pcia_intr(1)
+ br r31, pal_post_dev_interrupt //
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+sys_int_21:
+
+ lda r12,0xf01(r31) // calculate DIRn address
+ sll r12,32,r12
+ ldah r13,DIR_addr(r31)
+ sll r13,8,r13
+ bis r12,r13,r12
+
+ mfpr r13, pt_whami // get CPU ID
+ extbl r13, 1, r13 // Isolate just whami bits
+
+#ifdef BIG_TSUNAMI
+ sll r13,4,r13
+ or r12,r13,r12
+#else
+ lda r12,0x0080(r12)
+ and r13,0x1,r14 // grab LSB and shift left 6
+ sll r14,6,r14
+ and r13,0x2,r10 // grabl LSB+1 and shift left 9
+ sll r10,9,r10
+
+ mskbl r12,0,r12 // calculate DIRn address
+ lda r13,0x280(r31)
+ bis r12,r13,r12
+ or r12,r14,r12
+ or r12,r10,r12
+#endif
+
+ ldq_p r13, 0(r12) // read DIRn
+
+ or r31,1,r14 // set bit 55 (ISA Interrupt)
+ sll r14,55,r14
+
+ and r13, r14, r14 // check if bit 55 is set
+ lda r16,0x900(r31) // load offset for normal into r13
+ beq r14, normal_int // if not compute the vector normally
+
+ lda r16,0x800(r31) // replace with offset for pic
+ lda r12,0xf01(r31) // build an addr to access PIC
+ sll r12,32,r12 // at f01fc000000
+ ldah r13,0xfc(r31)
+ sll r13,8,r13
+ bis r12,r13,r12
+ ldq_p r13,0x0020(r12) // read PIC1 ISR for interrupting dev
+
+normal_int:
+ //ctlz r13,r14 // count the number of leading zeros
+ // EV5 doesn't have ctlz, but we do, so lets use it
+ .byte 0x4e
+ .byte 0x06
+ .byte 0xed
+ .byte 0x73
+ lda r10,63(r31)
+ subq r10,r14,r17 // subtract from
+
+ lda r13,0x10(r31)
+ mulq r17,r13,r17 // compute 0x900 + (0x10 * Highest DIRn-bit)
+ addq r17,r16,r17
+
+ or r31,3,r16 // a0 means it is a I/O interrupt
+
+ br r31, pal_post_interrupt
+
+#elif defined(TLASER)
+ ALIGN_BRANCH
+sys_int_23:
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ srl r13, 22, r13 // shift down to examine IPL17
+
+ Intr_Find_TIOP(r13,r14)
+ beq r14, 1f
+
+ Get_TLSB_Node_Address(r14,r10)
+ lda r10, 0xac0(r10) // Get base TLILID address
+
+ ldl_p r13, 0(r10) // Read the TLILID register
+ bne r13, pal_post_dev_interrupt
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+sys_int_22:
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ srl r13, 6, r14 // check the Intim bit
+
+ blbs r14, tlep_intim // go service Intim
+ srl r13, 5, r14 // check the IP Int bit
+
+ blbs r14, tlep_ipint // go service IP Int
+ srl r13, 17, r13 // shift down to examine IPL16
+
+ Intr_Find_TIOP(r13,r14)
+ beq r14, 1f
+
+ Get_TLSB_Node_Address(r14,r10)
+ lda r10, 0xa80(r10) // Get base TLILID address
+
+ ldl_p r13, 0(r10) // Read the TLILID register
+ bne r13, pal_post_dev_interrupt
+ beq r13, 1f
+
+ and r13, 0x3, r10 // check for PCIA bits
+ beq r10, pal_post_dev_interrupt // done if nothing set
+ save_pcia_intr(2)
+ br r31, pal_post_dev_interrupt //
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+sys_int_21:
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ srl r13, 12, r13 // shift down to examine IPL15
+
+ Intr_Find_TIOP(r13,r14)
+ beq r14, 1f
+
+ Get_TLSB_Node_Address(r14,r10)
+ lda r10, 0xa40(r10) // Get base TLILID address
+
+ ldl_p r13, 0(r10) // Read the TLILID register
+ bne r13, pal_post_dev_interrupt
+ beq r13, 1f
+
+ and r13, 0x3, r10 // check for PCIA bits
+ beq r10, pal_post_dev_interrupt // done if nothing set
+ save_pcia_intr(1)
+ br r31, pal_post_dev_interrupt //
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+sys_int_20:
+ lda r13, 1(r31) // Duart0 bit
+ Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
+
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ blbs r13, tlep_uart0 // go service UART int
+
+ srl r13, 7, r13 // shift down to examine IPL14
+ Intr_Find_TIOP(r13,r14)
+
+ beq r14, tlep_ecc // Branch if not IPL14
+ Get_TLSB_Node_Address(r14,r10)
+
+ lda r10, 0xa00(r10) // Get base TLILID0 address
+ ldl_p r13, 0(r10) // Read the TLILID register
+
+ bne r13, pal_post_dev_interrupt
+ beq r13, 1f
+
+ and r13, 0x3, r10 // check for PCIA bits
+ beq r10, pal_post_dev_interrupt // done if nothing set
+ save_pcia_intr(0)
+ br r31, pal_post_dev_interrupt //
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+tlep_intim:
+ lda r13, 0xffb(r31) // get upper GBUS address bits
+ sll r13, 28, r13 // shift up to top
+
+ lda r13, (0x300)(r13) // full CSRC address (tlep watch csrc offset)
+ ldq_p r13, 0(r13) // read CSRC
+
+ lda r13, 0x40(r31) // load Intim bit
+ Write_TLINTRSUMx(r13,r10,r14) // clear the Intim bit
+
+ lda r16, osfint_c_clk(r31) // passive release
+ br r31, pal_post_interrupt // Build the stack frame
+
+
+ ALIGN_BRANCH
+tlep_ipint:
+ lda r13, 0x20(r31) // load IP Int bit
+ Write_TLINTRSUMx(r13,r10,r14) // clear the IP Int bit
+
+ lda r16, osfint_c_ip(r31) // passive release
+ br r31, pal_post_interrupt // Build the stack frame
+
+
+ ALIGN_BRANCH
+tlep_uart0:
+ lda r13, 0xffa(r31) // get upper GBUS address bits
+ sll r13, 28, r13 // shift up to top
+
+ ldl_p r14, 0x80(r13) // zero pointer register
+ lda r14, 3(r31) // index to RR3
+
+ stl_p r14, 0x80(r13) // write pointer register
+ mb
+
+ mb
+ ldl_p r14, 0x80(r13) // read RR3
+
+ srl r14, 5, r10 // is it Channel A RX?
+ blbs r10, uart0_rx
+
+ srl r14, 4, r10 // is it Channel A TX?
+ blbs r10, uart0_tx
+
+ srl r14, 2, r10 // is it Channel B RX?
+ blbs r10, uart1_rx
+
+ srl r14, 1, r10 // is it Channel B TX?
+ blbs r10, uart1_tx
+
+ lda r8, 0(r31) // passive release
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+uart0_rx:
+ lda r8, 0x680(r31) // UART0 RX vector
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+uart0_tx:
+ lda r14, 0x28(r31) // Reset TX Int Pending code
+ mb
+ stl_p r14, 0x80(r13) // write Channel A WR0
+ mb
+
+ lda r8, 0x6c0(r31) // UART0 TX vector
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+uart1_rx:
+ lda r8, 0x690(r31) // UART1 RX vector
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+uart1_tx:
+ lda r14, 0x28(r31) // Reset TX Int Pending code
+ stl_p r14, 0(r13) // write Channel B WR0
+
+ lda r8, 0x6d0(r31) // UART1 TX vector
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+clear_duart0_int:
+ lda r13, 1(r31) // load duart0 bit
+ Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
+
+ beq r8, 1f
+ or r8, r31, r13 // move vector to r13
+ br r31, pal_post_dev_interrupt // Build the stack frame
+1: nop
+ nop
+ hw_rei
+// lda r16, osfint_c_passrel(r31) // passive release
+// br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+tlep_ecc:
+ mfpr r14, pt_whami // get our node id
+ extbl r14, 1, r14 // shift to bit 0
+
+ srl r14, 1, r14 // shift off cpu number
+ Get_TLSB_Node_Address(r14,r10) // compute our nodespace address
+
+ ldl_p r13, 0x40(r10) // read our TLBER WAS tlsb_tlber_offset
+ srl r13, 17, r13 // shift down the CWDE/CRDE bits
+
+ and r13, 3, r13 // mask the CWDE/CRDE bits
+ beq r13, 1f
+
+ ornot r31, r31, r12 // set flag
+ lda r9, mchk_c_sys_ecc(r31) // System Correctable error MCHK code
+ br r31, sys_merge_sys_corr // jump to CRD logout frame code
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+
+#endif // if TSUNAMI || BIG_TSUNAMI elif TLASER
+
+ ALIGN_BRANCH
+pal_post_dev_interrupt:
+ or r13, r31, r17 // move vector to a1
+ or r31, osfint_c_dev, r16 // a0 signals IO device interrupt
+
+pal_post_interrupt:
+ mfpr r12, pt_entint
+
+ mtpr r12, exc_addr
+
+ nop
+ nop
+
+ hw_rei_spe
+
+
+//
+// sys_passive_release
+// Just pretend the interrupt never occurred.
+//
+
+EXPORT(sys_passive_release)
+ mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps
+ nop
+
+ mfpr r31, pt0 // Pad write to dtb_cm
+ hw_rei
+
+//
+// sys_int_powerfail
+// A powerfail interrupt has been detected. The stack has been pushed.
+// IPL and PS are updated as well.
+//
+// I'm not sure what to do here, I'm treating it as an IO device interrupt
+//
+//
+
+ ALIGN_BLOCK
+sys_int_powerfail:
+ lda r12, 0xffc4(r31) // get GBUS_MISCR address bits
+ sll r12, 24, r12 // shift to proper position
+ ldq_p r12, 0(r12) // read GBUS_MISCR
+ srl r12, 5, r12 // isolate bit <5>
+ blbc r12, 1f // if clear, no missed mchk
+
+ // Missed a CFAIL mchk
+ lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits
+ sll r13, 24, r13 // shift to proper position
+ lda r14, 0x40(r31) // get bit <6> mask
+ ldq_p r12, 0(r13) // read GBUS$SERNUM
+ or r12, r14, r14 // set bit <6>
+ stq_p r14, 0(r13) // clear GBUS$SERNUM<6>
+ mb
+ mb
+
+1: br r31, sys_int_mchk // do a machine check
+
+ lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector
+ mfpr r25, pt_entint
+
+ lda r16, osfint_c_dev(r31) // a0 to device code
+ mtpr r25, exc_addr
+
+ nop // pad exc_addr write
+ nop
+
+ hw_rei_spe
+
+//
+// sys_halt_interrupt
+// A halt interrupt has been detected. Pass control to the console.
+//
+//
+//
+ EXPORT(sys_halt_interrupt)
+
+ ldah r13, 0x1800(r31) // load Halt/^PHalt bits
+ Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits
+
+ mtpr r11, dtb_cm // Restore Mbox current mode
+ nop
+ nop
+ mtpr r0, pt0
+ lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt
+ br r31, sys_enter_console // enter the console
+
+
+
+//
+// sys_int_mchk_or_crd
+//
+// Current state:
+// Stack is pushed
+// ps, sp and gp are updated
+// r12
+// r13 - INTID (new EV5 IPL)
+// r14 - exc_addr
+// r25 - ISR
+// r16, r17, r18 - available
+//
+//
+ ALIGN_BLOCK
+sys_int_mchk_or_crd:
+ srl r25, isr_v_mck, r12
+ blbs r12, sys_int_mchk
+ //
+ // Not a Machine check interrupt, so must be an Internal CRD interrupt
+ //
+
+ mb //Clear out Cbox prior to reading IPRs
+ srl r25, isr_v_crd, r13 //Check for CRD
+ blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!!
+
+ lda r9, 1(r31)
+ sll r9, hwint_clr_v_crdc, r9 // get ack bit for crd
+ mtpr r9, ev5__hwint_clr // ack the crd interrupt
+
+ or r31, r31, r12 // clear flag
+ lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code
+
+sys_merge_sys_corr:
+ ldah r14, 0xfff0(r31)
+ mtpr r0, pt0 // save r0 for scratch
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+ mtpr r1, pt1 // save r0 for scratch
+
+ ldq_p r0, ei_addr(r14) // EI_ADDR IPR
+ ldq_p r10, fill_syn(r14) // FILL_SYN IPR
+ bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub
+
+ blbs r12, 1f // no scrubbing for IRQ0 case
+// XXX bugnion pvc_jsr crd_scrub_mem, bsr=1
+ bsr r13, sys_crd_scrub_mem // and go scrub
+
+ // ld/st pair in scrub routine will have finished due
+ // to ibox stall of stx_c. Don't need another mb.
+ ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
+ or r8, r31, r12 // Must only be executed once in this flow, and must
+ br r31, 2f // be after the scrub routine.
+
+1: ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
+ // For IRQ0 CRD case only - meaningless data.
+
+2: mfpr r13, pt_mces // Get MCES
+ srl r12, ei_stat_v_ei_es, r14 // Isolate EI_STAT:EI_ES
+ blbc r14, 6f // branch if 630
+ srl r13, mces_v_dsc, r14 // check if 620 reporting disabled
+ blbc r14, 5f // branch if enabled
+ or r13, r31, r14 // don't set SCE if disabled
+ br r31, 8f // continue
+5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit
+ br r31, 8f
+
+6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled
+ blbc r14, 7f // branch if enabled
+ or r13, r31, r14 // don't set PCE if disabled
+ br r31, 8f // continue
+7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit
+
+ // Setup SCB if dpc is not set
+8: mtpr r14, pt_mces // Store updated MCES
+ srl r13, mces_v_sce, r1 // Get SCE
+ srl r13, mces_v_pce, r14 // Get PCE
+ or r1, r14, r1 // SCE OR PCE, since they share
+ // the CRD logout frame
+ // Get base of the logout area.
+ GET_IMPURE(r14) // addr of per-cpu impure area
+ GET_ADDR(r14,(pal_logout_area+mchk_crd_base),r14)
+
+ blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame
+
+ // Set the 2nd error flag in the logout area:
+
+ lda r1, 3(r31) // Set retry and 2nd error flags
+ sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword
+ stl_p r1, mchk_crd_flag+4(r14) // store flag longword
+ br sys_crd_ack
+
+sys_crd_write_logout_frame:
+ // should only be here if neither the pce or sce bits are set
+
+ //
+ // Write the mchk code to the logout area
+ //
+ stq_p r9, mchk_crd_mchk_code(r14)
+
+
+ //
+ // Write the first 2 quadwords of the logout area:
+ //
+ lda r1, 1(r31) // Set retry flag
+ sll r1, 63, r9 // Move retry flag to bit 63
+ lda r1, mchk_crd_size(r9) // Combine retry flag and frame size
+ stq_p r1, mchk_crd_flag(r14) // store flag/frame size
+
+ //
+ // Write error IPRs already fetched to the logout area
+ //
+ stq_p r0, mchk_crd_ei_addr(r14)
+ stq_p r10, mchk_crd_fill_syn(r14)
+ stq_p r8, mchk_crd_ei_stat(r14)
+ stq_p r25, mchk_crd_isr(r14)
+ //
+ // Log system specific info here
+ //
+crd_storeTLEP_:
+ lda r1, 0xffc4(r31) // Get GBUS$MISCR address
+ sll r1, 24, r1
+ ldq_p r1, 0(r1) // Read GBUS$MISCR
+ sll r1, 16, r1 // shift up to proper field
+ mfpr r10, pt_whami // get our node id
+ extbl r10, 1, r10 // shift to bit 0
+ or r1, r10, r1 // merge MISCR and WHAMI
+ stl_p r1, mchk_crd_whami(r14) // write to crd logout area
+ srl r10, 1, r10 // shift off cpu number
+
+ Get_TLSB_Node_Address(r10,r0) // compute our nodespace address
+
+ OSFcrd_TLEPstore_tlsb(tldev)
+ OSFcrd_TLEPstore_tlsb_clr(tlber)
+ OSFcrd_TLEPstore_tlsb_clr(tlesr0)
+ OSFcrd_TLEPstore_tlsb_clr(tlesr1)
+ OSFcrd_TLEPstore_tlsb_clr(tlesr2)
+ OSFcrd_TLEPstore_tlsb_clr(tlesr3)
+
+sys_crd_ack:
+ mfpr r0, pt0 // restore r0
+ mfpr r1, pt1 // restore r1
+
+ srl r12, ei_stat_v_ei_es, r12
+ blbc r12, 5f
+ srl r13, mces_v_dsc, r10 // logging enabled?
+ br r31, 6f
+5: srl r13, mces_v_dpc, r10 // logging enabled?
+6: blbc r10, sys_crd_post_interrupt // logging enabled -- report it
+
+ // logging not enabled
+ // Get base of the logout area.
+ GET_IMPURE(r13) // addr of per-cpu impure area
+ GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13)
+ ldl_p r10, mchk_crd_rsvd(r13) // bump counter
+ addl r10, 1, r10
+ stl_p r10, mchk_crd_rsvd(r13)
+ mb
+ br r31, sys_crd_dismiss_interrupt // just return
+
+ //
+ // The stack is pushed. Load up a0,a1,a2 and vector via entInt
+ //
+ //
+
+ ALIGN_BRANCH
+sys_crd_post_interrupt:
+ lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
+ lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector
+
+ blbc r12, 1f
+ lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector
+
+1: subq r31, 1, r18 // get a -1
+ mfpr r25, pt_entInt
+
+ srl r18, 42, r18 // shift off low bits of kseg addr
+ mtpr r25, exc_addr // load interrupt vector
+
+ sll r18, 42, r18 // shift back into position
+ or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
+
+ hw_rei_spe // done
+
+
+ //
+ // The stack is pushed. Need to back out of it all.
+ //
+
+sys_crd_dismiss_interrupt:
+ br r31, Call_Pal_Rti
+
+
+// sys_crd_scrub_mem
+//
+// r0 = addr of cache block
+//
+ ALIGN_BLOCK // align for branch target
+sys_crd_scrub_mem:
+ // now find error in memory, and attempt to scrub that cache block
+ // This routine just scrubs the failing octaword
+ // Only need to "touch" one quadword per octaword to accomplish the scrub
+ srl r0, 39, r8 // get high bit of bad pa
+ blbs r8, 1f // don't attempt fixup on IO space addrs
+ nop // needed to align the ldq_pl to octaword boundary
+ nop // "
+
+ ldq_p r8, 0(r0) // attempt to read the bad memory
+ // location
+ // (Note bits 63:40,3:0 of ei_addr
+ // are set to 1, but as long as
+ // we are doing a phys ref, should
+ // be ok)
+ nop // Needed to keep the Ibox from swapping the ldq_p into E1
+
+ stq_p r8, 0(r0) // Store it back if it is still there.
+ // If store fails, location already
+ // scrubbed by someone else
+
+ nop // needed to align the ldq_p to octaword boundary
+
+ lda r8, 0x20(r31) // flip bit 5 to touch next hexaword
+ xor r8, r0, r0
+ nop // needed to align the ldq_p to octaword boundary
+ nop // "
+
+ ldq_p r8, 0(r0) // attempt to read the bad memory
+ // location
+ // (Note bits 63:40,3:0 of ei_addr
+ // are set to 1, but as long as
+ // we are doing a phys ref, should
+ // be ok)
+ nop // Needed to keep the Ibox from swapping the ldq_p into E1
+
+ stq_p r8, 0(r0) // Store it back if it is still there.
+ // If store fails, location already
+ // scrubbed by someone else
+
+ lda r8, 0x20(r31) // restore r0 to original address
+ xor r8, r0, r0
+
+ //at this point, ei_stat could be locked due to a new corr error on the ld,
+ //so read ei_stat to unlock AFTER this routine.
+
+// XXX bugnion pvc$jsr crd_scrub_mem, bsr=1, dest=1
+1: ret r31, (r13) // and back we go
+
+
+//
+// sys_int_mchk - MCHK Interrupt code
+//
+// Machine check interrupt from the system. Setup and join the
+// regular machine check flow.
+// On exit:
+// pt0 - saved r0
+// pt1 - saved r1
+// pt4 - saved r4
+// pt5 - saved r5
+// pt6 - saved r6
+// pt10 - saved exc_addr
+// pt_misc<47:32> - mchk code
+// pt_misc<31:16> - scb vector
+// r14 - base of Cbox IPRs in IO space
+// MCES<mchk> is set
+//
+ ALIGN_BLOCK
+sys_int_mchk:
+ lda r14, mchk_c_sys_hrd_error(r31)
+ mfpr r12, exc_addr
+
+ addq r14, 1, r14 // Flag as interrupt
+ nop
+
+ sll r14, 32, r14 // Move mchk code to position
+ mtpr r12, pt10 // Stash exc_addr
+
+ mfpr r12, pt_misc // Get MCES and scratch
+ mtpr r0, pt0 // Stash for scratch
+
+ zap r12, 0x3c, r12 // Clear scratch
+ blbs r12, sys_double_machine_check // MCHK halt if double machine check
+
+ or r12, r14, r12 // Combine mchk code
+ lda r14, scb_v_sysmchk(r31) // Get SCB vector
+
+ sll r14, 16, r14 // Move SCBv to position
+ or r12, r14, r14 // Combine SCBv
+
+ bis r14, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
+ mtpr r14, pt_misc // Save mchk code!scbv!whami!mces
+
+ ldah r14, 0xfff0(r31)
+ mtpr r1, pt1 // Stash for scratch
+
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+ mtpr r4, pt4
+
+ mtpr r5, pt5
+
+ mtpr r6, pt6
+ br r31, sys_mchk_collect_iprs // Join common machine check flow
+
+
+//
+// sys_int_perf_cnt - Performance counter interrupt code
+//
+// A performance counter interrupt has been detected. The stack
+// has been pushed. IPL and PS are updated as well.
+//
+// on exit to interrupt entry point ENTINT::
+// a0 = osfint$c_perf
+// a1 = scb$v_perfmon (650)
+// a2 = 0 if performance counter 0 fired
+// a2 = 1 if performance counter 1 fired
+// a2 = 2 if performance counter 2 fired
+// (if more than one counter overflowed, an interrupt will be
+// generated for each counter that overflows)
+//
+//
+//
+ ALIGN_BLOCK
+sys_int_perf_cnt: // Performance counter interrupt
+ lda r17, scb_v_perfmon(r31) // a1 to interrupt vector
+ mfpr r25, pt_entint
+
+ lda r16, osfint_c_perf(r31) // a0 to perf counter code
+ mtpr r25, exc_addr
+
+ //isolate which perf ctr fired, load code in a2, and ack
+ mfpr r25, isr
+ or r31, r31, r18 // assume interrupt was pc0
+
+ srl r25, isr_v_pc1, r25 // isolate
+ cmovlbs r25, 1, r18 // if pc1 set, load 1 into r14
+
+ srl r25, 1, r25 // get pc2
+ cmovlbs r25, 2, r18 // if pc2 set, load 2 into r14
+
+ lda r25, 1(r31) // get a one
+ sll r25, r18, r25
+
+ sll r25, hwint_clr_v_pc0c, r25 // ack only the perf counter that generated the interrupt
+ mtpr r25, hwint_clr
+
+ hw_rei_spe
+
+
+
+//
+// sys_reset - System specific RESET code
+// On entry:
+// r1 = pal_base +8
+//
+// Entry state on trap:
+// r0 = whami
+// r2 = base of scratch area
+// r3 = halt code
+// and the following 3 if init_cbox is enabled:
+// r5 = sc_ctl
+// r6 = bc_ctl
+// r7 = bc_cnfg
+//
+// Entry state on switch:
+// r17 - new PC
+// r18 - new PCBB
+// r19 - new VPTB
+//
+
+ ALIGN_BLOCK
+ .globl sys_reset
+sys_reset:
+// mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load
+ mtpr r31, itb_ia // clear the ITB
+ mtpr r31, dtb_ia // clear the DTB
+
+ lda r1, -8(r1) // point to start of code
+ mtpr r1, pal_base // initialize PAL_BASE
+
+ // Interrupts
+ mtpr r31, astrr // stop ASTs
+ mtpr r31, aster // stop ASTs
+ mtpr r31, sirr // clear software interrupts
+
+ mtpr r0, pt1 // r0 is whami (unless we entered via swp)
+
+ ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero)
+
+ bis r31, 1, r0
+ sll r0, icsr_v_crde, r0 // A 1 in iscr<corr_read_enable>
+ or r0, r1, r1 // Set the bit
+
+ mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable,
+ // super page enabled, correct read per assembly option
+
+ // Mbox/Dcache init
+ lda r1,BIT(mcsr_v_sp1)(zero)
+
+ mtpr r1, mcsr // MCSR - Super page enabled
+ lda r1, BIT(dc_mode_v_dc_ena)(r31)
+ ALIGN_BRANCH
+// mtpr r1, dc_mode // turn Dcache on
+ nop
+
+ mfpr r31, pt0 // No Mbox instr in 1,2,3,4
+ mfpr r31, pt0
+ mfpr r31, pt0
+ mfpr r31, pt0
+ mtpr r31, dc_flush // flush Dcache
+
+ // build PS (IPL=7,CM=K,VMM=0,SW=0)
+ lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7
+ lda r1, 0x1F(r31)
+ mtpr r1, ipl // set internal <ipl>=1F
+ mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy
+ mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy
+
+ // Create the PALtemp pt_intmask
+ // MAP:
+ // OSF IPL EV5 internal IPL(hex) note
+ // 0 0
+ // 1 1
+ // 2 2
+ // 3 14 device
+ // 4 15 device
+ // 5 16 device
+ // 6 1E device,performance counter, powerfail
+ // 7 1F
+ //
+
+ ldah r1, 0x1f1E(r31) // Create upper lw of int_mask
+ lda r1, 0x1615(r1)
+
+ sll r1, 32, r1
+ ldah r1, 0x1402(r1) // Create lower lw of int_mask
+
+ lda r1, 0x0100(r1)
+ mtpr r1, pt_intmask // Stash in PALtemp
+
+ // Unlock a bunch of chip internal IPRs
+ mtpr r31, exc_sum // clear out exeception summary and exc_mask
+ mfpr r31, va // unlock va, mmstat
+ lda r8,(BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(zero)
+
+ mtpr r8, icperr_stat // Clear Icache parity error & timeout status
+ lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
+
+ mtpr r8, dcperr_stat // Clear Dcache parity error status
+
+ rc r0 // clear intr_flag
+ mtpr r31, pt_trap
+
+ mfpr r0, pt_misc
+ srl r0, pt_misc_v_switch, r1
+ blbs r1, sys_reset_switch // see if we got here from swppal
+
+ // Rest of the "real" reset flow
+ // ASN
+ mtpr r31, dtb_asn
+ mtpr r31, itb_asn
+
+ lda r1, 0x67(r31)
+ sll r1, hwint_clr_v_pc0c, r1
+ mtpr r1, hwint_clr // Clear hardware interrupt requests
+
+ lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error
+ mfpr r0, pt1 // get whami
+ insbl r0, 1, r0 // isolate whami in correct pt_misc position
+ or r0, r1, r1 // combine whami and mces
+ mtpr r1, pt_misc // store whami and mces, swap bit clear
+
+ zapnot r3, 1, r0 // isolate halt code
+ mtpr r0, pt0 // save entry type
+
+ // Cycle counter
+ or r31, 1, r9 // get a one
+ sll r9, 32, r9 // shift to <32>
+ mtpr r31, cc // clear Cycle Counter
+ mtpr r9, cc_ctl // clear and enable the Cycle Counter
+ mtpr r31, pt_scc // clear System Cycle Counter
+
+
+ // Misc PALtemps
+ mtpr r31, maf_mode // no mbox instructions for 3 cycles
+ or r31, 1, r1 // get bogus scbb value
+ mtpr r1, pt_scbb // load scbb
+ mtpr r31, pt_prbr // clear out prbr
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ // yes, this is ugly, but you figure out a better
+ // way to get the address of the kludge_initial_pcbb
+ // in r1 with an uncooperative assembler --ali
+ br r1, kludge_getpcb_addr
+ br r31, kludge_initial_pcbb
+kludge_getpcb_addr:
+ ldq_p r19, 0(r1)
+ sll r19, 44, r19
+ srl r19, 44, r19
+ mulq r19,4,r19
+ addq r19, r1, r1
+ addq r1,4,r1
+#elif defined(TLASER)
+ // or zero,kludge_initial_pcbb,r1
+ GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
+#endif
+ mtpr r1, pt_pcbb // load pcbb
+ lda r1, 2(r31) // get a two
+ sll r1, 32, r1 // gen up upper bits
+ mtpr r1, mvptbr
+ mtpr r1, ivptbr
+ mtpr r31, pt_ptbr
+ // Performance counters
+ mtpr r31, pmctr
+
+ // Clear pmctr_ctl in impure area
+
+
+ ldah r14, 0xfff0(r31)
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+ GET_IMPURE(r13)
+ stq_p r31, 0(r13) // Clear lock_flag
+
+ mfpr r0, pt0 // get entry type
+ br r31, sys_enter_console // enter the cosole
+
+
+ // swppal entry
+ // r0 - pt_misc
+ // r17 - new PC
+ // r18 - new PCBB
+ // r19 - new VPTB
+sys_reset_switch:
+ or r31, 1, r9
+ sll r9, pt_misc_v_switch, r9
+ bic r0, r9, r0 // clear switch bit
+ mtpr r0, pt_misc
+
+ rpcc r1 // get cyccounter
+
+ ldq_p r22, osfpcb_q_fen(r18) // get new fen/pme
+ ldl_p r23, osfpcb_l_cc(r18) // get cycle counter
+ ldl_p r24, osfpcb_l_asn(r18) // get new asn
+
+
+ ldq_p r25, osfpcb_q_Mmptr(r18)// get new mmptr
+ sll r25, page_offset_size_bits, r25 // convert pfn to pa
+ mtpr r25, pt_ptbr // load the new mmptr
+ mtpr r18, pt_pcbb // set new pcbb
+
+ bic r17, 3, r17 // clean use pc
+ mtpr r17, exc_addr // set new pc
+ mtpr r19, mvptbr
+ mtpr r19, ivptbr
+
+ ldq_p r30, osfpcb_q_Usp(r18) // get new usp
+ mtpr r30, pt_usp // save usp
+
+ sll r24, dtb_asn_v_asn, r8
+ mtpr r8, dtb_asn
+ sll r24, itb_asn_v_asn, r24
+ mtpr r24, itb_asn
+
+ mfpr r25, icsr // get current icsr
+ lda r24, 1(r31)
+ sll r24, icsr_v_fpe, r24 // 1 in icsr<fpe> position
+ bic r25, r24, r25 // clean out old fpe
+ and r22, 1, r22 // isolate new fen bit
+ sll r22, icsr_v_fpe, r22
+ or r22, r25, r25 // or in new fpe
+ mtpr r25, icsr // update ibox ipr
+
+ subl r23, r1, r1 // gen new cc offset
+ insll r1, 4, r1 // << 32
+ mtpr r1, cc // set new offset
+
+ or r31, r31, r0 // set success
+ ldq_p r30, osfpcb_q_Ksp(r18) // get new ksp
+ mfpr r31, pt0 // stall
+ hw_rei_stall
+
+//
+//sys_machine_check - Machine check PAL
+// A machine_check trap has occurred. The Icache has been flushed.
+//
+//
+
+ ALIGN_BLOCK
+EXPORT(sys_machine_check)
+ // Need to fill up the refill buffer (32 instructions) and
+ // then flush the Icache again.
+ // Also, due to possible 2nd Cbox register file write for
+ // uncorrectable errors, no register file read or write for 7 cycles.
+
+ nop
+ mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites
+ // r0 later
+ nop
+ nop
+
+ nop
+ nop
+
+ nop
+ nop
+
+ nop
+ nop
+ // 10 instructions// 5 cycles
+
+ nop
+ nop
+
+ nop
+ nop
+
+ // Register file can now be written
+ lda r0, scb_v_procmchk(r31) // SCB vector
+ mfpr r13, pt_mces // Get MCES
+ sll r0, 16, r0 // Move SCBv to correct position
+ bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
+
+
+ zap r14, 0x3C, r14 // Clear mchk_code word and SCBv word
+ mtpr r14, pt_mces
+ // 20 instructions
+
+ nop
+ or r14, r0, r14 // Insert new SCB vector
+ lda r0, mchk_c_proc_hrd_error(r31) // MCHK code
+ mfpr r12, exc_addr
+
+ sll r0, 32, r0 // Move MCHK code to correct position
+ mtpr r4, pt4
+ or r14, r0, r14 // Insert new MCHK code
+ mtpr r14, pt_misc // Store updated MCES, MCHK code, and SCBv
+
+ ldah r14, 0xfff0(r31)
+ mtpr r1, pt1 // Stash for scratch - 30 instructions
+
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+ mtpr r12, pt10 // Stash exc_addr
+
+
+
+ mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed.
+ blbs r13, sys_double_machine_check // MCHK halt if double machine check
+
+ mtpr r6, pt6
+ mtpr r5, pt5
+
+ // Look for the powerfail cases here....
+ mfpr r4, isr
+ srl r4, isr_v_pfl, r4
+ blbc r4, sys_mchk_collect_iprs // skip if no powerfail interrupt pending
+ lda r4, 0xffc4(r31) // get GBUS$MISCR address bits
+ sll r4, 24, r4 // shift to proper position
+ ldq_p r4, 0(r4) // read GBUS$MISCR
+ srl r4, 5, r4 // isolate bit <5>
+ blbc r4, sys_mchk_collect_iprs // skip if already cleared
+ // No missed CFAIL mchk
+ lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits
+ sll r5, 24, r5 // shift to proper position
+ lda r6, 0x40(r31) // get bit <6> mask
+ ldq_p r4, 0(r5) // read GBUS$SERNUM
+ or r4, r6, r6 // set bit <6>
+ stq_p r6, 0(r5) // clear GBUS$SERNUM<6>
+ mb
+ mb
+
+
+ //
+ // Start to collect the IPRs. Common entry point for mchk flows.
+ //
+ // Current state:
+ // pt0 - saved r0
+ // pt1 - saved r1
+ // pt4 - saved r4
+ // pt5 - saved r5
+ // pt6 - saved r6
+ // pt10 - saved exc_addr
+ // pt_misc<47:32> - mchk code
+ // pt_misc<31:16> - scb vector
+ // r14 - base of Cbox IPRs in IO space
+ // r0, r1, r4, r5, r6, r12, r13, r25 - available
+ // r8, r9, r10 - available as all loads are physical
+ // MCES<mchk> is set
+ //
+ //
+
+EXPORT(sys_mchk_collect_iprs)
+ mb // MB before reading Scache IPRs
+ mfpr r1, icperr_stat
+
+ mfpr r8, dcperr_stat
+ mtpr r31, dc_flush // Flush the Dcache
+
+ mfpr r31, pt0 // Pad Mbox instructions from dc_flush
+ mfpr r31, pt0
+ nop
+ nop
+
+ ldq_p r9, sc_addr(r14) // SC_ADDR IPR
+ bis r9, r31, r31 // Touch ld to make sure it completes before
+ // read of SC_STAT
+ ldq_p r10, sc_stat(r14) // SC_STAT, also unlocks SC_ADDR
+
+ ldq_p r12, ei_addr(r14) // EI_ADDR IPR
+ ldq_p r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR
+ ldq_p r0, fill_syn(r14) // FILL_SYN IPR
+ bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT
+ bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT
+ ldq_p r25, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
+ ldq_p r31, ei_stat(r14) // Read again to insure it is unlocked
+
+
+
+
+ //
+ // Look for nonretryable cases
+ // In this segment:
+ // r5<0> = 1 means retryable
+ // r4, r6, and r14 are available for scratch
+ //
+ //
+
+
+ bis r31, r31, r5 // Clear local retryable flag
+ srl r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits to low bits
+
+ lda r4, 1(r31)
+ sll r4, icperr_stat_v_tmr, r4
+ and r1, r4, r4 // Timeout reset
+ bne r4, sys_cpu_mchk_not_retryable
+
+ and r8, BIT(dcperr_stat_v_lock), r4 // DCache parity error locked
+ bne r4, sys_cpu_mchk_not_retryable
+
+ lda r4, 1(r31)
+ sll r4, sc_stat_v_sc_scnd_err, r4
+ and r10, r4, r4 // 2nd Scache error occurred
+ bne r4, sys_cpu_mchk_not_retryable
+
+
+ bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control
+ // Parity Error, Interface Parity Error, 2nd Error
+
+ and r25, r4, r4
+ bne r4, sys_cpu_mchk_not_retryable
+
+// bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4
+ bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
+ and r25, r4, r4 // Isolate the Uncorrectable Error Bit
+// bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6
+ bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit
+ cmovne r6, 0, r4 // r4 = 0 if IRD or if No Uncorrectable Error
+ bne r4, sys_cpu_mchk_not_retryable
+
+ lda r4, 7(r31)
+ and r10, r4, r4 // Isolate the Scache Tag Parity Error bits
+ bne r4, sys_cpu_mchk_not_retryable // All Scache Tag PEs are not retryable
+
+
+ lda r4, 0x7f8(r31)
+ and r10, r4, r4 // Isolate the Scache Data Parity Error bits
+ srl r10, sc_stat_v_cbox_cmd, r6
+ and r6, 0x1f, r6 // Isolate Scache Command field
+ subq r6, 1, r6 // Scache Iread command = 1
+ cmoveq r6, 0, r4 // r4 = 0 if IRD or if No Parity Error
+ bne r4, sys_cpu_mchk_not_retryable
+
+ // Look for the system unretryable cases here....
+
+ mfpr r4, isr // mchk_interrupt pin asserted
+ srl r4, isr_v_mck, r4
+ blbs r4, sys_cpu_mchk_not_retryable
+
+
+
+ //
+ // Look for retryable cases
+ // In this segment:
+ // r5<0> = 1 means retryable
+ // r6 - holds the mchk code
+ // r4 and r14 are available for scratch
+ //
+ //
+
+
+ // Within the chip, the retryable cases are Istream errors
+ lda r4, 3(r31)
+ sll r4, icperr_stat_v_dpe, r4
+ and r1, r4, r4
+ cmovne r4, 1, r5 // Retryable if just Icache parity error
+
+
+ lda r4, 0x7f8(r31)
+ and r10, r4, r4 // Isolate the Scache Data Parity Error bits
+ srl r10, sc_stat_v_cbox_cmd, r14
+ and r14, 0x1f, r14 // Isolate Scache Command field
+ subq r14, 1, r14 // Scache Iread command = 1
+ cmovne r4, 1, r4 // r4 = 1 if Scache data parity error bit set
+ cmovne r14, 0, r4 // r4 = 1 if Scache PE and Iread
+ bis r4, r5, r5 // Accumulate
+
+
+ bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
+ and r25, r4, r4 // Isolate the Uncorrectable Error Bit
+ and r25, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r14 // Isolate the Iread bit
+ cmovne r4, 1, r4 // r4 = 1 if uncorr error
+ cmoveq r14, 0, r4 // r4 = 1 if uncorr and Iread
+ bis r4, r5, r5 // Accumulate
+
+ mfpr r6, pt_misc
+ extwl r6, 4, r6 // Fetch mchk code
+ bic r6, 1, r6 // Clear flag from interrupt flow
+ cmovne r5, mchk_c_retryable_ird, r6 // Set mchk code
+
+
+ //
+ // Write the logout frame
+ //
+ // Current state:
+ // r0 - fill_syn
+ // r1 - icperr_stat
+ // r4 - available
+ // r5<0> - retry flag
+ // r6 - mchk code
+ // r8 - dcperr_stat
+ // r9 - sc_addr
+ // r10 - sc_stat
+ // r12 - ei_addr
+ // r13 - bc_tag_addr
+ // r14 - available
+ // r25 - ei_stat (shifted)
+ // pt0 - saved r0
+ // pt1 - saved r1
+ // pt4 - saved r4
+ // pt5 - saved r5
+ // pt6 - saved r6
+ // pt10 - saved exc_addr
+ //
+ //
+
+sys_mchk_write_logout_frame:
+ // Get base of the logout area.
+ GET_IMPURE(r14) // addr of per-cpu impure area
+ GET_ADDR(r14,pal_logout_area+mchk_mchk_base,r14)
+
+ // Write the first 2 quadwords of the logout area:
+
+ sll r5, 63, r5 // Move retry flag to bit 63
+ lda r4, mchk_size(r5) // Combine retry flag and frame size
+ stq_p r4, mchk_flag(r14) // store flag/frame size
+ lda r4, mchk_sys_base(r31) // sys offset
+ sll r4, 32, r4
+ lda r4, mchk_cpu_base(r4) // cpu offset
+ stq_p r4, mchk_offsets(r14) // store sys offset/cpu offset into logout frame
+
+ //
+ // Write the mchk code to the logout area
+ // Write error IPRs already fetched to the logout area
+ // Restore some GPRs from PALtemps
+ //
+
+ mfpr r5, pt5
+ stq_p r6, mchk_mchk_code(r14)
+ mfpr r4, pt4
+ stq_p r1, mchk_ic_perr_stat(r14)
+ mfpr r6, pt6
+ stq_p r8, mchk_dc_perr_stat(r14)
+ mfpr r1, pt1
+ stq_p r9, mchk_sc_addr(r14)
+ stq_p r10, mchk_sc_stat(r14)
+ stq_p r12, mchk_ei_addr(r14)
+ stq_p r13, mchk_bc_tag_addr(r14)
+ stq_p r0, mchk_fill_syn(r14)
+ mfpr r0, pt0
+ sll r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits back to expected position
+ // retrieve lower 28 bits again from ei_stat and restore before storing to logout frame
+ ldah r13, 0xfff0(r31)
+ zapnot r13, 0x1f, r13
+ ldq_p r13, ei_stat(r13)
+ sll r13, 64-ei_stat_v_bc_tperr, r13
+ srl r13, 64-ei_stat_v_bc_tperr, r13
+ or r25, r13, r25
+ stq_p r25, mchk_ei_stat(r14)
+
+
+
+
+ //
+ // complete the CPU-specific part of the logout frame
+ //
+
+ ldah r13, 0xfff0(r31)
+ zap r13, 0xE0, r13 // Get Cbox IPR base
+ ldq_p r13, ld_lock(r13) // Get ld_lock IPR
+ stq_p r13, mchk_ld_lock(r14) // and stash it in the frame
+
+ // Unlock IPRs
+ lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
+ mtpr r8, dcperr_stat // Clear Dcache parity error status
+
+ lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31)
+ mtpr r8, icperr_stat // Clear Icache parity error & timeout status
+
+1: ldq_p r8, mchk_ic_perr_stat(r14) // get ICPERR_STAT value
+ GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value
+ and r0, r8, r0 // compare
+ beq r0, 2f // check next case if nothing set
+ lda r0, mchk_c_retryable_ird(r31) // set new MCHK code
+ br r31, do_670 // setup new vector
+
+2: ldq_p r8, mchk_dc_perr_stat(r14) // get DCPERR_STAT value
+ GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value
+ and r0, r8, r0 // compare
+ beq r0, 3f // check next case if nothing set
+ lda r0, mchk_c_dcperr(r31) // set new MCHK code
+ br r31, do_670 // setup new vector
+
+3: ldq_p r8, mchk_sc_stat(r14) // get SC_STAT value
+ GET_ADDR(r0,0x107ff,r31) // get SC_STAT value
+ and r0, r8, r0 // compare
+ beq r0, 4f // check next case if nothing set
+ lda r0, mchk_c_scperr(r31) // set new MCHK code
+ br r31, do_670 // setup new vector
+
+4: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value
+ GET_ADDR(r0,0x30000000,r31) // get EI_STAT value
+ and r0, r8, r0 // compare
+ beq r0, 5f // check next case if nothing set
+ lda r0, mchk_c_bcperr(r31) // set new MCHK code
+ br r31, do_670 // setup new vector
+
+5: ldl_p r8, mchk_tlber(r14) // get TLBER value
+ GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value
+ sll r0, 16, r0 // shift into proper position
+ GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value
+ or r0, r1, r0 // merge mask values
+ and r0, r8, r0 // compare
+ beq r0, 6f // check next case if nothing set
+ GET_ADDR(r0, 0xfff0, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+6: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value
+ GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value
+ and r0, r8, r0 // compare
+ beq r0, 7f // check next case if nothing set
+ GET_ADDR(r0, 0xfffa, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+7: ldl_p r8, mchk_tlepderr(r14) // get TLEPDERR value
+ GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value
+ and r0, r8, r0 // compare
+ beq r0, 8f // check next case if nothing set
+ GET_ADDR(r0, 0xfffb, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+8: ldl_p r8, mchk_tlepmerr(r14) // get TLEPMERR value
+ GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value
+ and r0, r8, r0 // compare
+ beq r0, 9f // check next case if nothing set
+ GET_ADDR(r0, 0xfffc, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+9: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value
+ GET_ADDR(r0,0xb,r31) // get EI_STAT mask value
+ sll r0, 32, r0 // shift to upper lw
+ and r0, r8, r0 // compare
+ beq r0, 1f // check next case if nothing set
+ GET_ADDR(r0,0xfffd,r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+1: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value
+ GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value
+ and r0, r8, r0 // compare
+ beq r0, cont_logout_frame // check next case if nothing set
+ GET_ADDR(r0, 0xfffe, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+do_670: lda r8, scb_v_procmchk(r31) // SCB vector
+ br r31, do_6x0_cont
+do_660: lda r8, scb_v_sysmchk(r31) // SCB vector
+do_6x0_cont:
+ sll r8, 16, r8 // shift to proper position
+ mfpr r1, pt_misc // fetch current pt_misc
+ GET_ADDR(r4,0xffff, r31) // mask for vector field
+ sll r4, 16, r4 // shift to proper position
+ bic r1, r4, r1 // clear out old vector field
+ or r1, r8, r1 // merge in new vector
+ mtpr r1, pt_misc // save new vector field
+ stl_p r0, mchk_mchk_code(r14) // save new mchk code
+
+cont_logout_frame:
+ // Restore some GPRs from PALtemps
+ mfpr r0, pt0
+ mfpr r1, pt1
+ mfpr r4, pt4
+
+ mfpr r12, pt10 // fetch original PC
+ blbs r12, sys_machine_check_while_in_pal // MCHK halt if machine check in pal
+
+//XXXbugnion pvc_jsr armc, bsr=1
+ bsr r12, sys_arith_and_mchk // go check for and deal with arith trap
+
+ mtpr r31, exc_sum // Clear Exception Summary
+
+ mfpr r25, pt10 // write exc_addr after arith_and_mchk to pickup new pc
+ stq_p r25, mchk_exc_addr(r14)
+
+ //
+ // Set up the km trap
+ //
+
+
+sys_post_mchk_trap:
+ mfpr r25, pt_misc // Check for flag from mchk interrupt
+ extwl r25, 4, r25
+ blbs r25, sys_mchk_stack_done // Stack from already pushed if from interrupt flow
+
+ bis r14, r31, r12 // stash pointer to logout area
+ mfpr r14, pt10 // get exc_addr
+
+ sll r11, 63-3, r25 // get mode to msb
+ bge r25, 3f
+
+ mtpr r31, dtb_cm
+ mtpr r31, ev5__ps
+
+ mtpr r30, pt_usp // save user stack
+ mfpr r30, pt_ksp
+
+3:
+ lda sp, 0-osfsf_c_size(sp) // allocate stack space
+ nop
+
+ stq r18, osfsf_a2(sp) // a2
+ stq r11, osfsf_ps(sp) // save ps
+
+ stq r14, osfsf_pc(sp) // save pc
+ mfpr r25, pt_entint // get the VA of the interrupt routine
+
+ stq r16, osfsf_a0(sp) // a0
+ lda r16, osfint_c_mchk(r31) // flag as mchk in a0
+
+ stq r17, osfsf_a1(sp) // a1
+ mfpr r17, pt_misc // get vector
+
+ stq r29, osfsf_gp(sp) // old gp
+ mtpr r25, exc_addr //
+
+ or r31, 7, r11 // get new ps (km, high ipl)
+ subq r31, 1, r18 // get a -1
+
+ extwl r17, 2, r17 // a1 <- interrupt vector
+ bis r31, ipl_machine_check, r25
+
+ mtpr r25, ipl // Set internal ipl
+ srl r18, 42, r18 // shift off low bits of kseg addr
+
+ sll r18, 42, r18 // shift back into position
+ mfpr r29, pt_kgp // get the kern r29
+
+ or r12, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
+ hw_rei_spe // out to interrupt dispatch routine
+
+
+ //
+ // The stack is pushed. Load up a0,a1,a2 and vector via entInt
+ //
+ //
+ ALIGN_BRANCH
+sys_mchk_stack_done:
+ lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
+ lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector
+
+ subq r31, 1, r18 // get a -1
+ mfpr r25, pt_entInt
+
+ srl r18, 42, r18 // shift off low bits of kseg addr
+ mtpr r25, exc_addr // load interrupt vector
+
+ sll r18, 42, r18 // shift back into position
+ or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
+
+ hw_rei_spe // done
+
+
+ ALIGN_BRANCH
+sys_cpu_mchk_not_retryable:
+ mfpr r6, pt_misc
+ extwl r6, 4, r6 // Fetch mchk code
+ br r31, sys_mchk_write_logout_frame //
+
+
+
+//
+//sys_double_machine_check - a machine check was started, but MCES<MCHK> was
+// already set. We will now double machine check halt.
+//
+// pt0 - old R0
+//
+//
+
+EXPORT(sys_double_machine_check)
+ lda r0, hlt_c_dbl_mchk(r31)
+ br r31, sys_enter_console
+
+//
+// sys_machine_check_while_in_pal - a machine check was started,
+// exc_addr points to a PAL PC. We will now machine check halt.
+//
+// pt0 - old R0
+//
+//
+sys_machine_check_while_in_pal:
+ stq_p r12, mchk_exc_addr(r14) // exc_addr has not yet been written
+ lda r0, hlt_c_mchk_from_pal(r31)
+ br r31, sys_enter_console
+
+
+//ARITH and MCHK
+// Check for arithmetic errors and build trap frame,
+// but don't post the trap.
+// on entry:
+// pt10 - exc_addr
+// r12 - return address
+// r14 - logout frame pointer
+// r13 - available
+// r8,r9,r10 - available except across stq's
+// pt0,1,6 - available
+//
+// on exit:
+// pt10 - new exc_addr
+// r17 = exc_mask
+// r16 = exc_sum
+// r14 - logout frame pointer
+//
+ ALIGN_BRANCH
+sys_arith_and_mchk:
+ mfpr r13, ev5__exc_sum
+ srl r13, exc_sum_v_swc, r13
+ bne r13, handle_arith_and_mchk
+
+// XXX bugnion pvc$jsr armc, bsr=1, dest=1
+ ret r31, (r12) // return if no outstanding arithmetic error
+
+handle_arith_and_mchk:
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel
+ // no virt ref for next 2 cycles
+ mtpr r14, pt0
+
+ mtpr r1, pt1 // get a scratch reg
+ and r11, osfps_m_mode, r1 // get mode bit
+
+ bis r11, r31, r25 // save ps
+ beq r1, 1f // if zero we are in kern now
+
+ bis r31, r31, r25 // set the new ps
+ mtpr r30, pt_usp // save user stack
+
+ mfpr r30, pt_ksp // get kern stack
+1:
+ mfpr r14, exc_addr // get pc into r14 in case stack writes fault
+
+ lda sp, 0-osfsf_c_size(sp) // allocate stack space
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ mfpr r1, pt_entArith
+ stq r14, osfsf_pc(sp) // save pc
+
+ stq r17, osfsf_a1(sp)
+ mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
+
+ stq r29, osfsf_gp(sp)
+ stq r16, osfsf_a0(sp) // save regs
+
+ bis r13, r31, r16 // move exc_sum to r16
+ stq r18, osfsf_a2(sp)
+
+ stq r11, osfsf_ps(sp) // save ps
+ mfpr r29, pt_kgp // get the kern gp
+
+ mfpr r14, pt0 // restore logout frame pointer from pt0
+ bis r25, r31, r11 // set new ps
+
+ mtpr r1, pt10 // Set new PC
+ mfpr r1, pt1
+
+// XXX bugnion pvc$jsr armc, bsr=1, dest=1
+ ret r31, (r12) // return if no outstanding arithmetic error
+
+
+
+// sys_enter_console - Common PALcode for ENTERING console
+//
+// Entry:
+// Entered when PAL wants to enter the console.
+// usually as the result of a HALT instruction or button,
+// or catastrophic error.
+//
+// Regs on entry...
+//
+// R0 = halt code
+// pt0 <- r0
+//
+// Function:
+//
+// Save all readable machine state, and "call" the console
+//
+// Returns:
+//
+//
+// Notes:
+//
+// In these routines, once the save state routine has been executed,
+// the remainder of the registers become scratchable, as the only
+// "valid" copy of them is the "saved" copy.
+//
+// Any registers or PTs that are modified before calling the save
+// routine will have there data lost. The code below will save all
+// state, but will loose pt 0,4,5.
+//
+//
+
+ ALIGN_BLOCK
+EXPORT(sys_enter_console)
+ mtpr r1, pt4
+ mtpr r3, pt5
+ subq r31, 1, r1
+ sll r1, 42, r1
+ ldah r1, 1(r1)
+
+ /* taken from scrmax, seems like the obvious thing to do */
+ mtpr r1, exc_addr
+ mfpr r1, pt4
+ mfpr r3, pt5
+ STALL
+ STALL
+ hw_rei_stall
+
+
+//
+// sys_exit_console - Common PALcode for ENTERING console
+//
+// Entry:
+// Entered when console wants to reenter PAL.
+// usually as the result of a CONTINUE.
+//
+//
+// Regs' on entry...
+//
+//
+// Function:
+//
+// Restore all readable machine state, and return to user code.
+//
+//
+//
+//
+ ALIGN_BLOCK
+sys_exit_console:
+
+ GET_IMPURE(r1)
+
+ // clear lock and intr_flags prior to leaving console
+ rc r31 // clear intr_flag
+ // lock flag cleared by restore_state
+ // TB's have been flushed
+
+ ldq_p r3, (cns_gpr+(8*3))(r1) // restore r3
+ ldq_p r1, (cns_gpr+8)(r1) // restore r1
+ hw_rei_stall // back to user
+
+
+// kludge_initial_pcbb - PCB for Boot use only
+
+ ALIGN_128
+.globl kludge_initial_pcbb
+kludge_initial_pcbb: // PCB is 128 bytes long
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+
+// SET_SC_BC_CTL subroutine
+//
+// Subroutine to set the SC_CTL, BC_CONFIG, and BC_CTL registers and
+// flush the Scache
+// There must be no outstanding memory references -- istream or
+// dstream -- when these registers are written. EV5 prefetcher is
+// difficult to turn off. So, this routine needs to be exactly 32
+// instructions long// the final jmp must be in the last octaword of a
+// page (prefetcher doesn't go across page)
+//
+//
+// Register expecations:
+// r0 base address of CBOX iprs
+// r5 value to set sc_ctl to (flush bit is added in)
+// r6 value to set bc_ctl to
+// r7 value to set bc_config to
+// r10 return address
+// r19 old sc_ctl value
+// r20 old value of bc_ctl
+// r21 old value of bc_config
+// r23 flush scache flag
+// Register usage:
+// r17 sc_ctl with flush bit cleared
+// r22 loop address
+//
+//
+set_sc_bc_ctl:
+ ret r31, (r10) // return to where we came from
+++ /dev/null
-/*
- * Copyright (c) 2003, 2004, 2005
- * The Regents of The University of Michigan
- * All Rights Reserved
- *
- * This code is part of the M5 simulator, developed by Nathan Binkert,
- * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
- * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
- * Schultz.
- *
- * Permission is granted to use, copy, create derivative works and
- * redistribute this software and such derivative works for any
- * purpose, so long as the copyright notice above, this grant of
- * permission, and the disclaimer below appear in all copies made; and
- * so long as the name of The University of Michigan is not used in
- * any advertising or publicity pertaining to the use or distribution
- * of this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
- * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
- * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
- * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
- * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
- * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
- * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
- * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGES.
- */
-/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-// build_fixed_image: not sure what means
-// real_mm to be replaced during rewrite
-// remove_save_state remove_restore_state can be remooved to save space ??
-
-
-#define egore 0
-#define acore 0
-#define beh_model 0
-#define ev5_p2 1
-#define ev5_p1 0
-#define ldvpte_bug_fix 1
-#define spe_fix 0
-#define osf_chm_fix 0
-#define build_fixed_image 0
-#define enable_p4_fixups 0
-#define osf_svmin 1
-#define enable_physical_console 0
-#define fill_err_hack 0
-#define icflush_on_tbix 0
-#define max_cpuid 1
-#define perfmon_debug 0
-#define rax_mode 0
-
-#define hw_rei_spe hw_rei
-
-#include "ev5_defs.h"
-#include "ev5_impure.h"
-#include "ev5_alpha_defs.h"
-#include "ev5_paldef.h"
-#include "ev5_osfalpha_defs.h"
-#include "fromHudsonMacros.h"
-#include "fromHudsonOsf.h"
-#include "dc21164FromGasSources.h"
-#include "cserve.h"
-#include "tlaser.h"
-
-#define ldlp ldl_p
-#define ldqp ldq_p
-
-#define stlp stl_p
-#define stqp stq_p
-#define stqpc stqp
-
-#ifdef SIMOS
-#define ldqpl ldq_p
-#define sdqpl sdq_p
-#else
-<--bomb>
-#endif
-
-#define pt_entInt pt_entint
-#define pt_entArith pt_entarith
-#define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8)
-#define mchk_flag CNS_Q_FLAG
-#define mchk_sys_base 56
-#define mchk_cpu_base (CNS_Q_LD_LOCK + 8)
-#define mchk_offsets CNS_Q_EXC_ADDR
-#define mchk_mchk_code 8
-#define mchk_ic_perr_stat CNS_Q_ICPERR_STAT
-#define mchk_dc_perr_stat CNS_Q_DCPERR_STAT
-#define mchk_sc_addr CNS_Q_SC_ADDR
-#define mchk_sc_stat CNS_Q_SC_STAT
-#define mchk_ei_addr CNS_Q_EI_ADDR
-#define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR
-#define mchk_fill_syn CNS_Q_FILL_SYN
-#define mchk_ei_stat CNS_Q_EI_STAT
-#define mchk_exc_addr CNS_Q_EXC_ADDR
-#define mchk_ld_lock CNS_Q_LD_LOCK
-#define osfpcb_q_Ksp pcb_q_ksp
-#define pal_impure_common_size ((0x200 + 7) & 0xfff8)
-
-#ifdef BIG_TSUNAMI
-#define MAXPROC 0x3f
-#define IPIQ_addr 0x800
-#define IPIQ_shift 0
-#define IPIR_addr 0x840
-#define IPIR_shift 0
-#define RTC_addr 0x880
-#define RTC_shift 0
-#define DIR_addr 0xa2
-#else
-#define MAXPROC 0x3
-#define IPIQ_addr 0x080
-#define IPIQ_shift 12
-#define IPIR_addr 0x080
-#define IPIR_shift 8
-#define RTC_addr 0x080
-#define RTC_shift 4
-#define DIR_addr 0xa0
-#endif
-
-#define ALIGN_BLOCK \
- .align 5
-
-#define ALIGN_BRANCH \
- .align 3
-
-#define EXPORT(_x) \
- .align 5; \
- .globl _x; \
-_x:
-
-// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-// XXX the following is 'made up'
-// XXX bugnion
-
-// XXX bugnion not sure how to align 'quad'
-#define ALIGN_QUAD \
- .align 3
-
-#define ALIGN_128 \
- .align 7
-
-
-#define GET_IMPURE(_r) mfpr _r,pt_impure
-#define GET_ADDR(_r1,_off,_r2) lda _r1,_off(_r2)
-
-
-#define BIT(_x) (1<<(_x))
-
-
-// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-// XXX back to original code
-
-// .sbttl "System specific code - beh model version"
-
-//
-// Entry points
-// SYS$CFLUSH - Cache flush
-// SYS$CSERVE - Console service
-// SYS$WRIPIR - interprocessor interrupts
-// SYS$HALT_INTERRUPT - Halt interrupt
-// SYS$PASSIVE_RELEASE - Interrupt, passive release
-// SYS$INTERRUPT - Interrupt
-// SYS$RESET - Reset
-// SYS$ENTER_CONSOLE
-
-//
-// Macro to read TLINTRSUMx
-//
-// Based on the CPU_NUMBER, read either the TLINTRSUM0 or TLINTRSUM1 register
-//
-// Assumed register usage:
-// rsum TLINTRSUMx contents
-// raddr node space address
-// scratch scratch register
-
-
-// .macro Read_TLINTRSUMx rsum, raddr, scratch, ?label1, ?label2
-//
-// nop
-// mfpr 'scratch', pt_whami // Get our whami (VID)
-//
-// extbl 'scratch', #1, 'scratch' // shift down to bit 0
-// lda 'raddr', ^xff88(r31) // Get base node space address bits
-//
-// sll 'raddr', #24, 'raddr' // Shift up to proper position
-// srl 'scratch', #1, 'rsum' // Shift off the cpu number
-//
-// sll 'rsum', #22, 'rsum' // Get our node offset
-// addq 'raddr', 'rsum', 'raddr' // Get our base node space address
-//
-// blbs 'scratch', label1
-// lda 'raddr', <tlep$tlintrsum0_offset>('raddr')
-//
-// br r31, label2
-//label1: lda 'raddr', <tlep$tlintrsum1_offset>('raddr')
-//
-//label2: ldlp 'rsum', 0('raddr') // read the right tlintrsum reg
-//.endm
-
-#define Read_TLINTRSUMx(_rsum,_raddr,_scratch) \
- nop; \
- mfpr _scratch,pt_whami; \
- extbl _scratch,1,_scratch; \
- lda _raddr,0xff88(zero); \
- sll _raddr,24,_raddr; \
- srl _scratch,1,_rsum; \
- sll _rsum,22,_rsum; \
- addq _raddr,_rsum,_raddr; \
- blbs _scratch,1f; \
- lda _raddr,0x1180(_raddr); \
- br r31,2f; \
-1: \
- lda _raddr,0x11c0(_raddr); \
-2: ldlp _rsum,0(_raddr)
-
-
-
-//
-// Macro to write TLINTRSUMx
-//
-// Based on the CPU_NUMBER, write either the TLINTRSUM0 or TLINTRSUM1 register
-//
-// Assumed register usage:
-// rsum TLINTRSUMx write data
-// raddr node space address
-// scratch scratch register
-
-// .macro Write_TLINTRSUMx rsum, raddr, whami, ?label1, ?label2
-//
-// nop
-// mfpr 'whami', pt_whami // Get our whami (VID)
-//
-// extbl 'whami', #1, 'whami' // shift down to bit 0
-// lda 'raddr', ^xff88(r31) // Get base node space address bits
-//
-// sll 'raddr', #24, 'raddr' // Shift up to proper position
-// blbs 'whami', label1
-//
-// lda 'raddr', <tlep$tlintrsum0_offset>('raddr')
-// br r31, label2
-//
-// label1: lda 'raddr', <tlep$tlintrsum1_offset>('raddr')
-// label2: srl 'whami', #1, 'whami' // Shift off the cpu number
-//
-// sll 'whami', #22, 'whami' // Get our node offset
-// addq 'raddr', 'whami', 'raddr' // Get our base node space address
-//
-// mb
-// stqp 'rsum', 0('raddr') // write the right tlintrsum reg
-// mb
-// ldqp 'rsum', 0('raddr') // dummy read to tlintrsum
-// bis 'rsum', 'rsum', 'rsum' // needed to complete the ldqp above -jpo
-// .endm
-
-
-#define Write_TLINTRSUMx(_rsum,_raddr,_whami) \
- nop; \
- mfpr _whami,pt_whami; \
- extbl _whami,1,_whami; \
- lda _raddr,0xff88(zero); \
- sll _raddr,24,_raddr; \
- blbs _whami,1f; \
- lda _raddr,0x1180(_raddr);\
- br zero,2f; \
-1: lda _raddr,0x11c0(_raddr);\
-2: srl _whami,1,_whami; \
- addq _raddr,_whami,_raddr; \
- mb; \
- stqp _rsum,0(_raddr); \
- ldqp _rsum,0(_raddr); \
- bis _rsum,_rsum,_rsum
-
-
-//
-// Macro to determine highest priority TIOP Node ID from interrupt pending mask
-//
-// Assumed register usage:
-// rmask - TLINTRSUMx contents, shifted to isolate IOx bits
-// rid - TLSB Node ID of highest TIOP
-
-//.macro Intr_Find_TIOP rmask, rid, ?l1, ?l2, ?l3, ?l4, ?l5, ?l6
-// srl 'rmask', #4, 'rid' // check IOP8
-// blbc 'rid', l1 // not IOP8
-//
-// lda 'rid', 8(r31) // IOP8
-// br r31, l6
-//
-// l1: srl 'rmask', #3, 'rid' // check IOP7
-// blbc 'rid', l2 // not IOP7
-//
-// lda 'rid', 7(r31) // IOP7
-// br r31, l6
-//
-// l2: srl 'rmask', #2, 'rid' // check IOP6
-// blbc 'rid', l3 // not IOP6
-//
-// lda 'rid', 6(r31) // IOP6
-// br r31, l6
-//
-// l3: srl 'rmask', #1, 'rid' // check IOP5
-// blbc 'rid', l4 // not IOP5
-//
-// lda 'rid', 5(r31) // IOP5
-// br r31, l6
-//
-// l4: srl 'rmask', #0, 'rid' // check IOP4
-// blbc 'rid', l5 // not IOP4
-//
-// lda r14, 4(r31) // IOP4
-// br r31, l6
-//
-// l5: lda r14, 0(r31) // passive release
-// l6:
-// .endm
-
-
-#define Intr_Find_TIOP(_rmask,_rid) \
- srl _rmask,3,_rid; \
- blbc _rid,1f; \
- lda _rid,8(zero); \
- br zero,6f; \
-1: srl _rmask,3,_rid; \
- blbc _rid, 2f; \
- lda _rid, 7(r31); \
- br r31, 6f; \
-2: srl _rmask, 2, _rid; \
- blbc _rid, 3f; \
- lda _rid, 6(r31); \
- br r31, 6f; \
-3: srl _rmask, 1, _rid; \
- blbc _rid, 4f; \
- lda _rid, 5(r31); \
- br r31, 6f; \
-4: srl _rmask, 0, _rid; \
- blbc _rid, 5f; \
- lda r14, 4(r31); \
- br r31, 6f; \
-5: lda r14, 0(r31); \
-6:
-
-
-
-
-//
-// Macro to calculate base node space address for given node id
-//
-// Assumed register usage:
-// rid - TLSB node id
-// raddr - base node space address
-
-//.macro Get_TLSB_Node_Address rid, raddr
-// sll 'rid', #22, 'rid' // Get offset of IOP node
-// lda 'raddr', ^xff88(r31) // Get base node space address bits
-//
-// sll 'raddr', #24, 'raddr' // Shift up to proper position
-// addq 'raddr', 'rid', 'raddr' // Get TIOP node space address
-// .iif ne turbo_pcia_intr_fix, srl 'rid', #22, 'rid' // Restore IOP node id
-//.endm
-
-
-#define turbo_pcia_intr_fix 0
-
-
-#if turbo_pcia_intr_fix != 0
-#define Get_TLSB_Node_Address(_rid,_raddr) \
- sll _rid,22,_rid; \
- lda _raddr,0xff88(zero); \
- sll _raddr,24,_raddr; \
- addq _raddr,_rid,_raddr; \
- srl _rid,22,_rid
-#else
-#define Get_TLSB_Node_Address(_rid,_raddr) \
- sll _rid,22,_rid; \
- lda _raddr,0xff88(zero); \
- sll _raddr,24,_raddr; \
- addq _raddr,_rid,_raddr
-#endif
-
-
-
-
-
-// .macro mchk$TLEPstore rlog, rs, rs1, nodebase, tlepreg, clr, tlsb, crd
-// .iif eq tlsb, lda 'rs1',<tlep$'tlepreg'_offset>(r31)
-// .iif ne tlsb, lda 'rs1',<tlsb$'tlepreg'_offset>(r31)
-// or 'rs1', 'nodebase', 'rs1'
-// ldlp 'rs', 0('rs1')
-// .iif eq crd, stlp 'rs', mchk$'tlepreg'('rlog') // store in frame
-// .iif ne crd, stlp 'rs', mchk$crd_'tlepreg'('rlog') // store in frame
-// .iif ne clr, stlp 'rs',0('rs1') // optional write to clear
-// .endm
-
-
-// .macro OSFmchk$TLEPstore tlepreg, clr=0, tlsb=0
-// mchk$TLEPstore r14, r8, r4, r13, <tlepreg>, <clr>, <tlsb>, crd=0
-// .endm
-
-#define CONCAT(_a,_b) _a ## _b
-
-#define OSFmchk_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
- lda _rs1,CONCAT(tlep_,_tlepreg)(zero); \
- or _rs1,_nodebase,_rs1; \
- ldlp _rs1,0(_rs1); \
- stlp _rs,CONCAT(mchk_,_tlepreg)(_rlog)
-
-
-#define OSFmchk_TLEPstore(_tlepreg) OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
-
-
-// .macro OSFcrd$TLEPstore tlepreg, clr=0, tlsb=0
-// mchk$TLEPstore r14, r10, r1, r0, <tlepreg>, <clr>, <tlsb>, crd=1
-// .endm
-
-#define OSFcrd_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
- lda _rs1,CONCAT(tlep_,_tlepreg)(zero); \
- or _rs1,_nodebase,_rs1; \
- ldlp _rs1,0(_rs1); \
- stlp _rs,CONCAT(mchk_crd_,_tlepreg)(_rlog)
-
-#define OSFcrd_TLEPstore_tlsb_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
- lda _rs1,CONCAT(tlsb_,_tlepreg)(zero); \
- or _rs1,_nodebase,_rs1; \
- ldlp _rs1,0(_rs1); \
- stlp _rs,CONCAT(mchk_crd_,_tlepreg)(_rlog)
-
-#define OSFcrd_TLEPstore_tlsb_clr_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
- lda _rs1,CONCAT(tlsb_,_tlepreg)(zero); \
- or _rs1,_nodebase,_rs1; \
- ldlp _rs1,0(_rs1); \
- stlp _rs,CONCAT(mchk_crd_,_tlepreg)(_rlog); \
- stlp _rs,0(_rs1)
-
-
-#define OSFcrd_TLEPstore(_tlepreg) OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
-#define OSFcrd_TLEPstore_tlsb(_tlepreg) OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg)
-#define OSFcrd_TLEPstore_tlsb_clr(_tlepreg) OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg)
-
-
-
-
-// .macro save_pcia_intr irq
-// and r13, #^xf, r25 // isolate low 4 bits
-// addq r14, #4, r14 // format the TIOP Node id field
-// sll r14, #4, r14 // shift the TIOP Node id
-// or r14, r25, r10 // merge Node id/hose/HPC
-// mfpr r14, pt14 // get saved value
-// extbl r14, #'irq', r25 // confirm none outstanding
-// bne r25, sys$machine_check_while_in_pal
-// insbl r10, #'irq', r10 // align new info
-// or r14, r10, r14 // merge info
-// mtpr r14, pt14 // save it
-// bic r13, #^xf, r13 // clear low 4 bits of vector
-// .endm
-
-#define save_pcia_intr(_irq) \
- and r13, 0xf, r25; \
- addq r14, 4, r14; \
- sll r14, 4, r14; \
- or r14, r25, r10; \
- mfpr r14, pt14; \
- extbl r14, _irq, r25; \
- bne r25, sys_machine_check_while_in_pal; \
- insbl r10, _irq, r10; \
- or r14, r10, r14; \
- mtpr r14, pt14; \
- bic r13, 0xf, r13
-
-
-
- ALIGN_BLOCK
-
-// .sbttl "wripir - PALcode for wripir instruction"
-//orig SYS$WRIPIR: // R16 has the processor number.
-
-EXPORT(sys_wripir)
-
-//++
-// Convert the processor number to a CPU mask
-//--
- and r16,MAXPROC, r14 // mask the top stuff (4 or 64 CPUs supported)
- bis r31,0x1,r16 // get a one
- sll r16,r14,r14 // shift the bit to the right place
- sll r14,IPIQ_shift,r14
-
-//++
-// Build the Broadcast Space base address
-//--
- lda r16,0xf01(r31)
- sll r16,32,r16
- ldah r13,0xa0(r31)
- sll r13,8,r13
- bis r16,r13,r16
- lda r16,IPIQ_addr(r16)
-
-//++
-// Send out the IP Intr
-//--
- stqp r14, 0(r16) // Tsunami MISC Register
- wmb // Push out the store
-
- hw_rei
-
-
- ALIGN_BLOCK
-// .sbttl "CFLUSH- PALcode for CFLUSH instruction"
-//+
-// SYS$CFLUSH
-// Entry:
-//
-// R16 - contains the PFN of the page to be flushed
-//
-// Function:
-// Flush all Dstream caches of 1 entire page
-//
-//-
-
-EXPORT(sys_cflush)
-
-// #convert pfn to addr, and clean off <63:20>
-// #sll r16, <page_offset_size_bits>+<63-20>>, r12
- sll r16, page_offset_size_bits+(63-20),r12
-
-// #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16>
-// # stolen from srcmax code. XXX bugnion
- lda r13, 0x10(r31) // assume 16Mbytes of cache
- sll r13, 20, r13 // convert to bytes
-
-
- srl r12, 63-20, r12 // shift back to normal position
- xor r12, r13, r12 // xor addr<18>
-
- or r31, 8192/(32*8), r13 // get count of loads
- nop
-
-cflush_loop:
- subq r13, 1, r13 // decr counter
- mfpr r25, ev5__intid // Fetch level of interruptor
-
- ldqp r31, 32*0(r12) // do a load
- ldqp r31, 32*1(r12) // do next load
-
- ldqp r31, 32*2(r12) // do next load
- ldqp r31, 32*3(r12) // do next load
-
- ldqp r31, 32*4(r12) // do next load
- ldqp r31, 32*5(r12) // do next load
-
- ldqp r31, 32*6(r12) // do next load
- ldqp r31, 32*7(r12) // do next load
-
- mfpr r14, ev5__ipl // Fetch current level
- lda r12, (32*8)(r12) // skip to next cache block addr
-
- cmple r25, r14, r25 // R25 = 1 if intid .less than or eql ipl
- beq r25, 1f // if any int's pending, re-queue CFLUSH -- need to check for hlt interrupt???
-
- bne r13, cflush_loop // loop till done
- hw_rei // back to user
-
- ALIGN_BRANCH
-1: // Here if interrupted
- mfpr r12, exc_addr
- subq r12, 4, r12 // Backup PC to point to CFLUSH
-
- mtpr r12, exc_addr
- nop
-
- mfpr r31, pt0 // Pad exc_addr write
- hw_rei
-
-
- ALIGN_BLOCK
-// .sbttl "CSERVE- PALcode for CSERVE instruction"
-//+
-// SYS$CSERVE
-//
-// Function:
-// Various functions for private use of console software
-//
-// option selector in r0
-// arguments in r16....
-//
-//
-// r0 = 0 unknown
-//
-// r0 = 1 ldqp
-// r0 = 2 stqp
-// args, are as for normal STQP/LDQP in VMS PAL
-//
-// r0 = 3 dump_tb's
-// r16 = detination PA to dump tb's to.
-//
-// r0<0> = 1, success
-// r0<0> = 0, failure, or option not supported
-// r0<63:1> = (generally 0, but may be function dependent)
-// r0 - load data on ldqp
-//
-//-
-EXPORT(sys_cserve)
-
-#ifdef SIMOS
- /* taken from scrmax */
- cmpeq r18, CSERVE_K_RD_IMPURE, r0
- bne r0, Sys_Cserve_Rd_Impure
-
- cmpeq r18, CSERVE_K_JTOPAL, r0
- bne r0, Sys_Cserve_Jtopal
- call_pal 0
-
- or r31, r31, r0
- hw_rei // and back we go
-
-Sys_Cserve_Rd_Impure:
- mfpr r0, pt_impure // Get base of impure scratch area.
- hw_rei
-
- ALIGN_BRANCH
-
-Sys_Cserve_Jtopal:
- bic a0, 3, t8 // Clear out low 2 bits of address
- bis t8, 1, t8 // Or in PAL mode bit
- mtpr t8,exc_addr
- hw_rei
-
-
-#else /* SIMOS */
-
- cmpeq r16, cserve_ldlp, r12 // check for ldqp
- bne r12, 1f // br if
-
- cmpeq r16, cserve_stlp, r12 // check for stqp
- bne r12, 2f // br if
-
- cmpeq r16, cserve_callback, r12 // check for callback entry
- bne r12, csrv_callback // br if
-
- cmpeq r16, cserve_identify, r12 // check for callback entry
- bne r12, csrv_identify // br if
-
- or r31, r31, r0 // set failure
- nop // pad palshadow write
-
- hw_rei // and back we go
-#endif /* SIMOS */
-
-// ldqp
- ALIGN_QUAD
-1:
- ldqp r0,0(r17) // get the data
- nop // pad palshadow write
-
- hw_rei // and back we go
-
-
-// stqp
- ALIGN_QUAD
-2:
- stqp r18, 0(r17) // store the data
-#ifdef SIMOS
- lda r0,17(r31) // bogus
-#else
- lda r0, CSERVE_SUCCESS(r31) // set success
-#endif
- hw_rei // and back we go
-
-
- ALIGN_QUAD
-csrv_callback:
- ldq r16, 0(r17) // restore r16
- ldq r17, 8(r17) // restore r17
- lda r0, hlt_c_callback(r31)
- br r31, sys_enter_console
-
-
-csrv_identify:
- mfpr r0, pal_base
- ldqp r0, 8(r0)
- hw_rei
-
-
-// dump tb's
- ALIGN_QUAD
-0:
- // DTB PTEs - 64 entries
- addq r31, 64, r0 // initialize loop counter
- nop
-
-1: mfpr r12, ev5__dtb_pte_temp // read out next pte to temp
- mfpr r12, ev5__dtb_pte // read out next pte to reg file
-
- subq r0, 1, r0 // decrement loop counter
- nop // Pad - no Mbox instr in cycle after mfpr
-
- stqp r12, 0(r16) // store out PTE
- addq r16, 8 ,r16 // increment pointer
-
- bne r0, 1b
-
- ALIGN_BRANCH
- // ITB PTEs - 48 entries
- addq r31, 48, r0 // initialize loop counter
- nop
-
-2: mfpr r12, ev5__itb_pte_temp // read out next pte to temp
- mfpr r12, ev5__itb_pte // read out next pte to reg file
-
- subq r0, 1, r0 // decrement loop counter
- nop //
-
- stqp r12, 0(r16) // store out PTE
- addq r16, 8 ,r16 // increment pointer
-
- bne r0, 2b
- or r31, 1, r0 // set success
-
- hw_rei // and back we go
-
-
-// .sbttl "SYS$INTERRUPT - Interrupt processing code"
-
-//+
-// SYS$INTERRUPT
-//
-// Current state:
-// Stack is pushed
-// ps, sp and gp are updated
-// r12, r14 - available
-// r13 - INTID (new EV5 IPL)
-// r25 - ISR
-// r16, r17, r18 - available
-//
-//-
-
-
-EXPORT(sys_interrupt)
- cmpeq r13, 31, r12
- bne r12, sys_int_mchk_or_crd // Check for level 31 interrupt (machine check or crd)
-
- cmpeq r13, 30, r12
- bne r12, sys_int_powerfail // Check for level 30 interrupt (powerfail)
-
- cmpeq r13, 29, r12
- bne r12, sys_int_perf_cnt // Check for level 29 interrupt (performance counters)
-
- cmpeq r13, 23, r12
- bne r12, sys_int_23 // Check for level 23 interrupt
- // IPI in Tsunami
-
- cmpeq r13, 22, r12
- bne r12, sys_int_22 // Check for level 22 interrupt
- // timer interrupt
-
- cmpeq r13, 21, r12
- bne r12, sys_int_21 // Check for level 21 interrupt
- // I/O
-
- cmpeq r13, 20, r12
- bne r12, sys_int_20 // Check for level 20 interrupt (might be corrected
- // system error interrupt)
-
- mfpr r14, exc_addr // ooops, something is wrong
- br r31, pal_pal_bug_check_from_int
-
-
-
-
-//+
-//sys$int_2*
-// Routines to handle device interrupts at IPL 23-20.
-// System specific method to ack/clear the interrupt, detect passive release,
-// detect interprocessor (22), interval clock (22), corrected
-// system error (20)
-//
-// Current state:
-// Stack is pushed
-// ps, sp and gp are updated
-// r12, r14 - available
-// r13 - INTID (new EV5 IPL)
-// r25 - ISR
-//
-// On exit:
-// Interrupt has been ack'd/cleared
-// a0/r16 - signals IO device interrupt
-// a1/r17 - contains interrupt vector
-// exit to ent_int address
-//
-//-
- ALIGN_BRANCH
-sys_int_23:
- or r31,0,r16 // IPI interrupt A0 = 0
- lda r12,0xf01(r31) // build up an address for the MISC register
- sll r12,16,r12
- lda r12,0xa000(r12)
- sll r12,16,r12
- lda r12,IPIR_addr(r12)
-
- mfpr r10, pt_whami // get CPU ID
- extbl r10, 1, r10 // Isolate just whami bits
- or r31,0x1,r14 // load r14 with bit to clear
- sll r14,r10,r14 // left shift by CPU ID
- sll r14,IPIR_shift,r14
- stq_p r14, 0(r12) // clear the ipi interrupt
-
- br r31, pal_post_interrupt // Notify the OS
-
-
- ALIGN_BRANCH
-sys_int_22:
- or r31,1,r16 // a0 means it is a clock interrupt
- lda r12,0xf01(r31) // build up an address for the MISC register
- sll r12,16,r12
- lda r12,0xa000(r12)
- sll r12,16,r12
- lda r12,RTC_addr(r12)
-
- mfpr r10, pt_whami // get CPU ID
- extbl r10, 1, r10 // Isolate just whami bits
- or r31,0x1,r14 // load r14 with bit to clear
- sll r14,r10,r14 // left shift by CPU ID
- sll r14,RTC_shift,r14 // put the bits in the right position
- stq_p r14, 0(r12) // clear the rtc interrupt
-
- br r31, pal_post_interrupt // Tell the OS
-
-
- ALIGN_BRANCH
-sys_int_20:
- Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
- srl r13, 12, r13 // shift down to examine IPL15
-
- Intr_Find_TIOP(r13,r14)
- beq r14, 1f
-
- Get_TLSB_Node_Address(r14,r10)
- lda r10, 0xa40(r10) // Get base TLILID address
-
- ldlp r13, 0(r10) // Read the TLILID register
-#if turbo_pcia_intr_fix == 0
-//orig .if eq turbo_pcia_intr_fix
- bne r13, pal_post_dev_interrupt
-//orig .iff
- beq r13, 1f
-
- and r13, 0x3, r10 // check for PCIA bits
- beq r10, pal_post_dev_interrupt // done if nothing set
- save_pcia_intr(1)
- br r31, pal_post_dev_interrupt //
-// orig .endc
-#endif /* turbo_pcia_intr_fix == 0 */
-
-1: lda r16, osfint_c_passrel(r31) // passive release
- br r31, pal_post_interrupt //
-
-
- ALIGN_BRANCH
-sys_int_21:
-
- lda r12,0xf01(r31) // calculate DIRn address
- sll r12,32,r12
- ldah r13,DIR_addr(r31)
- sll r13,8,r13
- bis r12,r13,r12
-
- mfpr r13, pt_whami // get CPU ID
- extbl r13, 1, r13 // Isolate just whami bits
-
-#ifdef BIG_TSUNAMI
- sll r13,4,r13
- or r12,r13,r12
-#else
- lda r12,0x0080(r12)
- and r13,0x1,r14 // grab LSB and shift left 6
- sll r14,6,r14
- and r13,0x2,r10 // grabl LSB+1 and shift left 9
- sll r10,9,r10
-
- mskbl r12,0,r12 // calculate DIRn address
- lda r13,0x280(r31)
- bis r12,r13,r12
- or r12,r14,r12
- or r12,r10,r12
-#endif
-
- ldqp r13, 0(r12) // read DIRn
-
- or r31,1,r14 // set bit 55 (ISA Interrupt)
- sll r14,55,r14
-
- and r13, r14, r14 // check if bit 55 is set
- lda r16,0x900(r31) // load offset for normal into r13
- beq r14, normal_int // if not compute the vector normally
-
- lda r16,0x800(r31) // replace with offset for pic
- lda r12,0xf01(r31) // build an addr to access PIC
- sll r12,32,r12 // at f01fc000000
- ldah r13,0xfc(r31)
- sll r13,8,r13
- bis r12,r13,r12
- ldqp r13,0x0020(r12) // read PIC1 ISR for interrupting dev
-
-normal_int:
- //ctlz r13,r14 // count the number of leading zeros
- // EV5 doesn't have ctlz, but we do, so lets use it
- .byte 0x4e
- .byte 0x06
- .byte 0xed
- .byte 0x73
- lda r10,63(r31)
- subq r10,r14,r17 // subtract from
-
- lda r13,0x10(r31)
- mulq r17,r13,r17 // compute 0x900 + (0x10 * Highest DIRn-bit)
- addq r17,r16,r17
-
- or r31,3,r16 // a0 means it is a I/O interrupt
-
- br r31, pal_post_interrupt
-
- ALIGN_BRANCH
-pal_post_dev_interrupt:
- or r13, r31, r17 // move vector to a1
- or r31, osfint_c_dev, r16 // a0 signals IO device interrupt
-
-pal_post_interrupt:
- mfpr r12, pt_entint
-
- mtpr r12, exc_addr
-
- nop
- nop
-
- hw_rei_spe
-
-
-
-//+
-// sys_passive_release
-// Just pretend the interrupt never occurred.
-//-
-
-EXPORT(sys_passive_release)
- mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps
- nop
-
- mfpr r31, pt0 // Pad write to dtb_cm
- hw_rei
-
-//+
-//sys_int_powerfail
-// A powerfail interrupt has been detected. The stack has been pushed.
-// IPL and PS are updated as well.
-//
-// I'm not sure what to do here, I'm treating it as an IO device interrupt
-//
-//-
-
- ALIGN_BLOCK
-sys_int_powerfail:
- lda r12, 0xffc4(r31) // get GBUS_MISCR address bits
- sll r12, 24, r12 // shift to proper position
- ldqp r12, 0(r12) // read GBUS_MISCR
- srl r12, 5, r12 // isolate bit <5>
- blbc r12, 1f // if clear, no missed mchk
-
- // Missed a CFAIL mchk
- lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits
- sll r13, 24, r13 // shift to proper position
- lda r14, 0x40(r31) // get bit <6> mask
- ldqp r12, 0(r13) // read GBUS$SERNUM
- or r12, r14, r14 // set bit <6>
- stqp r14, 0(r13) // clear GBUS$SERNUM<6>
- mb
- mb
-
-1: br r31, sys_int_mchk // do a machine check
-
- lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector
- mfpr r25, pt_entint
-
- lda r16, osfint_c_dev(r31) // a0 to device code
- mtpr r25, exc_addr
-
- nop // pad exc_addr write
- nop
-
- hw_rei_spe
-
-//+
-// sys$halt_interrupt
-// A halt interrupt has been detected. Pass control to the console.
-//
-//
-//-
- EXPORT(sys_halt_interrupt)
-
- ldah r13, 0x1800(r31) // load Halt/^PHalt bits
- Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits
-
- mtpr r11, dtb_cm // Restore Mbox current mode
- nop
- nop
- mtpr r0, pt0
-#ifndef SIMOS
- pvc_jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
-#endif
- lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt
- br r31, sys_enter_console // enter the console
-
-
-
-//+
-// sys$int_mchk_or_crd
-//
-// Current state:
-// Stack is pushed
-// ps, sp and gp are updated
-// r12
-// r13 - INTID (new EV5 IPL)
-// r14 - exc_addr
-// r25 - ISR
-// r16, r17, r18 - available
-//
-//-
- ALIGN_BLOCK
-
-sys_int_mchk_or_crd:
- srl r25, isr_v_mck, r12
- blbs r12, sys_int_mchk
- //+
- // Not a Machine check interrupt, so must be an Internal CRD interrupt
- //-
-
- mb //Clear out Cbox prior to reading IPRs
- srl r25, isr_v_crd, r13 //Check for CRD
- blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!!
-
- lda r9, 1(r31)
- sll r9, hwint_clr_v_crdc, r9 // get ack bit for crd
- mtpr r9, ev5__hwint_clr // ack the crd interrupt
-
- or r31, r31, r12 // clear flag
- lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code
-
-sys_merge_sys_corr:
- ldah r14, 0xfff0(r31)
- mtpr r0, pt0 // save r0 for scratch
- zap r14, 0xE0, r14 // Get Cbox IPR base
- mtpr r1, pt1 // save r0 for scratch
-
- ldqp r0, ei_addr(r14) // EI_ADDR IPR
- ldqp r10, fill_syn(r14) // FILL_SYN IPR
- bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub
-
- blbs r12, 1f // no scrubbing for IRQ0 case
-// XXX bugnion pvc_jsr crd_scrub_mem, bsr=1
- bsr r13, sys_crd_scrub_mem // and go scrub
-
- // ld/st pair in scrub routine will have finished due
- // to ibox stall of stx_c. Don't need another mb.
- ldqp r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
- or r8, r31, r12 // Must only be executed once in this flow, and must
- br r31, 2f // be after the scrub routine.
-
-1: ldqp r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
- // For IRQ0 CRD case only - meaningless data.
-
-2: mfpr r13, pt_mces // Get MCES
- srl r12, ei_stat_v_ei_es, r14 // Isolate EI_STAT:EI_ES
- blbc r14, 6f // branch if 630
- srl r13, mces_v_dsc, r14 // check if 620 reporting disabled
- blbc r14, 5f // branch if enabled
- or r13, r31, r14 // don't set SCE if disabled
- br r31, 8f // continue
-5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit
- br r31, 8f
-
-6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled
- blbc r14, 7f // branch if enabled
- or r13, r31, r14 // don't set PCE if disabled
- br r31, 8f // continue
-7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit
-
- // Setup SCB if dpc is not set
-8: mtpr r14, pt_mces // Store updated MCES
- srl r13, mces_v_sce, r1 // Get SCE
- srl r13, mces_v_pce, r14 // Get PCE
- or r1, r14, r1 // SCE OR PCE, since they share
- // the CRD logout frame
- // Get base of the logout area.
- GET_IMPURE(r14) // addr of per-cpu impure area
- GET_ADDR(r14,(pal_logout_area+mchk_crd_base),r14)
-
- blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame
-
- // Set the 2nd error flag in the logout area:
-
- lda r1, 3(r31) // Set retry and 2nd error flags
- sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword
- stlp r1, mchk_crd_flag+4(r14) // store flag longword
- br sys_crd_ack
-
-sys_crd_write_logout_frame:
- // should only be here if neither the pce or sce bits are set
-
- //+
- // Write the mchk code to the logout area
- //-
- stqp r9, mchk_crd_mchk_code(r14)
-
-
- //+
- // Write the first 2 quadwords of the logout area:
- //-
- lda r1, 1(r31) // Set retry flag
- sll r1, 63, r9 // Move retry flag to bit 63
- lda r1, mchk_crd_size(r9) // Combine retry flag and frame size
- stqp r1, mchk_crd_flag(r14) // store flag/frame size
-
-#ifndef SIMOS
- /* needed? bugnion */
- lda r1, mchk_crd_sys_base(r31) // sys offset
- sll r1, 32, r1
- lda r1, mchk_crd_cpu_base(r1) // cpu offset
- stqp r1, mchk_crd_offsets(r14) // store sys offset/cpu offset into logout frame
-
-#endif
- //+
- // Write error IPRs already fetched to the logout area
- //-
- stqp r0, mchk_crd_ei_addr(r14)
- stqp r10, mchk_crd_fill_syn(r14)
- stqp r8, mchk_crd_ei_stat(r14)
- stqp r25, mchk_crd_isr(r14)
- //+
- // Log system specific info here
- //-
-crd_storeTLEP_:
- lda r1, 0xffc4(r31) // Get GBUS$MISCR address
- sll r1, 24, r1
- ldqp r1, 0(r1) // Read GBUS$MISCR
- sll r1, 16, r1 // shift up to proper field
- mfpr r10, pt_whami // get our node id
- extbl r10, 1, r10 // shift to bit 0
- or r1, r10, r1 // merge MISCR and WHAMI
- stlp r1, mchk_crd_whami(r14) // write to crd logout area
- srl r10, 1, r10 // shift off cpu number
-
- Get_TLSB_Node_Address(r10,r0) // compute our nodespace address
-
- OSFcrd_TLEPstore_tlsb(tldev)
- OSFcrd_TLEPstore_tlsb_clr(tlber)
- OSFcrd_TLEPstore_tlsb_clr(tlesr0)
- OSFcrd_TLEPstore_tlsb_clr(tlesr1)
- OSFcrd_TLEPstore_tlsb_clr(tlesr2)
- OSFcrd_TLEPstore_tlsb_clr(tlesr3)
-
-sys_crd_ack:
- mfpr r0, pt0 // restore r0
- mfpr r1, pt1 // restore r1
-
- srl r12, ei_stat_v_ei_es, r12
- blbc r12, 5f
- srl r13, mces_v_dsc, r10 // logging enabled?
- br r31, 6f
-5: srl r13, mces_v_dpc, r10 // logging enabled?
-6: blbc r10, sys_crd_post_interrupt // logging enabled -- report it
-
- // logging not enabled --
- // Get base of the logout area.
- GET_IMPURE(r13) // addr of per-cpu impure area
- GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13)
- ldlp r10, mchk_crd_rsvd(r13) // bump counter
- addl r10, 1, r10
- stlp r10, mchk_crd_rsvd(r13)
- mb
- br r31, sys_crd_dismiss_interrupt // just return
-
- //+
- // The stack is pushed. Load up a0,a1,a2 and vector via entInt
- //
- //-
-
- ALIGN_BRANCH
-sys_crd_post_interrupt:
- lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
- lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector
-
- blbc r12, 1f
- lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector
-
-1: subq r31, 1, r18 // get a -1
- mfpr r25, pt_entInt
-
- srl r18, 42, r18 // shift off low bits of kseg addr
- mtpr r25, exc_addr // load interrupt vector
-
- sll r18, 42, r18 // shift back into position
- or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
-
- hw_rei_spe // done
-
-
- //+
- // The stack is pushed. Need to back out of it all.
- //-
-
-sys_crd_dismiss_interrupt:
- br r31, Call_Pal_Rti
-
-
-// .sbttl sys_crd_scrub_mem
-
- //+
- //
- // sys_crd_scrub_mem
- // called
- // jsr r13, sys$crd_scrub_mem
- // r0 = addr of cache block
- //
- //-
-
-
-
- ALIGN_BLOCK // align for branch target
-sys_crd_scrub_mem:
- // now find error in memory, and attempt to scrub that cache block
- // This routine just scrubs the failing octaword
- // Only need to "touch" one quadword per octaword to accomplish the scrub
- srl r0, 39, r8 // get high bit of bad pa
- blbs r8, 1f // don't attempt fixup on IO space addrs
- nop // needed to align the ldqpl to octaword boundary
- nop // "
-
- ldqpl r8, 0(r0) // attempt to read the bad memory
- // location
- // (Note bits 63:40,3:0 of ei_addr
- // are set to 1, but as long as
- // we are doing a phys ref, should
- // be ok)
- nop // Needed to keep the Ibox from swapping the ldqpl into E1
-
- stqpc r8, 0(r0) // Store it back if it is still there.
- // If store fails, location already
- // scrubbed by someone else
-
- nop // needed to align the ldqpl to octaword boundary
-
- lda r8, 0x20(r31) // flip bit 5 to touch next hexaword
- xor r8, r0, r0
- nop // needed to align the ldqpl to octaword boundary
- nop // "
-
- ldqpl r8, 0(r0) // attempt to read the bad memory
- // location
- // (Note bits 63:40,3:0 of ei_addr
- // are set to 1, but as long as
- // we are doing a phys ref, should
- // be ok)
- nop // Needed to keep the Ibox from swapping the ldqpl into E1
-
- stqpc r8, 0(r0) // Store it back if it is still there.
- // If store fails, location already
- // scrubbed by someone else
-
- lda r8, 0x20(r31) // restore r0 to original address
- xor r8, r0, r0
-
- //at this point, ei_stat could be locked due to a new corr error on the ld,
- //so read ei_stat to unlock AFTER this routine.
-
-// XXX bugnion pvc$jsr crd_scrub_mem, bsr=1, dest=1
-1: ret r31, (r13) // and back we go
-
-
-// .sbttl "SYS$INT_MCHK - MCHK Interrupt code"
-//+
-// Machine check interrupt from the system. Setup and join the
-// regular machine check flow.
-// On exit:
-// pt0 - saved r0
-// pt1 - saved r1
-// pt4 - saved r4
-// pt5 - saved r5
-// pt6 - saved r6
-// pt10 - saved exc_addr
-// pt_misc<47:32> - mchk code
-// pt_misc<31:16> - scb vector
-// r14 - base of Cbox IPRs in IO space
-// MCES<mchk> is set
-//-
- ALIGN_BLOCK
-sys_int_mchk:
- lda r14, mchk_c_sys_hrd_error(r31)
- mfpr r12, exc_addr
-
- addq r14, 1, r14 // Flag as interrupt
- nop
-
- sll r14, 32, r14 // Move mchk code to position
- mtpr r12, pt10 // Stash exc_addr
-
- mfpr r12, pt_misc // Get MCES and scratch
- mtpr r0, pt0 // Stash for scratch
-
- zap r12, 0x3c, r12 // Clear scratch
- blbs r12, sys_double_machine_check // MCHK halt if double machine check
-
- or r12, r14, r12 // Combine mchk code
- lda r14, scb_v_sysmchk(r31) // Get SCB vector
-
- sll r14, 16, r14 // Move SCBv to position
- or r12, r14, r14 // Combine SCBv
-
- bis r14, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
- mtpr r14, pt_misc // Save mchk code!scbv!whami!mces
-
- ldah r14, 0xfff0(r31)
- mtpr r1, pt1 // Stash for scratch
-
- zap r14, 0xE0, r14 // Get Cbox IPR base
- mtpr r4, pt4
-
- mtpr r5, pt5
-
-#if beh_model
-// .if ne beh_model
- ldah r25, 0xC000(r31) // Get base of demon space
- lda r25, 0x340(r25) // Add interrupt demon offset
-
- ldqp r13, 0(r25) // Read the control register
- nop
-
- and r13, 0x10, r8 // For debug, check that the interrupt is expected
- beq r8, interrupt_not_expected
-
- bic r13, 0x10, r13
- stqp r13, 0(r25) // Ack and clear the interrupt
-// XXX bugnion pvc$violate 379 // stqp can't trap except replay. mt ipr only problem if mf same ipr in same shadow
- .endc
-#endif
-
- mtpr r6, pt6
- br r31, sys_mchk_collect_iprs // Join common machine check flow
-
-
-// .sbttl "SYS$INT_PERF_CNT - Performance counter interrupt code"
-//+
-//sys$int_perf_cnt
-//
-// A performance counter interrupt has been detected. The stack has been pushed.
-// IPL and PS are updated as well.
-//
-// on exit to interrupt entry point ENTINT::
-// a0 = osfint$c_perf
-// a1 = scb$v_perfmon (650)
-// a2 = 0 if performance counter 0 fired
-// a2 = 1 if performance counter 1 fired
-// a2 = 2 if performance counter 2 fired
-// (if more than one counter overflowed, an interrupt will be
-// generated for each counter that overflows)
-//
-//
-//-
- ALIGN_BLOCK
-sys_int_perf_cnt: // Performance counter interrupt
- lda r17, scb_v_perfmon(r31) // a1 to interrupt vector
- mfpr r25, pt_entint
-
- lda r16, osfint_c_perf(r31) // a0 to perf counter code
- mtpr r25, exc_addr
-
- //isolate which perf ctr fired, load code in a2, and ack
- mfpr r25, isr
- or r31, r31, r18 // assume interrupt was pc0
-
- srl r25, isr_v_pc1, r25 // isolate
- cmovlbs r25, 1, r18 // if pc1 set, load 1 into r14
-
- srl r25, 1, r25 // get pc2
- cmovlbs r25, 2, r18 // if pc2 set, load 2 into r14
-
- lda r25, 1(r31) // get a one
- sll r25, r18, r25
-
- sll r25, hwint_clr_v_pc0c, r25 // ack only the perf counter that generated the interrupt
- mtpr r25, hwint_clr
-
- hw_rei_spe
-
-
-
- ALIGN_BLOCK
-// .sbttl "System specific RESET code"
-//+
-// RESET code
-// On entry:
-// r1 = pal_base +8
-//
-// Entry state on trap:
-// r0 = whami
-// r2 = base of scratch area
-// r3 = halt code
-// and the following 3 if init_cbox is enabled:
-// r5 = sc_ctl
-// r6 = bc_ctl
-// r7 = bc_cnfg
-//
-// Entry state on switch:
-// r17 - new PC
-// r18 - new PCBB
-// r19 - new VPTB
-//
-//-
-
-#if rax_mode==0
- .globl sys_reset
-sys_reset:
-// mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load
- mtpr r31, itb_ia // clear the ITB
- mtpr r31, dtb_ia // clear the DTB
-
- lda r1, -8(r1) // point to start of code
- mtpr r1, pal_base // initialize PAL_BASE
-
- // Interrupts
- mtpr r31, astrr // stop ASTs
- mtpr r31, aster // stop ASTs
- mtpr r31, sirr // clear software interrupts
-
- mtpr r0, pt1 // r0 is whami (unless we entered via swp)
-
-//orig ldah r1, <<1@<icsr$v_sde-16>> ! <1@<icsr$v_fpe-16>> ! <2@<icsr$v_spe-16>>>(r31)
- ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero)
-
-#if disable_crd == 0
-// .if eq disable_crd
- bis r31, 1, r0
- sll r0, icsr_v_crde, r0 // A 1 in iscr<corr_read_enable>
- or r0, r1, r1 // Set the bit
-#endif
-
- mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable,
- // super page enabled, correct read per assembly option
-
- // Mbox/Dcache init
-//orig lda r1, <1@<mcsr$v_sp1>>(r31)
- lda r1,BIT(mcsr_v_sp1)(zero)
-
- mtpr r1, mcsr // MCSR - Super page enabled
- lda r1, BIT(dc_mode_v_dc_ena)(r31)
- ALIGN_BRANCH
-// mtpr r1, dc_mode // turn Dcache on
- nop
-
- mfpr r31, pt0 // No Mbox instr in 1,2,3,4
- mfpr r31, pt0
- mfpr r31, pt0
- mfpr r31, pt0
- mtpr r31, dc_flush // flush Dcache
-
- // build PS (IPL=7,CM=K,VMM=0,SW=0)
- lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7
- lda r1, 0x1F(r31)
- mtpr r1, ipl // set internal <ipl>=1F
- mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy
- mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy
-
- // Create the PALtemp pt_intmask -
- // MAP:
- // OSF IPL EV5 internal IPL(hex) note
- // 0 0
- // 1 1
- // 2 2
- // 3 14 device
- // 4 15 device
- // 5 16 device
- // 6 1E device,performance counter, powerfail
- // 7 1F
- //
-
- ldah r1, 0x1f1E(r31) // Create upper lw of int_mask
- lda r1, 0x1615(r1)
-
- sll r1, 32, r1
- ldah r1, 0x1402(r1) // Create lower lw of int_mask
-
- lda r1, 0x0100(r1)
- mtpr r1, pt_intmask // Stash in PALtemp
-
- // Unlock a bunch of chip internal IPRs
- mtpr r31, exc_sum // clear out exeception summary and exc_mask
- mfpr r31, va // unlock va, mmstat
-//rig lda r8, <<1@icperr_stat$v_dpe> ! <1@icperr_stat$v_tpe> ! <1@icperr_stat$v_tmr>>(r31)
- lda r8,(BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(zero)
-
- mtpr r8, icperr_stat // Clear Icache parity error & timeout status
-//orig lda r8, <<1@dcperr_stat$v_lock> ! <1@dcperr_stat$v_seo>>(r31)
- lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
-
- mtpr r8, dcperr_stat // Clear Dcache parity error status
-
- rc r0 // clear intr_flag
- mtpr r31, pt_trap
-
- mfpr r0, pt_misc
- srl r0, pt_misc_v_switch, r1
- blbs r1, sys_reset_switch // see if we got here from swppal
-
- // Rest of the "real" reset flow
- // ASN
- mtpr r31, dtb_asn
- mtpr r31, itb_asn
-
- lda r1, 0x67(r31)
- sll r1, hwint_clr_v_pc0c, r1
- mtpr r1, hwint_clr // Clear hardware interrupt requests
-
- lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error
- mfpr r0, pt1 // get whami
- insbl r0, 1, r0 // isolate whami in correct pt_misc position
- or r0, r1, r1 // combine whami and mces
- mtpr r1, pt_misc // store whami and mces, swap bit clear
-
- zapnot r3, 1, r0 // isolate halt code
- mtpr r0, pt0 // save entry type
-
- // Cycle counter
- or r31, 1, r9 // get a one
- sll r9, 32, r9 // shift to <32>
- mtpr r31, cc // clear Cycle Counter
- mtpr r9, cc_ctl // clear and enable the Cycle Counter
- mtpr r31, pt_scc // clear System Cycle Counter
-
-
- // Misc PALtemps
- mtpr r31, maf_mode // no mbox instructions for 3 cycles
- or r31, 1, r1 // get bogus scbb value
- mtpr r1, pt_scbb // load scbb
- mtpr r31, pt_prbr // clear out prbr
-#ifdef SIMOS
- // yes, this is ugly, but you figure out a better
- // way to get the address of the kludge_initial_pcbb
- // in r1 with an uncooperative assembler --ali
- br r1, kludge_getpcb_addr
- br r31, kludge_initial_pcbb
-kludge_getpcb_addr:
- ldqp r19, 0(r1)
- sll r19, 44, r19
- srl r19, 44, r19
- mulq r19,4,r19
- addq r19, r1, r1
- addq r1,4,r1
-// or zero,kludge_initial_pcbb,r1
-// GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
-#else
- mfpr r1, pal_base
-//orig sget_addr r1, (kludge_initial_pcbb-pal$base), r1, verify=0// get address for temp pcbb
- GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
-#endif
- mtpr r1, pt_pcbb // load pcbb
- lda r1, 2(r31) // get a two
- sll r1, 32, r1 // gen up upper bits
- mtpr r1, mvptbr
- mtpr r1, ivptbr
- mtpr r31, pt_ptbr
- // Performance counters
- mtpr r31, pmctr
-
-#if init_cbox != 0
-// .if ne init_cbox
- // Only init the Scache and the Bcache if there have been no previous
- // cacheable dstream loads or stores.
- //
- // Inputs:
- // r5 - sc_ctl
- // r6 - bc_ctl
- // r7 - bc_cnfg
-
- ldah r0, 0xfff0(r31)
- zap r0, 0xE0, r0 // Get Cbox IPR base
- ldqp r19, ev5__sc_ctl(r0) // read current sc_ctl
-temp = <<<1@bc_ctl$v_ei_dis_err> + <1@bc_ctl$v_ei_ecc_or_parity> + <1@bc_ctl$v_corr_fill_dat>>@-1>
- lda r20, temp(r31) // create default bc_ctl (bc disabled, errors disabled, ecc mode)
- sll r20, 1, r20
-temp = 0x017441 // default bc_config
- get_addr r21, temp, r31 // create default bc_config
- lda r23, <1@sc_ctl_v_sc_flush>(r31) //set flag to invalidate scache in set_sc_bc_ctl
-
-// XXX bugnion pvc$jsr scbcctl, bsr=1
- bsr r10, set_sc_bc_ctl
- update_bc_ctl_shadow r6, r23 // update bc_ctl shadow using r6 as input// r23 gets adjusted impure pointer
- store_reg1 bc_config, r7, r23, ipr=1 // update bc_config shadow in impure area
-// .endc
-#endif
- // Clear pmctr_ctl in impure area
-
-#ifndef SIMOS
- // can't assemble ???
- update_pmctr_ctl r31, r1 // clear pmctr_ctl // r1 trashed
-#endif
-
- ldah r14, 0xfff0(r31)
- zap r14, 0xE0, r14 // Get Cbox IPR base
-#ifndef SIMOS
- ldqp r31, sc_stat(r14) // Clear sc_stat and sc_addr
- ldqp r31, ei_stat(r14)
- ldqp r31, ei_stat(r14) // Clear ei_stat, ei_addr, bc_tag_addr, fill_syn
-#endif
- GET_IMPURE(r13)
- stqpc r31, 0(r13) // Clear lock_flag
-
- mfpr r0, pt0 // get entry type
- br r31, sys_enter_console // enter the cosole
-
-#endif /* rax_mode == 0 */
-
-
-
-
-//.if ne rax_mode
-#if rax_mode != 0
-
- // For RAX:
- // r0 - icsr at first, then used for cbox ipr base offset
- // r2 - mcsr
- // r3 - dc_mode
- // r4 - maf_mode
- // r5 - sc_ctl
- // r6 - bc_ctl
- // r7 - bc_cnfg
- .globl sys_reset
-sys_reset:
- mtpr r31, ev5__dtb_cm // set mbox mode to kernel
- mtpr r31, ev5__ps // set Ibox mode to kernel - E1
-
- mtpr r0, ev5__icsr // Load ICSR - E1
-
- mtpr r2, ev5__mcsr
- mfpr r8, pal_base
-
- ldah r0, 0xfff0(r31)
- zap r0, 0xE0, r0 // Get Cbox IPR base
-
- mtpr r31, ev5__itb_asn // clear asn - E1
- ldqp r19, ev5__sc_ctl(r0) // read current sc_ctl
-
-temp = <<<1@bc_ctl$v_ei_dis_err> + <1@bc_ctl$v_ei_ecc_or_parity> + <1@bc_ctl$v_corr_fill_dat>>@-1>
- lda r20, temp(r31) // create default bc_ctl (bc disabled, errors disabled, ecc mode)
- sll r20, 1, r20
-
-temp = 0x017441 // default bc_config
- get_addr r21, temp, r31 // create default bc_config
- lda r23, <1@sc_ctl_v_sc_flush>(r31) //set flag to invalidate scache in set_sc_bc_ctl
-
-// XXX bugnion pvc$jsr scbcctl, bsr=1
- bsr r10, set_sc_bc_ctl
- update_bc_ctl_shadow r6, r2 // initialize bc_ctl shadow// adjusted impure pointer in r2
- store_reg1 pmctr_ctl, r31, r2, ipr=1 // clear pmctr_ctl
- store_reg1 bc_config, r7, r2, ipr=1 // initialize bc_config shadow
-
- mtpr r3, ev5__dc_mode // write dc_mode
- mtpr r31, ev5__dc_flush // flush dcache
-
- mtpr r31, ev5__exc_sum // clear exc_sum - E1
- mtpr r31, ev5__exc_mask // clear exc_mask - E1
-
- ldah r2, 4(r31) // For EXC_ADDR
- mtpr r2, ev5__exc_addr // EXC_ADDR to 40000 (hex)
-
- mtpr r31, ev5__sirr // Clear SW interrupts (for ISP)
- mtpr r4, ev5__maf_mode // write maf_mode
-
- mtpr r31, ev5__alt_mode // set alt_mode to kernel
- mtpr r31, ev5__itb_ia // clear ITB - E1
-
- lda r1, 0x1F(r31) // For IPL
- mtpr r1, ev5__ipl // IPL to 1F
-
- mtpr r31, ev5__hwint_clr // clear hardware interrupts
- mtpr r31, ev5__aster // disable AST interrupts
-
- mtpr r31, ev5__astrr // clear AST requests
- mtpr r31, ev5__dtb_ia // clear dtb
-
- nop
- mtpr r31, pt_trap
-
- srl r2, page_offset_size_bits, r9 // Start to make PTE for address 40000
- sll r9, 32, r9
-
- lda r9, 0x7F01(r9) // Make PTE, V set, all RE set, all but UWE set
- nop
-
- mtpr r9, dtb_pte // ACORE hack, load TB with 1-1 translation for address 40000
- mtpr r2, itb_tag // ACORE hack, load TB with 1-1 translation for address 40000
-
- mtpr r2, dtb_tag
- mtpr r9, itb_pte
-
- and r31, r31, r0 // clear deposited registers, note: r2 already overwritten
- and r31, r31, r3
-
- and r31, r31, r4
- and r31, r31, r5
-
- and r31, r31, r6
- and r31, r31, r7
-
- hw_rei //May need to be a rei_stall since
- //we write to TB's above
- //However, it currently works ok. (JH)
-
-
-// .endc
-#endif /*rax_mode != 0 */
-
-
- // swppal entry
- // r0 - pt_misc
- // r17 - new PC
- // r18 - new PCBB
- // r19 - new VPTB
-sys_reset_switch:
- or r31, 1, r9
- sll r9, pt_misc_v_switch, r9
- bic r0, r9, r0 // clear switch bit
- mtpr r0, pt_misc
-
- rpcc r1 // get cyccounter
-
- ldqp r22, osfpcb_q_fen(r18) // get new fen/pme
- ldlp r23, osfpcb_l_cc(r18) // get cycle counter
- ldlp r24, osfpcb_l_asn(r18) // get new asn
-
-
- ldqp r25, osfpcb_q_Mmptr(r18)// get new mmptr
- sll r25, page_offset_size_bits, r25 // convert pfn to pa
- mtpr r25, pt_ptbr // load the new mmptr
- mtpr r18, pt_pcbb // set new pcbb
-
- bic r17, 3, r17 // clean use pc
- mtpr r17, exc_addr // set new pc
- mtpr r19, mvptbr
- mtpr r19, ivptbr
-
- ldqp r30, osfpcb_q_Usp(r18) // get new usp
- mtpr r30, pt_usp // save usp
-
- sll r24, dtb_asn_v_asn, r8
- mtpr r8, dtb_asn
- sll r24, itb_asn_v_asn, r24
- mtpr r24, itb_asn
-
- mfpr r25, icsr // get current icsr
- lda r24, 1(r31)
- sll r24, icsr_v_fpe, r24 // 1 in icsr<fpe> position
- bic r25, r24, r25 // clean out old fpe
- and r22, 1, r22 // isolate new fen bit
- sll r22, icsr_v_fpe, r22
- or r22, r25, r25 // or in new fpe
- mtpr r25, icsr // update ibox ipr
-
- subl r23, r1, r1 // gen new cc offset
- insll r1, 4, r1 // << 32
- mtpr r1, cc // set new offset
-
- or r31, r31, r0 // set success
- ldqp r30, osfpcb_q_Ksp(r18) // get new ksp
- mfpr r31, pt0 // stall
- hw_rei_stall
-
-// .sbttl "SYS_MACHINE_CHECK - Machine check PAL"
- ALIGN_BLOCK
-//+
-//sys$machine_check
-// A machine_check trap has occurred. The Icache has been flushed.
-//
-//-
-
-EXPORT(sys_machine_check)
- // Need to fill up the refill buffer (32 instructions) and
- // then flush the Icache again.
- // Also, due to possible 2nd Cbox register file write for
- // uncorrectable errors, no register file read or write for 7 cycles.
-
- nop
- mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites r0 later
-
- nop
- nop
-
- nop
- nop
-
- nop
- nop
-
- nop
- nop
- // 10 instructions// 5 cycles
-
- nop
- nop
-
- nop
- nop
-
- // Register file can now be written
- lda r0, scb_v_procmchk(r31) // SCB vector
- mfpr r13, pt_mces // Get MCES
- sll r0, 16, r0 // Move SCBv to correct position
-// bis r13, #<1@mces$v_mchk>, r14 // Set MCES<MCHK> bit
- bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
-
-
- zap r14, 0x3C, r14 // Clear mchk_code word and SCBv word
- mtpr r14, pt_mces
- // 20 instructions
-
- nop
- or r14, r0, r14 // Insert new SCB vector
- lda r0, mchk_c_proc_hrd_error(r31) // MCHK code
- mfpr r12, exc_addr
-
- sll r0, 32, r0 // Move MCHK code to correct position
- mtpr r4, pt4
- or r14, r0, r14 // Insert new MCHK code
- mtpr r14, pt_misc // Store updated MCES, MCHK code, and SCBv
-
- ldah r14, 0xfff0(r31)
- mtpr r1, pt1 // Stash for scratch - 30 instructions
-
- zap r14, 0xE0, r14 // Get Cbox IPR base
- mtpr r12, pt10 // Stash exc_addr
-
-
-
- mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed.
- blbs r13, sys_double_machine_check // MCHK halt if double machine check
-
- mtpr r6, pt6
- mtpr r5, pt5
-
- // Look for the powerfail cases here....
- mfpr r4, isr
- srl r4, isr_v_pfl, r4
- blbc r4, sys_mchk_collect_iprs // skip if no powerfail interrupt pending
- lda r4, 0xffc4(r31) // get GBUS$MISCR address bits
- sll r4, 24, r4 // shift to proper position
- ldqp r4, 0(r4) // read GBUS$MISCR
- srl r4, 5, r4 // isolate bit <5>
- blbc r4, sys_mchk_collect_iprs // skip if already cleared
- // No missed CFAIL mchk
- lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits
- sll r5, 24, r5 // shift to proper position
- lda r6, 0x40(r31) // get bit <6> mask
- ldqp r4, 0(r5) // read GBUS$SERNUM
- or r4, r6, r6 // set bit <6>
- stqp r6, 0(r5) // clear GBUS$SERNUM<6>
- mb
- mb
-
-
- //+
- // Start to collect the IPRs. Common entry point for mchk flows.
- //
- // Current state:
- // pt0 - saved r0
- // pt1 - saved r1
- // pt4 - saved r4
- // pt5 - saved r5
- // pt6 - saved r6
- // pt10 - saved exc_addr
- // pt_misc<47:32> - mchk code
- // pt_misc<31:16> - scb vector
- // r14 - base of Cbox IPRs in IO space
- // r0, r1, r4, r5, r6, r12, r13, r25 - available
- // r8, r9, r10 - available as all loads are physical
- // MCES<mchk> is set
- //
- //-
-
-EXPORT(sys_mchk_collect_iprs)
- mb // MB before reading Scache IPRs
- mfpr r1, icperr_stat
-
- mfpr r8, dcperr_stat
- mtpr r31, dc_flush // Flush the Dcache
-
- mfpr r31, pt0 // Pad Mbox instructions from dc_flush
- mfpr r31, pt0
- nop
- nop
-
- ldqp r9, sc_addr(r14) // SC_ADDR IPR
- bis r9, r31, r31 // Touch ld to make sure it completes before
- // read of SC_STAT
- ldqp r10, sc_stat(r14) // SC_STAT, also unlocks SC_ADDR
-
- ldqp r12, ei_addr(r14) // EI_ADDR IPR
- ldqp r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR
- ldqp r0, fill_syn(r14) // FILL_SYN IPR
- bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT
- bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT
- ldqp r25, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
- ldqp r31, ei_stat(r14) // Read again to insure it is unlocked
-
-
-
-
- //+
- // Look for nonretryable cases
- // In this segment:
- // r5<0> = 1 means retryable
- // r4, r6, and r14 are available for scratch
- //
- //-
-
-
- bis r31, r31, r5 // Clear local retryable flag
- srl r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits to low bits
-
- lda r4, 1(r31)
- sll r4, icperr_stat_v_tmr, r4
- and r1, r4, r4 // Timeout reset
- bne r4, sys_cpu_mchk_not_retryable
-
- and r8, BIT(dcperr_stat_v_lock), r4 // DCache parity error locked
- bne r4, sys_cpu_mchk_not_retryable
-
- lda r4, 1(r31)
- sll r4, sc_stat_v_sc_scnd_err, r4
- and r10, r4, r4 // 2nd Scache error occurred
- bne r4, sys_cpu_mchk_not_retryable
-
-
- bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control
- // Parity Error, Interface Parity Error, 2nd Error
-
- and r25, r4, r4
- bne r4, sys_cpu_mchk_not_retryable
-
-// bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4
- bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
- and r25, r4, r4 // Isolate the Uncorrectable Error Bit
-// bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6
- bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit
- cmovne r6, 0, r4 // r4 = 0 if IRD or if No Uncorrectable Error
- bne r4, sys_cpu_mchk_not_retryable
-
- lda r4, 7(r31)
- and r10, r4, r4 // Isolate the Scache Tag Parity Error bits
- bne r4, sys_cpu_mchk_not_retryable // All Scache Tag PEs are not retryable
-
-
- lda r4, 0x7f8(r31)
- and r10, r4, r4 // Isolate the Scache Data Parity Error bits
- srl r10, sc_stat_v_cbox_cmd, r6
- and r6, 0x1f, r6 // Isolate Scache Command field
- subq r6, 1, r6 // Scache Iread command = 1
- cmoveq r6, 0, r4 // r4 = 0 if IRD or if No Parity Error
- bne r4, sys_cpu_mchk_not_retryable
-
- // Look for the system unretryable cases here....
-
- mfpr r4, isr // mchk_interrupt pin asserted
- srl r4, isr_v_mck, r4
- blbs r4, sys_cpu_mchk_not_retryable
-
-
-
- //+
- // Look for retryable cases
- // In this segment:
- // r5<0> = 1 means retryable
- // r6 - holds the mchk code
- // r4 and r14 are available for scratch
- //
- //-
-
-
- // Within the chip, the retryable cases are Istream errors
- lda r4, 3(r31)
- sll r4, icperr_stat_v_dpe, r4
- and r1, r4, r4
- cmovne r4, 1, r5 // Retryable if just Icache parity error
-
-
- lda r4, 0x7f8(r31)
- and r10, r4, r4 // Isolate the Scache Data Parity Error bits
- srl r10, sc_stat_v_cbox_cmd, r14
- and r14, 0x1f, r14 // Isolate Scache Command field
- subq r14, 1, r14 // Scache Iread command = 1
- cmovne r4, 1, r4 // r4 = 1 if Scache data parity error bit set
- cmovne r14, 0, r4 // r4 = 1 if Scache PE and Iread
- bis r4, r5, r5 // Accumulate
-
-
- bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
- and r25, r4, r4 // Isolate the Uncorrectable Error Bit
- and r25, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r14 // Isolate the Iread bit
- cmovne r4, 1, r4 // r4 = 1 if uncorr error
- cmoveq r14, 0, r4 // r4 = 1 if uncorr and Iread
- bis r4, r5, r5 // Accumulate
-
- mfpr r6, pt_misc
- extwl r6, 4, r6 // Fetch mchk code
- bic r6, 1, r6 // Clear flag from interrupt flow
- cmovne r5, mchk_c_retryable_ird, r6 // Set mchk code
-
-
-
- // In the system, the retryable cases are ...
- // (code here handles beh model read NXM)
-
-#if beh_model != 0
-// .if ne beh_model
- ldah r4, 0xC000(r31) // Get base of demon space
- lda r4, 0x550(r4) // Add NXM demon flag offset
-
- ldqp r4, 0(r4) // Read the demon register
- lda r14, mchk_c_read_nxm(r31)
- cmovlbs r4, r14, r6 // Set mchk code if read NXM
- cmovlbs r4, 1, r4
- bis r4, r5, r5 // Accumulate retry bit
-#endif
-
-
- //+
- // Write the logout frame
- //
- // Current state:
- // r0 - fill_syn
- // r1 - icperr_stat
- // r4 - available
- // r5<0> - retry flag
- // r6 - mchk code
- // r8 - dcperr_stat
- // r9 - sc_addr
- // r10 - sc_stat
- // r12 - ei_addr
- // r13 - bc_tag_addr
- // r14 - available
- // r25 - ei_stat (shifted)
- // pt0 - saved r0
- // pt1 - saved r1
- // pt4 - saved r4
- // pt5 - saved r5
- // pt6 - saved r6
- // pt10 - saved exc_addr
- //
- //-
-
-sys_mchk_write_logout_frame:
- // Get base of the logout area.
- GET_IMPURE(r14) // addr of per-cpu impure area
- GET_ADDR(r14,pal_logout_area+mchk_mchk_base,r14)
-
- // Write the first 2 quadwords of the logout area:
-
- sll r5, 63, r5 // Move retry flag to bit 63
- lda r4, mchk_size(r5) // Combine retry flag and frame size
- stqp r4, mchk_flag(r14) // store flag/frame size
- lda r4, mchk_sys_base(r31) // sys offset
- sll r4, 32, r4
- lda r4, mchk_cpu_base(r4) // cpu offset
- stqp r4, mchk_offsets(r14) // store sys offset/cpu offset into logout frame
-
- //+
- // Write the mchk code to the logout area
- // Write error IPRs already fetched to the logout area
- // Restore some GPRs from PALtemps
- //-
-
- mfpr r5, pt5
- stqp r6, mchk_mchk_code(r14)
- mfpr r4, pt4
- stqp r1, mchk_ic_perr_stat(r14)
- mfpr r6, pt6
- stqp r8, mchk_dc_perr_stat(r14)
- mfpr r1, pt1
- stqp r9, mchk_sc_addr(r14)
- stqp r10, mchk_sc_stat(r14)
- stqp r12, mchk_ei_addr(r14)
- stqp r13, mchk_bc_tag_addr(r14)
- stqp r0, mchk_fill_syn(r14)
- mfpr r0, pt0
- sll r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits back to expected position
- // retrieve lower 28 bits again from ei_stat and restore before storing to logout frame
- ldah r13, 0xfff0(r31)
- zapnot r13, 0x1f, r13
- ldqp r13, ei_stat(r13)
- sll r13, 64-ei_stat_v_bc_tperr, r13
- srl r13, 64-ei_stat_v_bc_tperr, r13
- or r25, r13, r25
- stqp r25, mchk_ei_stat(r14)
-
-
-
-
- //+
- // complete the CPU-specific part of the logout frame
- //-
-
-#ifndef SIMOS
- // cant' assemble.Where is the macro ?
- mchk_logout mm_stat
- mchk_logout va // Unlocks VA and MM_STAT
- mchk_logout isr
- mchk_logout icsr
- mchk_logout pal_base
- mchk_logout exc_mask
- mchk_logout exc_sum
-#endif
-
- ldah r13, 0xfff0(r31)
- zap r13, 0xE0, r13 // Get Cbox IPR base
- ldqp r13, ld_lock(r13) // Get ld_lock IPR
- stqp r13, mchk_ld_lock(r14) // and stash it in the frame
-
- //+
- // complete the PAL-specific part of the logout frame
- //-
-#ifdef vms
- t = 0
- .repeat 24
- pt_mchk_logout \t
- t = t + 1
- .endr
-#endif
-#ifndef SIMOS
- //can't assemble ?
- pt_mchk_logout 0
- pt_mchk_logout 1
- pt_mchk_logout 2
- pt_mchk_logout 3
- pt_mchk_logout 4
- pt_mchk_logout 5
- pt_mchk_logout 6
- pt_mchk_logout 7
- pt_mchk_logout 8
- pt_mchk_logout 9
- pt_mchk_logout 10
- pt_mchk_logout 11
- pt_mchk_logout 12
- pt_mchk_logout 13
- pt_mchk_logout 14
- pt_mchk_logout 15
- pt_mchk_logout 16
- pt_mchk_logout 17
- pt_mchk_logout 18
- pt_mchk_logout 19
- pt_mchk_logout 20
- pt_mchk_logout 21
- pt_mchk_logout 22
- pt_mchk_logout 23
-#endif
-
-
- //+
- // Log system specific info here
- //-
-
-#if alpha_fw != 0
-// .if ne alpha_fw
-storeTLEP_:
- lda r13, 0xffc4(r31) // Get GBUS$MISCR address
- sll r13, 24, r13
- ldqp r13, 0(r13) // Read GBUS$MISCR
- sll r13, 16, r13 // shift up to proper field
- mfpr r8, pt_whami // get our node id
- extbl r8, 1, r8 // shift to bit 0
- or r13, r8, r13 // merge MISCR and WHAMI
- stlp r13, mchk$gbus(r14) // write to logout area
- srl r8, 1, r8 // shift off cpu number
-
- Get_TLSB_Node_Address r8,r13 // compute our nodespace address
-
- OSFmchk_TLEPstore tldev, tlsb=1
- OSFmchk_TLEPstore tlber, tlsb=1, clr=1
- OSFmchk_TLEPstore tlcnr, tlsb=1
- OSFmchk_TLEPstore tlvid, tlsb=1
- OSFmchk_TLEPstore tlesr0, tlsb=1, clr=1
- OSFmchk_TLEPstore tlesr1, tlsb=1, clr=1
- OSFmchk_TLEPstore tlesr2, tlsb=1, clr=1
- OSFmchk_TLEPstore tlesr3, tlsb=1, clr=1
- OSFmchk_TLEPstore tlmodconfig
- OSFmchk_TLEPstore tlepaerr, clr=1
- OSFmchk_TLEPstore tlepderr, clr=1
- OSFmchk_TLEPstore tlepmerr, clr=1
- OSFmchk_TLEPstore tlintrmask0
- OSFmchk_TLEPstore tlintrmask1
- OSFmchk_TLEPstore tlintrsum0
- OSFmchk_TLEPstore tlintrsum1
- OSFmchk_TLEPstore tlep_vmg
-// .endc
-#endif /*alpha_fw != 0 */
- // Unlock IPRs
- lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
- mtpr r8, dcperr_stat // Clear Dcache parity error status
-
- lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31)
- mtpr r8, icperr_stat // Clear Icache parity error & timeout status
-
-1: ldqp r8, mchk_ic_perr_stat(r14) // get ICPERR_STAT value
- GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value
- and r0, r8, r0 // compare
- beq r0, 2f // check next case if nothing set
- lda r0, mchk_c_retryable_ird(r31) // set new MCHK code
- br r31, do_670 // setup new vector
-
-2: ldqp r8, mchk_dc_perr_stat(r14) // get DCPERR_STAT value
- GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value
- and r0, r8, r0 // compare
- beq r0, 3f // check next case if nothing set
- lda r0, mchk_c_dcperr(r31) // set new MCHK code
- br r31, do_670 // setup new vector
-
-3: ldqp r8, mchk_sc_stat(r14) // get SC_STAT value
- GET_ADDR(r0,0x107ff,r31) // get SC_STAT value
- and r0, r8, r0 // compare
- beq r0, 4f // check next case if nothing set
- lda r0, mchk_c_scperr(r31) // set new MCHK code
- br r31, do_670 // setup new vector
-
-4: ldqp r8, mchk_ei_stat(r14) // get EI_STAT value
- GET_ADDR(r0,0x30000000,r31) // get EI_STAT value
- and r0, r8, r0 // compare
- beq r0, 5f // check next case if nothing set
- lda r0, mchk_c_bcperr(r31) // set new MCHK code
- br r31, do_670 // setup new vector
-
-5: ldlp r8, mchk_tlber(r14) // get TLBER value
- GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value
- sll r0, 16, r0 // shift into proper position
- GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value
- or r0, r1, r0 // merge mask values
- and r0, r8, r0 // compare
- beq r0, 6f // check next case if nothing set
- GET_ADDR(r0, 0xfff0, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-6: ldlp r8, mchk_tlepaerr(r14) // get TLEPAERR value
- GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value
- and r0, r8, r0 // compare
- beq r0, 7f // check next case if nothing set
- GET_ADDR(r0, 0xfffa, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-7: ldlp r8, mchk_tlepderr(r14) // get TLEPDERR value
- GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value
- and r0, r8, r0 // compare
- beq r0, 8f // check next case if nothing set
- GET_ADDR(r0, 0xfffb, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-8: ldlp r8, mchk_tlepmerr(r14) // get TLEPMERR value
- GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value
- and r0, r8, r0 // compare
- beq r0, 9f // check next case if nothing set
- GET_ADDR(r0, 0xfffc, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-9: ldqp r8, mchk_ei_stat(r14) // get EI_STAT value
- GET_ADDR(r0,0xb,r31) // get EI_STAT mask value
- sll r0, 32, r0 // shift to upper lw
- and r0, r8, r0 // compare
- beq r0, 1f // check next case if nothing set
- GET_ADDR(r0,0xfffd,r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-1: ldlp r8, mchk_tlepaerr(r14) // get TLEPAERR value
- GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value
- and r0, r8, r0 // compare
- beq r0, cont_logout_frame // check next case if nothing set
- GET_ADDR(r0, 0xfffe, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-do_670: lda r8, scb_v_procmchk(r31) // SCB vector
- br r31, do_6x0_cont
-do_660: lda r8, scb_v_sysmchk(r31) // SCB vector
-do_6x0_cont:
- sll r8, 16, r8 // shift to proper position
- mfpr r1, pt_misc // fetch current pt_misc
- GET_ADDR(r4,0xffff, r31) // mask for vector field
- sll r4, 16, r4 // shift to proper position
- bic r1, r4, r1 // clear out old vector field
- or r1, r8, r1 // merge in new vector
- mtpr r1, pt_misc // save new vector field
- stlp r0, mchk_mchk_code(r14) // save new mchk code
-
-cont_logout_frame:
- // Restore some GPRs from PALtemps
- mfpr r0, pt0
- mfpr r1, pt1
- mfpr r4, pt4
-
- mfpr r12, pt10 // fetch original PC
- blbs r12, sys_machine_check_while_in_pal // MCHK halt if machine check in pal
-
-//XXXbugnion pvc_jsr armc, bsr=1
- bsr r12, sys_arith_and_mchk // go check for and deal with arith trap
-
- mtpr r31, exc_sum // Clear Exception Summary
-
- mfpr r25, pt10 // write exc_addr after arith_and_mchk to pickup new pc
- stqp r25, mchk_exc_addr(r14)
-
- //+
- // Set up the km trap
- //-
-
-
-sys_post_mchk_trap:
- mfpr r25, pt_misc // Check for flag from mchk interrupt
- extwl r25, 4, r25
- blbs r25, sys_mchk_stack_done // Stack from already pushed if from interrupt flow
-
- bis r14, r31, r12 // stash pointer to logout area
- mfpr r14, pt10 // get exc_addr
-
- sll r11, 63-3, r25 // get mode to msb
- bge r25, 3f
-
- mtpr r31, dtb_cm
- mtpr r31, ev5__ps
-
- mtpr r30, pt_usp // save user stack
- mfpr r30, pt_ksp
-
-3:
- lda sp, 0-osfsf_c_size(sp) // allocate stack space
- nop
-
- stq r18, osfsf_a2(sp) // a2
- stq r11, osfsf_ps(sp) // save ps
-
- stq r14, osfsf_pc(sp) // save pc
- mfpr r25, pt_entint // get the VA of the interrupt routine
-
- stq r16, osfsf_a0(sp) // a0
- lda r16, osfint_c_mchk(r31) // flag as mchk in a0
-
- stq r17, osfsf_a1(sp) // a1
- mfpr r17, pt_misc // get vector
-
- stq r29, osfsf_gp(sp) // old gp
- mtpr r25, exc_addr //
-
- or r31, 7, r11 // get new ps (km, high ipl)
- subq r31, 1, r18 // get a -1
-
- extwl r17, 2, r17 // a1 <- interrupt vector
- bis r31, ipl_machine_check, r25
-
- mtpr r25, ipl // Set internal ipl
- srl r18, 42, r18 // shift off low bits of kseg addr
-
- sll r18, 42, r18 // shift back into position
- mfpr r29, pt_kgp // get the kern r29
-
- or r12, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
- hw_rei_spe // out to interrupt dispatch routine
-
-
- //+
- // The stack is pushed. Load up a0,a1,a2 and vector via entInt
- //
- //-
- ALIGN_BRANCH
-sys_mchk_stack_done:
- lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
- lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector
-
- subq r31, 1, r18 // get a -1
- mfpr r25, pt_entInt
-
- srl r18, 42, r18 // shift off low bits of kseg addr
- mtpr r25, exc_addr // load interrupt vector
-
- sll r18, 42, r18 // shift back into position
- or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
-
- hw_rei_spe // done
-
-
- ALIGN_BRANCH
-sys_cpu_mchk_not_retryable:
- mfpr r6, pt_misc
- extwl r6, 4, r6 // Fetch mchk code
- br r31, sys_mchk_write_logout_frame //
-
-
-
-//+
-//sys$double_machine_check - a machine check was started, but MCES<MCHK> was
-// already set. We will now double machine check halt.
-//
-// pt0 - old R0
-//
-//+
-
-EXPORT(sys_double_machine_check)
-#ifndef SIMOS
- pvc$jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
-#endif
- lda r0, hlt_c_dbl_mchk(r31)
- br r31, sys_enter_console
-
-//+
-//sys$machine_check_while_in_pal - a machine check was started, exc_addr points to
-// a PAL PC. We will now machine check halt.
-//
-// pt0 - old R0
-//
-//+
-sys_machine_check_while_in_pal:
- stqp r12, mchk_exc_addr(r14) // exc_addr has not yet been written
-
-#ifndef SIMOS
- pvc$jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
-#endif
- lda r0, hlt_c_mchk_from_pal(r31)
- br r31, sys_enter_console
-
-
-//ARITH and MCHK
-// Check for arithmetic errors and build trap frame,
-// but don't post the trap.
-// on entry:
-// pt10 - exc_addr
-// r12 - return address
-// r14 - logout frame pointer
-// r13 - available
-// r8,r9,r10 - available except across stq's
-// pt0,1,6 - available
-//
-// on exit:
-// pt10 - new exc_addr
-// r17 = exc_mask
-// r16 = exc_sum
-// r14 - logout frame pointer
-//
- ALIGN_BRANCH
-sys_arith_and_mchk:
- mfpr r13, ev5__exc_sum
- srl r13, exc_sum_v_swc, r13
- bne r13, handle_arith_and_mchk
-
-// XXX bugnion pvc$jsr armc, bsr=1, dest=1
- ret r31, (r12) // return if no outstanding arithmetic error
-
-handle_arith_and_mchk:
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r14, pt0
-
- mtpr r1, pt1 // get a scratch reg
- and r11, osfps_m_mode, r1 // get mode bit
-
- bis r11, r31, r25 // save ps
- beq r1, 1f // if zero we are in kern now
-
- bis r31, r31, r25 // set the new ps
- mtpr r30, pt_usp // save user stack
-
- mfpr r30, pt_ksp // get kern stack
-1:
- mfpr r14, exc_addr // get pc into r14 in case stack writes fault
-
- lda sp, 0-osfsf_c_size(sp) // allocate stack space
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r1, pt_entArith
- stq r14, osfsf_pc(sp) // save pc
-
- stq r17, osfsf_a1(sp)
- mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
-
- stq r29, osfsf_gp(sp)
- stq r16, osfsf_a0(sp) // save regs
-
- bis r13, r31, r16 // move exc_sum to r16
- stq r18, osfsf_a2(sp)
-
- stq r11, osfsf_ps(sp) // save ps
- mfpr r29, pt_kgp // get the kern gp
-
- mfpr r14, pt0 // restore logout frame pointer from pt0
- bis r25, r31, r11 // set new ps
-
- mtpr r1, pt10 // Set new PC
- mfpr r1, pt1
-
-// XXX bugnion pvc$jsr armc, bsr=1, dest=1
- ret r31, (r12) // return if no outstanding arithmetic error
-
-
-
-// .sbttl "SYS$ENTER_CONSOLE - Common PALcode for ENTERING console"
-
- ALIGN_BLOCK
-
-// SYS$enter_console
-//
-// Entry:
-// Entered when PAL wants to enter the console.
-// usually as the result of a HALT instruction or button,
-// or catastrophic error.
-//
-// Regs on entry...
-//
-// R0 = halt code
-// pt0 <- r0
-//
-// Function:
-//
-// Save all readable machine state, and "call" the console
-//
-// Returns:
-//
-//
-// Notes:
-//
-// In these routines, once the save state routine has been executed,
-// the remainder of the registers become scratchable, as the only
-// "valid" copy of them is the "saved" copy.
-//
-// Any registers or PTs that are modified before calling the save
-// routine will have there data lost. The code below will save all
-// state, but will loose pt 0,4,5.
-//
-//-
-
-EXPORT(sys_enter_console)
- mtpr r1, pt4
- mtpr r3, pt5
-#ifdef SIMOS
- subq r31, 1, r1
- sll r1, 42, r1
- ldah r1, 1(r1)
-#else /* SIMOS */
- lda r3, pal_enter_console_ptr(r31) //find stored vector
- ldqp r1, 0(r3)
-#endif /* SIMOS */
-
-#ifdef SIMOS
- /* taken from scrmax, seems like the obvious thing to do */
- mtpr r1, exc_addr
- mfpr r1, pt4
- mfpr r3, pt5
- STALL
- STALL
- hw_rei_stall
-#else
- pvc$violate 1007
- jmp r31, (r1) // off to common routine
-#endif
-
-
-// .sbttl "SYS$EXIT_CONSOLE - Common PALcode for ENTERING console"
-//+
-// sys$exit_console
-//
-// Entry:
-// Entered when console wants to reenter PAL.
-// usually as the result of a CONTINUE.
-//
-//
-// Regs' on entry...
-//
-//
-// Function:
-//
-// Restore all readable machine state, and return to user code.
-//
-//
-//
-//-
- ALIGN_BLOCK
-sys_exit_console:
- //Disable physical mode:
-#if enable_physical_console != 0
-// .if ne enable_physical_console
- mfpr r25, pt_ptbr
- bic r25, 1, r25 // clear physical console flag
- mtpr r25, pt_ptbr
-#endif
-
- GET_IMPURE(r1)
-
- // clear lock and intr_flags prior to leaving console
- rc r31 // clear intr_flag
- // lock flag cleared by restore_state
-#ifndef SIMOS
- pvc$jsr rststa, bsr=1
- bsr r3, pal_restore_state // go restore all state
- // note, R1 and R3 are NOT restored
- // by restore_state.
-#endif
- // TB's have been flushed
-
- ldqp r3, (cns_gpr+(8*3))(r1) // restore r3
- ldqp r1, (cns_gpr+8)(r1) // restore r1
- hw_rei_stall // back to user
-
-#if turbo_pcia_intr_fix != 0
-// .if ne turbo_pcia_intr_fix
-check_pcia_intr:
- mfpr r14, pt14 // fetch saved PCIA interrupt info
- beq r14, check_done // don't bother checking if no info
- mfpr r13, ipl // check the current IPL
- bic r13, 3, r25 // isolate ipl<5:2>
- cmpeq r25, 0x14, r25 // is it an I/O interrupt?
- beq r25, check_done // no, return
- and r13, 3, r25 // get I/O interrupt index
- extbl r14, r25, r13 // extract info for this interrupt
- beq r13, check_done // if no info, return
-
- // This is an RTI from a PCIA interrupt
- lda r12, 1(r31) // get initial bit mask
- sll r12, r25, r25 // shift to select interrupt index
- zap r14, r25, r14 // clear out info from this interrupt
- mtpr r14, pt14 // and save it
-
- and r13, 3, r25 // isolate HPC field
- subq r25, 1, r25 // subtract 1 to get HPC number
- srl r13, 2, r13 // generate base register address
- sll r13, 6, r13 // get slot/hose address bits
- lda r13, 0x38(r13) // insert other high bits
- sll r13, 28, r13 // shift high bits into position
-
- // Read the IPROGx register
- sll r25, 21, r14 // HPC address bit position
- or r13, r14, r14 // add in upper bits
- lda r14, 0x400(r14) // add in lower bits
- ldqp r14, 0(r14) // read IPROG
- srl r14, 4, r12 // check the In Progress bit
- blbc r12, 1f // skip if none in progress
- and r14, 0xf, r14 // isolate interrupt source
- lda r12, 1(r31) // make initial mask
- sll r12, r14, r14 // shift to make new intr source mask
- br r31, 2f
- // Write the SMPLIRQx register
-1: or r31, r31, r14 // default interrupt source mask
-2: GET_ADDR(r12, 0xffff, r31) // default SMPLIRQx data
- bic r12, r14, r12 // clear any interrupts in progres
-//orig lda r14, <0xbffc@-2>(r31) // get register address bits
- lda r14,(0xbffc>>2)(r31)
-
- sll r14, 10, r14 // shift into position
- or r14, r13, r14 // add in upper bits
- sll r25, 8, r25 // shift HPC number into position
- or r14, r25, r14 // add in lower bits
- stqp r12, 0(r14) // write SMPLIRQx register
- mb
- ldqp r12, 0(r14) // read it back
- bis r12, r12, r12 // touch register to insure completion
-
-check_done: // do these now and return
- lda r25, osfsf_c_size(sp) // get updated sp
- bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr
- br r31, pcia_check_return
-#endif
-
-
-// .sbttl KLUDGE_INITIAL_PCBB - PCB for Boot use only
-
- ALIGN_128
-.globl kludge_initial_pcbb
-kludge_initial_pcbb: // PCB is 128 bytes long
-// .repeat 16
-// .quad 0
-// .endr
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
-// .sbttl "SET_SC_BC_CTL subroutine"
-//
-// Subroutine to set the SC_CTL, BC_CONFIG, and BC_CTL registers and flush the Scache
-// There must be no outstanding memory references -- istream or dstream -- when
-// these registers are written. EV5 prefetcher is difficult to turn off. So,
-// this routine needs to be exactly 32 instructions long// the final jmp must
-// be in the last octaword of a page (prefetcher doesn't go across page)
-//
-//
-// Register expecations:
-// r0 base address of CBOX iprs
-// r5 value to set sc_ctl to (flush bit is added in)
-// r6 value to set bc_ctl to
-// r7 value to set bc_config to
-// r10 return address
-// r19 old sc_ctl value
-// r20 old value of bc_ctl
-// r21 old value of bc_config
-// r23 flush scache flag
-// Register usage:
-// r17 sc_ctl with flush bit cleared
-// r22 loop address
-//
-//
-#ifndef SIMOS
- align_page <32*4> // puts start of routine at next page boundary minus 32 longwords.
-#endif
-
-set_sc_bc_ctl:
-
-#ifndef SIMOS
- br r22, sc_ctl_loop //this branch must be in the same 4 instruction block as it's dest
-sc_ctl_loop:
-// XXX bugnion pvc$jsr scloop, dest=1
- mb
- mb
-
- bis r5, r23, r5 //r5 <- same sc_ctl with flush bit set (if flag set in r23)
-
- stqp r19, ev5__sc_ctl(r0) // write sc_ctl
- stqp r20, ev5__bc_ctl(r0) // write bc_ctl
- bis r31, r6, r20 // update r20 with new bc_ctl for 2nd time through loop
- stqp r21, bc_config(r0) // write bc_config register
- bis r31, r7, r21 // update r21 with new bc_config for 2nd time through loop
-
- bic r19, BIT(sc_ctl_v_sc_flush), r17 //r17 <- same sc_ctl without flush bit set
- //NOTE: only works because flush bit is in lower 16 bits
-
- wmb // don't merge with other writes
- stqp r17, ev5__sc_ctl(r0) // write sc_ctl without flush bit
- ldqp r17, ev5__sc_ctl(r0) // read sc_ctl
- bis r17, r17, r17 // stall until the data comes back
- bis r31, r5, r19 // update r19 with new sc_ctl for 2nd time through loop
-
- // fill with requisite number of nops (unops ok) to make exactly 32 instructions in loop
- t = 0
- .repeat 15
- unop
- t = t + 1
- .endr
- $opdef mnemonic= myjmp, -
- format= <custom=iregister, iregister, branch_offset>, -
- encoding= <26:31=0x1A, 21:25=%OP1,16:20=%OP2,14:15=0x00,0:13=%op3>
-
-// XXXbugnion pvc$jsr scloop
- myjmp r22,r22,sc_ctl_loop // first time, jump to sc_ctl_loop (hint will cause prefetcher to go to loop instead
- // of straight) // r22 gets sc_ctl_done
- // 2nd time, code continues at sc_ctl_done (I hope)
-sc_ctl_done:
-// XXX bugnion pvc$jsr scloop, dest=1
-// XXX bugnion pvc$jsr scbcctl
-#endif /*SIMOS*/
- ret r31, (r10) // return to where we came from
-
-
-.end
-
-
-
-
+++ /dev/null
-/*
- * Copyright (c) 2003, 2004, 2005
- * The Regents of The University of Michigan
- * All Rights Reserved
- *
- * This code is part of the M5 simulator, developed by Nathan Binkert,
- * Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions
- * from Ron Dreslinski, Dave Greene, Lisa Hsu, Ali Saidi, and Andrew
- * Schultz.
- *
- * Permission is granted to use, copy, create derivative works and
- * redistribute this software and such derivative works for any
- * purpose, so long as the copyright notice above, this grant of
- * permission, and the disclaimer below appear in all copies made; and
- * so long as the name of The University of Michigan is not used in
- * any advertising or publicity pertaining to the use or distribution
- * of this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
- * UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND
- * WITHOUT WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER
- * EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE. THE REGENTS OF THE UNIVERSITY OF MICHIGAN SHALL NOT BE
- * LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, SPECIAL, INDIRECT,
- * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, WITH RESPECT TO ANY CLAIM
- * ARISING OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE, EVEN
- * IF IT HAS BEEN OR IS HEREAFTER ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGES.
- */
-
-/*
-Copyright 1993 Hewlett-Packard Development Company, L.P.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
-of the Software, and to permit persons to whom the Software is furnished to do
-so, subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-SOFTWARE.
-*/
-
-// build_fixed_image: not sure what means
-// real_mm to be replaced during rewrite
-// remove_save_state remove_restore_state can be remooved to save space ??
-
-
-#define egore 0
-#define acore 0
-#define beh_model 0
-#define ev5_p2 1
-#define ev5_p1 0
-#define ldvpte_bug_fix 1
-#define spe_fix 0
-#define osf_chm_fix 0
-#define build_fixed_image 0
-#define enable_p4_fixups 0
-#define osf_svmin 1
-#define enable_physical_console 0
-#define fill_err_hack 0
-#define icflush_on_tbix 0
-#define max_cpuid 1
-#define perfmon_debug 0
-#define rax_mode 0
-
-#define hw_rei_spe hw_rei
-
-#include "ev5_defs.h"
-#include "ev5_impure.h"
-#include "ev5_alpha_defs.h"
-#include "ev5_paldef.h"
-#include "ev5_osfalpha_defs.h"
-#include "fromHudsonMacros.h"
-#include "fromHudsonOsf.h"
-#include "dc21164FromGasSources.h"
-#include "cserve.h"
-#include "tlaser.h"
-
-#define ldlp ldl_p
-#define ldqp ldq_p
-
-#define stlp stl_p
-#define stqp stq_p
-#define stqpc stqp
-
-#ifdef SIMOS
-#define ldqpl ldq_p
-#define sdqpl sdq_p
-#else
-<--bomb>
-#endif
-
-#define pt_entInt pt_entint
-#define pt_entArith pt_entarith
-#define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8)
-#define mchk_flag CNS_Q_FLAG
-#define mchk_sys_base 56
-#define mchk_cpu_base (CNS_Q_LD_LOCK + 8)
-#define mchk_offsets CNS_Q_EXC_ADDR
-#define mchk_mchk_code 8
-#define mchk_ic_perr_stat CNS_Q_ICPERR_STAT
-#define mchk_dc_perr_stat CNS_Q_DCPERR_STAT
-#define mchk_sc_addr CNS_Q_SC_ADDR
-#define mchk_sc_stat CNS_Q_SC_STAT
-#define mchk_ei_addr CNS_Q_EI_ADDR
-#define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR
-#define mchk_fill_syn CNS_Q_FILL_SYN
-#define mchk_ei_stat CNS_Q_EI_STAT
-#define mchk_exc_addr CNS_Q_EXC_ADDR
-#define mchk_ld_lock CNS_Q_LD_LOCK
-#define osfpcb_q_Ksp pcb_q_ksp
-#define pal_impure_common_size ((0x200 + 7) & 0xfff8)
-
-#define ALIGN_BLOCK \
- .align 5
-
-#define ALIGN_BRANCH \
- .align 3
-
-#define EXPORT(_x) \
- .align 5; \
- .globl _x; \
-_x:
-
-// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-// XXX the following is 'made up'
-// XXX bugnion
-
-// XXX bugnion not sure how to align 'quad'
-#define ALIGN_QUAD \
- .align 3
-
-#define ALIGN_128 \
- .align 7
-
-
-#define GET_IMPURE(_r) mfpr _r,pt_impure
-#define GET_ADDR(_r1,_off,_r2) lda _r1,_off(_r2)
-
-
-#define BIT(_x) (1<<(_x))
-
-
-// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-// XXX back to original code
-
-// .sbttl "System specific code - beh model version"
-
-//
-// Entry points
-// SYS$CFLUSH - Cache flush
-// SYS$CSERVE - Console service
-// SYS$WRIPIR - interprocessor interrupts
-// SYS$HALT_INTERRUPT - Halt interrupt
-// SYS$PASSIVE_RELEASE - Interrupt, passive release
-// SYS$INTERRUPT - Interrupt
-// SYS$RESET - Reset
-// SYS$ENTER_CONSOLE
-
-//
-// Macro to read TLINTRSUMx
-//
-// Based on the CPU_NUMBER, read either the TLINTRSUM0 or TLINTRSUM1 register
-//
-// Assumed register usage:
-// rsum TLINTRSUMx contents
-// raddr node space address
-// scratch scratch register
-
-
-// .macro Read_TLINTRSUMx rsum, raddr, scratch, ?label1, ?label2
-//
-// nop
-// mfpr 'scratch', pt_whami // Get our whami (VID)
-//
-// extbl 'scratch', #1, 'scratch' // shift down to bit 0
-// lda 'raddr', ^xff88(r31) // Get base node space address bits
-//
-// sll 'raddr', #24, 'raddr' // Shift up to proper position
-// srl 'scratch', #1, 'rsum' // Shift off the cpu number
-//
-// sll 'rsum', #22, 'rsum' // Get our node offset
-// addq 'raddr', 'rsum', 'raddr' // Get our base node space address
-//
-// blbs 'scratch', label1
-// lda 'raddr', <tlep$tlintrsum0_offset>('raddr')
-//
-// br r31, label2
-//label1: lda 'raddr', <tlep$tlintrsum1_offset>('raddr')
-//
-//label2: ldlp 'rsum', 0('raddr') // read the right tlintrsum reg
-//.endm
-
-#define Read_TLINTRSUMx(_rsum,_raddr,_scratch) \
- nop; \
- mfpr _scratch,pt_whami; \
- extbl _scratch,1,_scratch; \
- lda _raddr,0xff88(zero); \
- sll _raddr,24,_raddr; \
- srl _scratch,1,_rsum; \
- sll _rsum,22,_rsum; \
- addq _raddr,_rsum,_raddr; \
- blbs _scratch,1f; \
- lda _raddr,0x1180(_raddr); \
- br r31,2f; \
-1: \
- lda _raddr,0x11c0(_raddr); \
-2: ldlp _rsum,0(_raddr)
-
-
-
-//
-// Macro to write TLINTRSUMx
-//
-// Based on the CPU_NUMBER, write either the TLINTRSUM0 or TLINTRSUM1 register
-//
-// Assumed register usage:
-// rsum TLINTRSUMx write data
-// raddr node space address
-// scratch scratch register
-
-// .macro Write_TLINTRSUMx rsum, raddr, whami, ?label1, ?label2
-//
-// nop
-// mfpr 'whami', pt_whami // Get our whami (VID)
-//
-// extbl 'whami', #1, 'whami' // shift down to bit 0
-// lda 'raddr', ^xff88(r31) // Get base node space address bits
-//
-// sll 'raddr', #24, 'raddr' // Shift up to proper position
-// blbs 'whami', label1
-//
-// lda 'raddr', <tlep$tlintrsum0_offset>('raddr')
-// br r31, label2
-//
-// label1: lda 'raddr', <tlep$tlintrsum1_offset>('raddr')
-// label2: srl 'whami', #1, 'whami' // Shift off the cpu number
-//
-// sll 'whami', #22, 'whami' // Get our node offset
-// addq 'raddr', 'whami', 'raddr' // Get our base node space address
-//
-// mb
-// stqp 'rsum', 0('raddr') // write the right tlintrsum reg
-// mb
-// ldqp 'rsum', 0('raddr') // dummy read to tlintrsum
-// bis 'rsum', 'rsum', 'rsum' // needed to complete the ldqp above -jpo
-// .endm
-
-
-#define Write_TLINTRSUMx(_rsum,_raddr,_whami) \
- nop; \
- mfpr _whami,pt_whami; \
- extbl _whami,1,_whami; \
- lda _raddr,0xff88(zero); \
- sll _raddr,24,_raddr; \
- blbs _whami,1f; \
- lda _raddr,0x1180(_raddr);\
- br zero,2f; \
-1: lda _raddr,0x11c0(_raddr);\
-2: srl _whami,1,_whami; \
- addq _raddr,_whami,_raddr; \
- mb; \
- stqp _rsum,0(_raddr); \
- ldqp _rsum,0(_raddr); \
- bis _rsum,_rsum,_rsum
-
-
-//
-// Macro to determine highest priority TIOP Node ID from interrupt pending mask
-//
-// Assumed register usage:
-// rmask - TLINTRSUMx contents, shifted to isolate IOx bits
-// rid - TLSB Node ID of highest TIOP
-
-//.macro Intr_Find_TIOP rmask, rid, ?l1, ?l2, ?l3, ?l4, ?l5, ?l6
-// srl 'rmask', #4, 'rid' // check IOP8
-// blbc 'rid', l1 // not IOP8
-//
-// lda 'rid', 8(r31) // IOP8
-// br r31, l6
-//
-// l1: srl 'rmask', #3, 'rid' // check IOP7
-// blbc 'rid', l2 // not IOP7
-//
-// lda 'rid', 7(r31) // IOP7
-// br r31, l6
-//
-// l2: srl 'rmask', #2, 'rid' // check IOP6
-// blbc 'rid', l3 // not IOP6
-//
-// lda 'rid', 6(r31) // IOP6
-// br r31, l6
-//
-// l3: srl 'rmask', #1, 'rid' // check IOP5
-// blbc 'rid', l4 // not IOP5
-//
-// lda 'rid', 5(r31) // IOP5
-// br r31, l6
-//
-// l4: srl 'rmask', #0, 'rid' // check IOP4
-// blbc 'rid', l5 // not IOP4
-//
-// lda r14, 4(r31) // IOP4
-// br r31, l6
-//
-// l5: lda r14, 0(r31) // passive release
-// l6:
-// .endm
-
-
-#define Intr_Find_TIOP(_rmask,_rid) \
- srl _rmask,3,_rid; \
- blbc _rid,1f; \
- lda _rid,8(zero); \
- br zero,6f; \
-1: srl _rmask,3,_rid; \
- blbc _rid, 2f; \
- lda _rid, 7(r31); \
- br r31, 6f; \
-2: srl _rmask, 2, _rid; \
- blbc _rid, 3f; \
- lda _rid, 6(r31); \
- br r31, 6f; \
-3: srl _rmask, 1, _rid; \
- blbc _rid, 4f; \
- lda _rid, 5(r31); \
- br r31, 6f; \
-4: srl _rmask, 0, _rid; \
- blbc _rid, 5f; \
- lda r14, 4(r31); \
- br r31, 6f; \
-5: lda r14, 0(r31); \
-6:
-
-
-
-
-//
-// Macro to calculate base node space address for given node id
-//
-// Assumed register usage:
-// rid - TLSB node id
-// raddr - base node space address
-
-//.macro Get_TLSB_Node_Address rid, raddr
-// sll 'rid', #22, 'rid' // Get offset of IOP node
-// lda 'raddr', ^xff88(r31) // Get base node space address bits
-//
-// sll 'raddr', #24, 'raddr' // Shift up to proper position
-// addq 'raddr', 'rid', 'raddr' // Get TIOP node space address
-// .iif ne turbo_pcia_intr_fix, srl 'rid', #22, 'rid' // Restore IOP node id
-//.endm
-
-
-#define turbo_pcia_intr_fix 0
-
-
-#if turbo_pcia_intr_fix != 0
-#define Get_TLSB_Node_Address(_rid,_raddr) \
- sll _rid,22,_rid; \
- lda _raddr,0xff88(zero); \
- sll _raddr,24,_raddr; \
- addq _raddr,_rid,_raddr; \
- srl _rid,22,_rid
-#else
-#define Get_TLSB_Node_Address(_rid,_raddr) \
- sll _rid,22,_rid; \
- lda _raddr,0xff88(zero); \
- sll _raddr,24,_raddr; \
- addq _raddr,_rid,_raddr
-#endif
-
-
-
-
-
-// .macro mchk$TLEPstore rlog, rs, rs1, nodebase, tlepreg, clr, tlsb, crd
-// .iif eq tlsb, lda 'rs1',<tlep$'tlepreg'_offset>(r31)
-// .iif ne tlsb, lda 'rs1',<tlsb$'tlepreg'_offset>(r31)
-// or 'rs1', 'nodebase', 'rs1'
-// ldlp 'rs', 0('rs1')
-// .iif eq crd, stlp 'rs', mchk$'tlepreg'('rlog') // store in frame
-// .iif ne crd, stlp 'rs', mchk$crd_'tlepreg'('rlog') // store in frame
-// .iif ne clr, stlp 'rs',0('rs1') // optional write to clear
-// .endm
-
-
-// .macro OSFmchk$TLEPstore tlepreg, clr=0, tlsb=0
-// mchk$TLEPstore r14, r8, r4, r13, <tlepreg>, <clr>, <tlsb>, crd=0
-// .endm
-
-#define CONCAT(_a,_b) _a ## _b
-
-#define OSFmchk_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
- lda _rs1,CONCAT(tlep_,_tlepreg)(zero); \
- or _rs1,_nodebase,_rs1; \
- ldlp _rs1,0(_rs1); \
- stlp _rs,CONCAT(mchk_,_tlepreg)(_rlog)
-
-
-#define OSFmchk_TLEPstore(_tlepreg) OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
-
-
-// .macro OSFcrd$TLEPstore tlepreg, clr=0, tlsb=0
-// mchk$TLEPstore r14, r10, r1, r0, <tlepreg>, <clr>, <tlsb>, crd=1
-// .endm
-
-#define OSFcrd_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
- lda _rs1,CONCAT(tlep_,_tlepreg)(zero); \
- or _rs1,_nodebase,_rs1; \
- ldlp _rs1,0(_rs1); \
- stlp _rs,CONCAT(mchk_crd_,_tlepreg)(_rlog)
-
-#define OSFcrd_TLEPstore_tlsb_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
- lda _rs1,CONCAT(tlsb_,_tlepreg)(zero); \
- or _rs1,_nodebase,_rs1; \
- ldlp _rs1,0(_rs1); \
- stlp _rs,CONCAT(mchk_crd_,_tlepreg)(_rlog)
-
-#define OSFcrd_TLEPstore_tlsb_clr_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
- lda _rs1,CONCAT(tlsb_,_tlepreg)(zero); \
- or _rs1,_nodebase,_rs1; \
- ldlp _rs1,0(_rs1); \
- stlp _rs,CONCAT(mchk_crd_,_tlepreg)(_rlog); \
- stlp _rs,0(_rs1)
-
-
-#define OSFcrd_TLEPstore(_tlepreg) OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
-#define OSFcrd_TLEPstore_tlsb(_tlepreg) OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg)
-#define OSFcrd_TLEPstore_tlsb_clr(_tlepreg) OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg)
-
-
-
-
-// .macro save_pcia_intr irq
-// and r13, #^xf, r25 // isolate low 4 bits
-// addq r14, #4, r14 // format the TIOP Node id field
-// sll r14, #4, r14 // shift the TIOP Node id
-// or r14, r25, r10 // merge Node id/hose/HPC
-// mfpr r14, pt14 // get saved value
-// extbl r14, #'irq', r25 // confirm none outstanding
-// bne r25, sys$machine_check_while_in_pal
-// insbl r10, #'irq', r10 // align new info
-// or r14, r10, r14 // merge info
-// mtpr r14, pt14 // save it
-// bic r13, #^xf, r13 // clear low 4 bits of vector
-// .endm
-
-#define save_pcia_intr(_irq) \
- and r13, 0xf, r25; \
- addq r14, 4, r14; \
- sll r14, 4, r14; \
- or r14, r25, r10; \
- mfpr r14, pt14; \
- extbl r14, _irq, r25; \
- bne r25, sys_machine_check_while_in_pal; \
- insbl r10, _irq, r10; \
- or r14, r10, r14; \
- mtpr r14, pt14; \
- bic r13, 0xf, r13
-
-
-
- ALIGN_BLOCK
-
-// .sbttl "wripir - PALcode for wripir instruction"
-//orig SYS$WRIPIR: // R16 has the processor number.
-
-EXPORT(sys_wripir)
-
-//++
-// Convert the processor number to a CPU mask
-//--
-
- and r16,0xf, r14 // mask the top stuff (16 CPUs supported)
- bis r31,0x1,r16 // get a one
- sll r16,r14,r14 // shift the bit to the right place
-
-//++
-// Build the Broadcast Space base address
-//--
- lda r13,0xff8e(r31) // Load the upper address bits
- sll r13,24,r13 // shift them to the top
-
-//++
-// Send out the IP Intr
-//--
- stqp r14, 0x40(r13) // Write to TLIPINTR reg WAS TLSB_TLIPINTR_OFFSET
- wmb // Push out the store
-
- hw_rei
-
-
- ALIGN_BLOCK
-// .sbttl "CFLUSH- PALcode for CFLUSH instruction"
-//+
-// SYS$CFLUSH
-// Entry:
-//
-// R16 - contains the PFN of the page to be flushed
-//
-// Function:
-// Flush all Dstream caches of 1 entire page
-//
-//-
-
-EXPORT(sys_cflush)
-
-// #convert pfn to addr, and clean off <63:20>
-// #sll r16, <page_offset_size_bits>+<63-20>>, r12
- sll r16, page_offset_size_bits+(63-20),r12
-
-// #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16>
-// # stolen from srcmax code. XXX bugnion
- lda r13, 0x10(r31) // assume 16Mbytes of cache
- sll r13, 20, r13 // convert to bytes
-
-
- srl r12, 63-20, r12 // shift back to normal position
- xor r12, r13, r12 // xor addr<18>
-
- or r31, 8192/(32*8), r13 // get count of loads
- nop
-
-cflush_loop:
- subq r13, 1, r13 // decr counter
- mfpr r25, ev5__intid // Fetch level of interruptor
-
- ldqp r31, 32*0(r12) // do a load
- ldqp r31, 32*1(r12) // do next load
-
- ldqp r31, 32*2(r12) // do next load
- ldqp r31, 32*3(r12) // do next load
-
- ldqp r31, 32*4(r12) // do next load
- ldqp r31, 32*5(r12) // do next load
-
- ldqp r31, 32*6(r12) // do next load
- ldqp r31, 32*7(r12) // do next load
-
- mfpr r14, ev5__ipl // Fetch current level
- lda r12, (32*8)(r12) // skip to next cache block addr
-
- cmple r25, r14, r25 // R25 = 1 if intid .less than or eql ipl
- beq r25, 1f // if any int's pending, re-queue CFLUSH -- need to check for hlt interrupt???
-
- bne r13, cflush_loop // loop till done
- hw_rei // back to user
-
- ALIGN_BRANCH
-1: // Here if interrupted
- mfpr r12, exc_addr
- subq r12, 4, r12 // Backup PC to point to CFLUSH
-
- mtpr r12, exc_addr
- nop
-
- mfpr r31, pt0 // Pad exc_addr write
- hw_rei
-
-
- ALIGN_BLOCK
-// .sbttl "CSERVE- PALcode for CSERVE instruction"
-//+
-// SYS$CSERVE
-//
-// Function:
-// Various functions for private use of console software
-//
-// option selector in r0
-// arguments in r16....
-//
-//
-// r0 = 0 unknown
-//
-// r0 = 1 ldqp
-// r0 = 2 stqp
-// args, are as for normal STQP/LDQP in VMS PAL
-//
-// r0 = 3 dump_tb's
-// r16 = detination PA to dump tb's to.
-//
-// r0<0> = 1, success
-// r0<0> = 0, failure, or option not supported
-// r0<63:1> = (generally 0, but may be function dependent)
-// r0 - load data on ldqp
-//
-//-
-EXPORT(sys_cserve)
-
-#ifdef SIMOS
- /* taken from scrmax */
- cmpeq r18, CSERVE_K_RD_IMPURE, r0
- bne r0, Sys_Cserve_Rd_Impure
-
- cmpeq r18, CSERVE_K_JTOPAL, r0
- bne r0, Sys_Cserve_Jtopal
- call_pal 0
-
- or r31, r31, r0
- hw_rei // and back we go
-
-Sys_Cserve_Rd_Impure:
- mfpr r0, pt_impure // Get base of impure scratch area.
- hw_rei
-
- ALIGN_BRANCH
-
-Sys_Cserve_Jtopal:
- bic a0, 3, t8 // Clear out low 2 bits of address
- bis t8, 1, t8 // Or in PAL mode bit
- mtpr t8,exc_addr
- hw_rei
-
-
-#else /* SIMOS */
-
- cmpeq r16, cserve_ldlp, r12 // check for ldqp
- bne r12, 1f // br if
-
- cmpeq r16, cserve_stlp, r12 // check for stqp
- bne r12, 2f // br if
-
- cmpeq r16, cserve_callback, r12 // check for callback entry
- bne r12, csrv_callback // br if
-
- cmpeq r16, cserve_identify, r12 // check for callback entry
- bne r12, csrv_identify // br if
-
- or r31, r31, r0 // set failure
- nop // pad palshadow write
-
- hw_rei // and back we go
-#endif /* SIMOS */
-
-// ldqp
- ALIGN_QUAD
-1:
- ldqp r0,0(r17) // get the data
- nop // pad palshadow write
-
- hw_rei // and back we go
-
-
-// stqp
- ALIGN_QUAD
-2:
- stqp r18, 0(r17) // store the data
-#ifdef SIMOS
- lda r0,17(r31) // bogus
-#else
- lda r0, CSERVE_SUCCESS(r31) // set success
-#endif
- hw_rei // and back we go
-
-
- ALIGN_QUAD
-csrv_callback:
- ldq r16, 0(r17) // restore r16
- ldq r17, 8(r17) // restore r17
- lda r0, hlt_c_callback(r31)
- br r31, sys_enter_console
-
-
-csrv_identify:
- mfpr r0, pal_base
- ldqp r0, 8(r0)
- hw_rei
-
-
-// dump tb's
- ALIGN_QUAD
-0:
- // DTB PTEs - 64 entries
- addq r31, 64, r0 // initialize loop counter
- nop
-
-1: mfpr r12, ev5__dtb_pte_temp // read out next pte to temp
- mfpr r12, ev5__dtb_pte // read out next pte to reg file
-
- subq r0, 1, r0 // decrement loop counter
- nop // Pad - no Mbox instr in cycle after mfpr
-
- stqp r12, 0(r16) // store out PTE
- addq r16, 8 ,r16 // increment pointer
-
- bne r0, 1b
-
- ALIGN_BRANCH
- // ITB PTEs - 48 entries
- addq r31, 48, r0 // initialize loop counter
- nop
-
-2: mfpr r12, ev5__itb_pte_temp // read out next pte to temp
- mfpr r12, ev5__itb_pte // read out next pte to reg file
-
- subq r0, 1, r0 // decrement loop counter
- nop //
-
- stqp r12, 0(r16) // store out PTE
- addq r16, 8 ,r16 // increment pointer
-
- bne r0, 2b
- or r31, 1, r0 // set success
-
- hw_rei // and back we go
-
-
-// .sbttl "SYS$INTERRUPT - Interrupt processing code"
-
-//+
-// SYS$INTERRUPT
-//
-// Current state:
-// Stack is pushed
-// ps, sp and gp are updated
-// r12, r14 - available
-// r13 - INTID (new EV5 IPL)
-// r25 - ISR
-// r16, r17, r18 - available
-//
-//-
-
-
-EXPORT(sys_interrupt)
- cmpeq r13, 31, r12
- bne r12, sys_int_mchk_or_crd // Check for level 31 interrupt (machine check or crd)
-
- cmpeq r13, 30, r12
- bne r12, sys_int_powerfail // Check for level 30 interrupt (powerfail)
-
- cmpeq r13, 29, r12
- bne r12, sys_int_perf_cnt // Check for level 29 interrupt (performance counters)
-
- cmpeq r13, 23, r12
- bne r12, sys_int_23 // Check for level 23 interrupt
-
- cmpeq r13, 22, r12
- bne r12, sys_int_22 // Check for level 22 interrupt (might be
- // interprocessor or timer interrupt)
-
- cmpeq r13, 21, r12
- bne r12, sys_int_21 // Check for level 21 interrupt
-
- cmpeq r13, 20, r12
- bne r12, sys_int_20 // Check for level 20 interrupt (might be corrected
- // system error interrupt)
-
- mfpr r14, exc_addr // ooops, something is wrong
- br r31, pal_pal_bug_check_from_int
-
-
-
-
-//+
-//sys$int_2*
-// Routines to handle device interrupts at IPL 23-20.
-// System specific method to ack/clear the interrupt, detect passive release,
-// detect interprocessor (22), interval clock (22), corrected
-// system error (20)
-//
-// Current state:
-// Stack is pushed
-// ps, sp and gp are updated
-// r12, r14 - available
-// r13 - INTID (new EV5 IPL)
-// r25 - ISR
-//
-// On exit:
-// Interrupt has been ack'd/cleared
-// a0/r16 - signals IO device interrupt
-// a1/r17 - contains interrupt vector
-// exit to ent_int address
-//
-//-
- ALIGN_BRANCH
-sys_int_23:
- Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
- srl r13, 22, r13 // shift down to examine IPL17
-
- Intr_Find_TIOP(r13,r14)
- beq r14, 1f
-
- Get_TLSB_Node_Address(r14,r10)
- lda r10, 0xac0(r10) // Get base TLILID address
-
- ldlp r13, 0(r10) // Read the TLILID register
- bne r13, pal_post_dev_interrupt
-
-1: lda r16, osfint_c_passrel(r31) // passive release
- br r31, pal_post_interrupt //
-
-
- ALIGN_BRANCH
-sys_int_22:
- Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
- srl r13, 6, r14 // check the Intim bit
-
- blbs r14, tlep_intim // go service Intim
- srl r13, 5, r14 // check the IP Int bit
-
- blbs r14, tlep_ipint // go service IP Int
- srl r13, 17, r13 // shift down to examine IPL16
-
- Intr_Find_TIOP(r13,r14)
- beq r14, 1f
-
- Get_TLSB_Node_Address(r14,r10)
- lda r10, 0xa80(r10) // Get base TLILID address
-
- ldlp r13, 0(r10) // Read the TLILID register
-#if turbo_pcia_intr_fix == 0
-// .if eq turbo_pcia_intr_fix
- bne r13, pal_post_dev_interrupt
-//orig .iff
- beq r13, 1f
-
- and r13, 0x3, r10 // check for PCIA bits
- beq r10, pal_post_dev_interrupt // done if nothing set
- save_pcia_intr(2)
- br r31, pal_post_dev_interrupt //
-// .endc
-#endif /* turbo_pcia_intr_fix == 0 */
-
-1: lda r16, osfint_c_passrel(r31) // passive release
- br r31, pal_post_interrupt //
-
-
- ALIGN_BRANCH
-sys_int_21:
- Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
- srl r13, 12, r13 // shift down to examine IPL15
-
- Intr_Find_TIOP(r13,r14)
- beq r14, 1f
-
- Get_TLSB_Node_Address(r14,r10)
- lda r10, 0xa40(r10) // Get base TLILID address
-
- ldlp r13, 0(r10) // Read the TLILID register
-#if turbo_pcia_intr_fix == 0
-//orig .if eq turbo_pcia_intr_fix
- bne r13, pal_post_dev_interrupt
-//orig .iff
- beq r13, 1f
-
- and r13, 0x3, r10 // check for PCIA bits
- beq r10, pal_post_dev_interrupt // done if nothing set
- save_pcia_intr(1)
- br r31, pal_post_dev_interrupt //
-// orig .endc
-#endif /* turbo_pcia_intr_fix == 0 */
-
-1: lda r16, osfint_c_passrel(r31) // passive release
- br r31, pal_post_interrupt //
-
-
- ALIGN_BRANCH
-sys_int_20:
- lda r13, 1(r31) // Duart0 bit
- Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
-
- Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
- blbs r13, tlep_uart0 // go service UART int
-
- srl r13, 7, r13 // shift down to examine IPL14
- Intr_Find_TIOP(r13,r14)
-
- beq r14, tlep_ecc // Branch if not IPL14
- Get_TLSB_Node_Address(r14,r10)
-
- lda r10, 0xa00(r10) // Get base TLILID0 address
- ldlp r13, 0(r10) // Read the TLILID register
-
-#if turbo_pcia_intr_fix == 0
-// orig .if eq turbo_pcia_intr_fix
- bne r13, pal_post_dev_interrupt
-// orig .iff
- beq r13, 1f
-
- and r13, 0x3, r10 // check for PCIA bits
- beq r10, pal_post_dev_interrupt // done if nothing set
- save_pcia_intr(0)
- br r31, pal_post_dev_interrupt //
-// orig .endc
-#endif
-1: lda r16, osfint_c_passrel(r31) // passive release
- br r31, pal_post_interrupt //
-
-
- ALIGN_BRANCH
-tlep_intim:
- lda r13, 0xffb(r31) // get upper GBUS address bits
- sll r13, 28, r13 // shift up to top
-
- lda r13, (0x300)(r13) // full CSRC address (tlep watch csrc offset)
- ldqp r13, 0(r13) // read CSRC
-
- lda r13, 0x40(r31) // load Intim bit
- Write_TLINTRSUMx(r13,r10,r14) // clear the Intim bit
-
- lda r16, osfint_c_clk(r31) // passive release
- br r31, pal_post_interrupt // Build the stack frame
-
-
- ALIGN_BRANCH
-tlep_ipint:
- lda r13, 0x20(r31) // load IP Int bit
- Write_TLINTRSUMx(r13,r10,r14) // clear the IP Int bit
-
- lda r16, osfint_c_ip(r31) // passive release
- br r31, pal_post_interrupt // Build the stack frame
-
-
- ALIGN_BRANCH
-tlep_uart0:
- lda r13, 0xffa(r31) // get upper GBUS address bits
- sll r13, 28, r13 // shift up to top
-
- ldlp r14, 0x80(r13) // zero pointer register
- lda r14, 3(r31) // index to RR3
-
- stlp r14, 0x80(r13) // write pointer register
- mb
-
- mb
- ldlp r14, 0x80(r13) // read RR3
-
- srl r14, 5, r10 // is it Channel A RX?
- blbs r10, uart0_rx
-
- srl r14, 4, r10 // is it Channel A TX?
- blbs r10, uart0_tx
-
- srl r14, 2, r10 // is it Channel B RX?
- blbs r10, uart1_rx
-
- srl r14, 1, r10 // is it Channel B TX?
- blbs r10, uart1_tx
-
- lda r8, 0(r31) // passive release
- br r31, clear_duart0_int // clear tlintrsum and post
-
-
- ALIGN_BRANCH
-uart0_rx:
- lda r8, 0x680(r31) // UART0 RX vector
- br r31, clear_duart0_int // clear tlintrsum and post
-
-
- ALIGN_BRANCH
-uart0_tx:
- lda r14, 0x28(r31) // Reset TX Int Pending code
- mb
- stlp r14, 0x80(r13) // write Channel A WR0
- mb
-
- lda r8, 0x6c0(r31) // UART0 TX vector
- br r31, clear_duart0_int // clear tlintrsum and post
-
-
- ALIGN_BRANCH
-uart1_rx:
- lda r8, 0x690(r31) // UART1 RX vector
- br r31, clear_duart0_int // clear tlintrsum and post
-
-
- ALIGN_BRANCH
-uart1_tx:
- lda r14, 0x28(r31) // Reset TX Int Pending code
- stlp r14, 0(r13) // write Channel B WR0
-
- lda r8, 0x6d0(r31) // UART1 TX vector
- br r31, clear_duart0_int // clear tlintrsum and post
-
-
- ALIGN_BRANCH
-clear_duart0_int:
- lda r13, 1(r31) // load duart0 bit
- Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
-
- beq r8, 1f
- or r8, r31, r13 // move vector to r13
- br r31, pal_post_dev_interrupt // Build the stack frame
-1: nop
- nop
- hw_rei
-// lda r16, osfint_c_passrel(r31) // passive release
-// br r31, pal_post_interrupt //
-
-
- ALIGN_BRANCH
-tlep_ecc:
- mfpr r14, pt_whami // get our node id
- extbl r14, 1, r14 // shift to bit 0
-
- srl r14, 1, r14 // shift off cpu number
- Get_TLSB_Node_Address(r14,r10) // compute our nodespace address
-
- ldlp r13, 0x40(r10) // read our TLBER WAS tlsb_tlber_offset
- srl r13, 17, r13 // shift down the CWDE/CRDE bits
-
- and r13, 3, r13 // mask the CWDE/CRDE bits
- beq r13, 1f
-
- ornot r31, r31, r12 // set flag
- lda r9, mchk_c_sys_ecc(r31) // System Correctable error MCHK code
- br r31, sys_merge_sys_corr // jump to CRD logout frame code
-
-1: lda r16, osfint_c_passrel(r31) // passive release
-
-
- ALIGN_BRANCH
-
-pal_post_dev_interrupt:
- or r13, r31, r17 // move vector to a1
- or r31, osfint_c_dev, r16 // a0 signals IO device interrupt
-
-pal_post_interrupt:
- mfpr r12, pt_entint
-
- mtpr r12, exc_addr
-
- nop
- nop
-
- hw_rei_spe
-
-
-
-//+
-// sys_passive_release
-// Just pretend the interrupt never occurred.
-//-
-
-EXPORT(sys_passive_release)
- mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps
- nop
-
- mfpr r31, pt0 // Pad write to dtb_cm
- hw_rei
-
-//+
-//sys_int_powerfail
-// A powerfail interrupt has been detected. The stack has been pushed.
-// IPL and PS are updated as well.
-//
-// I'm not sure what to do here, I'm treating it as an IO device interrupt
-//
-//-
-
- ALIGN_BLOCK
-sys_int_powerfail:
- lda r12, 0xffc4(r31) // get GBUS_MISCR address bits
- sll r12, 24, r12 // shift to proper position
- ldqp r12, 0(r12) // read GBUS_MISCR
- srl r12, 5, r12 // isolate bit <5>
- blbc r12, 1f // if clear, no missed mchk
-
- // Missed a CFAIL mchk
- lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits
- sll r13, 24, r13 // shift to proper position
- lda r14, 0x40(r31) // get bit <6> mask
- ldqp r12, 0(r13) // read GBUS$SERNUM
- or r12, r14, r14 // set bit <6>
- stqp r14, 0(r13) // clear GBUS$SERNUM<6>
- mb
- mb
-
-1: br r31, sys_int_mchk // do a machine check
-
- lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector
- mfpr r25, pt_entint
-
- lda r16, osfint_c_dev(r31) // a0 to device code
- mtpr r25, exc_addr
-
- nop // pad exc_addr write
- nop
-
- hw_rei_spe
-
-//+
-// sys$halt_interrupt
-// A halt interrupt has been detected. Pass control to the console.
-//
-//
-//-
- EXPORT(sys_halt_interrupt)
-
- ldah r13, 0x1800(r31) // load Halt/^PHalt bits
- Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits
-
- mtpr r11, dtb_cm // Restore Mbox current mode
- nop
- nop
- mtpr r0, pt0
-#ifndef SIMOS
- pvc_jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
-#endif
- lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt
- br r31, sys_enter_console // enter the console
-
-
-
-//+
-// sys$int_mchk_or_crd
-//
-// Current state:
-// Stack is pushed
-// ps, sp and gp are updated
-// r12
-// r13 - INTID (new EV5 IPL)
-// r14 - exc_addr
-// r25 - ISR
-// r16, r17, r18 - available
-//
-//-
- ALIGN_BLOCK
-
-sys_int_mchk_or_crd:
- srl r25, isr_v_mck, r12
- blbs r12, sys_int_mchk
- //+
- // Not a Machine check interrupt, so must be an Internal CRD interrupt
- //-
-
- mb //Clear out Cbox prior to reading IPRs
- srl r25, isr_v_crd, r13 //Check for CRD
- blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!!
-
- lda r9, 1(r31)
- sll r9, hwint_clr_v_crdc, r9 // get ack bit for crd
- mtpr r9, ev5__hwint_clr // ack the crd interrupt
-
- or r31, r31, r12 // clear flag
- lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code
-
-sys_merge_sys_corr:
- ldah r14, 0xfff0(r31)
- mtpr r0, pt0 // save r0 for scratch
- zap r14, 0xE0, r14 // Get Cbox IPR base
- mtpr r1, pt1 // save r0 for scratch
-
- ldqp r0, ei_addr(r14) // EI_ADDR IPR
- ldqp r10, fill_syn(r14) // FILL_SYN IPR
- bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub
-
- blbs r12, 1f // no scrubbing for IRQ0 case
-// XXX bugnion pvc_jsr crd_scrub_mem, bsr=1
- bsr r13, sys_crd_scrub_mem // and go scrub
-
- // ld/st pair in scrub routine will have finished due
- // to ibox stall of stx_c. Don't need another mb.
- ldqp r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
- or r8, r31, r12 // Must only be executed once in this flow, and must
- br r31, 2f // be after the scrub routine.
-
-1: ldqp r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
- // For IRQ0 CRD case only - meaningless data.
-
-2: mfpr r13, pt_mces // Get MCES
- srl r12, ei_stat_v_ei_es, r14 // Isolate EI_STAT:EI_ES
- blbc r14, 6f // branch if 630
- srl r13, mces_v_dsc, r14 // check if 620 reporting disabled
- blbc r14, 5f // branch if enabled
- or r13, r31, r14 // don't set SCE if disabled
- br r31, 8f // continue
-5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit
- br r31, 8f
-
-6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled
- blbc r14, 7f // branch if enabled
- or r13, r31, r14 // don't set PCE if disabled
- br r31, 8f // continue
-7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit
-
- // Setup SCB if dpc is not set
-8: mtpr r14, pt_mces // Store updated MCES
- srl r13, mces_v_sce, r1 // Get SCE
- srl r13, mces_v_pce, r14 // Get PCE
- or r1, r14, r1 // SCE OR PCE, since they share
- // the CRD logout frame
- // Get base of the logout area.
- GET_IMPURE(r14) // addr of per-cpu impure area
- GET_ADDR(r14,(pal_logout_area+mchk_crd_base),r14)
-
- blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame
-
- // Set the 2nd error flag in the logout area:
-
- lda r1, 3(r31) // Set retry and 2nd error flags
- sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword
- stlp r1, mchk_crd_flag+4(r14) // store flag longword
- br sys_crd_ack
-
-sys_crd_write_logout_frame:
- // should only be here if neither the pce or sce bits are set
-
- //+
- // Write the mchk code to the logout area
- //-
- stqp r9, mchk_crd_mchk_code(r14)
-
-
- //+
- // Write the first 2 quadwords of the logout area:
- //-
- lda r1, 1(r31) // Set retry flag
- sll r1, 63, r9 // Move retry flag to bit 63
- lda r1, mchk_crd_size(r9) // Combine retry flag and frame size
- stqp r1, mchk_crd_flag(r14) // store flag/frame size
-
-#ifndef SIMOS
- /* needed? bugnion */
- lda r1, mchk_crd_sys_base(r31) // sys offset
- sll r1, 32, r1
- lda r1, mchk_crd_cpu_base(r1) // cpu offset
- stqp r1, mchk_crd_offsets(r14) // store sys offset/cpu offset into logout frame
-
-#endif
- //+
- // Write error IPRs already fetched to the logout area
- //-
- stqp r0, mchk_crd_ei_addr(r14)
- stqp r10, mchk_crd_fill_syn(r14)
- stqp r8, mchk_crd_ei_stat(r14)
- stqp r25, mchk_crd_isr(r14)
- //+
- // Log system specific info here
- //-
-crd_storeTLEP_:
- lda r1, 0xffc4(r31) // Get GBUS$MISCR address
- sll r1, 24, r1
- ldqp r1, 0(r1) // Read GBUS$MISCR
- sll r1, 16, r1 // shift up to proper field
- mfpr r10, pt_whami // get our node id
- extbl r10, 1, r10 // shift to bit 0
- or r1, r10, r1 // merge MISCR and WHAMI
- stlp r1, mchk_crd_whami(r14) // write to crd logout area
- srl r10, 1, r10 // shift off cpu number
-
- Get_TLSB_Node_Address(r10,r0) // compute our nodespace address
-
- OSFcrd_TLEPstore_tlsb(tldev)
- OSFcrd_TLEPstore_tlsb_clr(tlber)
- OSFcrd_TLEPstore_tlsb_clr(tlesr0)
- OSFcrd_TLEPstore_tlsb_clr(tlesr1)
- OSFcrd_TLEPstore_tlsb_clr(tlesr2)
- OSFcrd_TLEPstore_tlsb_clr(tlesr3)
-
-sys_crd_ack:
- mfpr r0, pt0 // restore r0
- mfpr r1, pt1 // restore r1
-
- srl r12, ei_stat_v_ei_es, r12
- blbc r12, 5f
- srl r13, mces_v_dsc, r10 // logging enabled?
- br r31, 6f
-5: srl r13, mces_v_dpc, r10 // logging enabled?
-6: blbc r10, sys_crd_post_interrupt // logging enabled -- report it
-
- // logging not enabled --
- // Get base of the logout area.
- GET_IMPURE(r13) // addr of per-cpu impure area
- GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13)
- ldlp r10, mchk_crd_rsvd(r13) // bump counter
- addl r10, 1, r10
- stlp r10, mchk_crd_rsvd(r13)
- mb
- br r31, sys_crd_dismiss_interrupt // just return
-
- //+
- // The stack is pushed. Load up a0,a1,a2 and vector via entInt
- //
- //-
-
- ALIGN_BRANCH
-sys_crd_post_interrupt:
- lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
- lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector
-
- blbc r12, 1f
- lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector
-
-1: subq r31, 1, r18 // get a -1
- mfpr r25, pt_entInt
-
- srl r18, 42, r18 // shift off low bits of kseg addr
- mtpr r25, exc_addr // load interrupt vector
-
- sll r18, 42, r18 // shift back into position
- or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
-
- hw_rei_spe // done
-
-
- //+
- // The stack is pushed. Need to back out of it all.
- //-
-
-sys_crd_dismiss_interrupt:
- br r31, Call_Pal_Rti
-
-
-// .sbttl sys_crd_scrub_mem
-
- //+
- //
- // sys_crd_scrub_mem
- // called
- // jsr r13, sys$crd_scrub_mem
- // r0 = addr of cache block
- //
- //-
-
-
-
- ALIGN_BLOCK // align for branch target
-sys_crd_scrub_mem:
- // now find error in memory, and attempt to scrub that cache block
- // This routine just scrubs the failing octaword
- // Only need to "touch" one quadword per octaword to accomplish the scrub
- srl r0, 39, r8 // get high bit of bad pa
- blbs r8, 1f // don't attempt fixup on IO space addrs
- nop // needed to align the ldqpl to octaword boundary
- nop // "
-
- ldqpl r8, 0(r0) // attempt to read the bad memory
- // location
- // (Note bits 63:40,3:0 of ei_addr
- // are set to 1, but as long as
- // we are doing a phys ref, should
- // be ok)
- nop // Needed to keep the Ibox from swapping the ldqpl into E1
-
- stqpc r8, 0(r0) // Store it back if it is still there.
- // If store fails, location already
- // scrubbed by someone else
-
- nop // needed to align the ldqpl to octaword boundary
-
- lda r8, 0x20(r31) // flip bit 5 to touch next hexaword
- xor r8, r0, r0
- nop // needed to align the ldqpl to octaword boundary
- nop // "
-
- ldqpl r8, 0(r0) // attempt to read the bad memory
- // location
- // (Note bits 63:40,3:0 of ei_addr
- // are set to 1, but as long as
- // we are doing a phys ref, should
- // be ok)
- nop // Needed to keep the Ibox from swapping the ldqpl into E1
-
- stqpc r8, 0(r0) // Store it back if it is still there.
- // If store fails, location already
- // scrubbed by someone else
-
- lda r8, 0x20(r31) // restore r0 to original address
- xor r8, r0, r0
-
- //at this point, ei_stat could be locked due to a new corr error on the ld,
- //so read ei_stat to unlock AFTER this routine.
-
-// XXX bugnion pvc$jsr crd_scrub_mem, bsr=1, dest=1
-1: ret r31, (r13) // and back we go
-
-
-// .sbttl "SYS$INT_MCHK - MCHK Interrupt code"
-//+
-// Machine check interrupt from the system. Setup and join the
-// regular machine check flow.
-// On exit:
-// pt0 - saved r0
-// pt1 - saved r1
-// pt4 - saved r4
-// pt5 - saved r5
-// pt6 - saved r6
-// pt10 - saved exc_addr
-// pt_misc<47:32> - mchk code
-// pt_misc<31:16> - scb vector
-// r14 - base of Cbox IPRs in IO space
-// MCES<mchk> is set
-//-
- ALIGN_BLOCK
-sys_int_mchk:
- lda r14, mchk_c_sys_hrd_error(r31)
- mfpr r12, exc_addr
-
- addq r14, 1, r14 // Flag as interrupt
- nop
-
- sll r14, 32, r14 // Move mchk code to position
- mtpr r12, pt10 // Stash exc_addr
-
- mfpr r12, pt_misc // Get MCES and scratch
- mtpr r0, pt0 // Stash for scratch
-
- zap r12, 0x3c, r12 // Clear scratch
- blbs r12, sys_double_machine_check // MCHK halt if double machine check
-
- or r12, r14, r12 // Combine mchk code
- lda r14, scb_v_sysmchk(r31) // Get SCB vector
-
- sll r14, 16, r14 // Move SCBv to position
- or r12, r14, r14 // Combine SCBv
-
- bis r14, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
- mtpr r14, pt_misc // Save mchk code!scbv!whami!mces
-
- ldah r14, 0xfff0(r31)
- mtpr r1, pt1 // Stash for scratch
-
- zap r14, 0xE0, r14 // Get Cbox IPR base
- mtpr r4, pt4
-
- mtpr r5, pt5
-
-#if beh_model
-// .if ne beh_model
- ldah r25, 0xC000(r31) // Get base of demon space
- lda r25, 0x340(r25) // Add interrupt demon offset
-
- ldqp r13, 0(r25) // Read the control register
- nop
-
- and r13, 0x10, r8 // For debug, check that the interrupt is expected
- beq r8, interrupt_not_expected
-
- bic r13, 0x10, r13
- stqp r13, 0(r25) // Ack and clear the interrupt
-// XXX bugnion pvc$violate 379 // stqp can't trap except replay. mt ipr only problem if mf same ipr in same shadow
- .endc
-#endif
-
- mtpr r6, pt6
- br r31, sys_mchk_collect_iprs // Join common machine check flow
-
-
-// .sbttl "SYS$INT_PERF_CNT - Performance counter interrupt code"
-//+
-//sys$int_perf_cnt
-//
-// A performance counter interrupt has been detected. The stack has been pushed.
-// IPL and PS are updated as well.
-//
-// on exit to interrupt entry point ENTINT::
-// a0 = osfint$c_perf
-// a1 = scb$v_perfmon (650)
-// a2 = 0 if performance counter 0 fired
-// a2 = 1 if performance counter 1 fired
-// a2 = 2 if performance counter 2 fired
-// (if more than one counter overflowed, an interrupt will be
-// generated for each counter that overflows)
-//
-//
-//-
- ALIGN_BLOCK
-sys_int_perf_cnt: // Performance counter interrupt
- lda r17, scb_v_perfmon(r31) // a1 to interrupt vector
- mfpr r25, pt_entint
-
- lda r16, osfint_c_perf(r31) // a0 to perf counter code
- mtpr r25, exc_addr
-
- //isolate which perf ctr fired, load code in a2, and ack
- mfpr r25, isr
- or r31, r31, r18 // assume interrupt was pc0
-
- srl r25, isr_v_pc1, r25 // isolate
- cmovlbs r25, 1, r18 // if pc1 set, load 1 into r14
-
- srl r25, 1, r25 // get pc2
- cmovlbs r25, 2, r18 // if pc2 set, load 2 into r14
-
- lda r25, 1(r31) // get a one
- sll r25, r18, r25
-
- sll r25, hwint_clr_v_pc0c, r25 // ack only the perf counter that generated the interrupt
- mtpr r25, hwint_clr
-
- hw_rei_spe
-
-
-
- ALIGN_BLOCK
-// .sbttl "System specific RESET code"
-//+
-// RESET code
-// On entry:
-// r1 = pal_base +8
-//
-// Entry state on trap:
-// r0 = whami
-// r2 = base of scratch area
-// r3 = halt code
-// and the following 3 if init_cbox is enabled:
-// r5 = sc_ctl
-// r6 = bc_ctl
-// r7 = bc_cnfg
-//
-// Entry state on switch:
-// r17 - new PC
-// r18 - new PCBB
-// r19 - new VPTB
-//
-//-
-
-#if rax_mode==0
- .globl sys_reset
-sys_reset:
-// mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load
- mtpr r31, itb_ia // clear the ITB
- mtpr r31, dtb_ia // clear the DTB
-
- lda r1, -8(r1) // point to start of code
- mtpr r1, pal_base // initialize PAL_BASE
-
- // Interrupts
- mtpr r31, astrr // stop ASTs
- mtpr r31, aster // stop ASTs
- mtpr r31, sirr // clear software interrupts
-
- mtpr r0, pt1 // r0 is whami (unless we entered via swp)
-
-//orig ldah r1, <<1@<icsr$v_sde-16>> ! <1@<icsr$v_fpe-16>> ! <2@<icsr$v_spe-16>>>(r31)
- ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero)
-
-#if disable_crd == 0
-// .if eq disable_crd
- bis r31, 1, r0
- sll r0, icsr_v_crde, r0 // A 1 in iscr<corr_read_enable>
- or r0, r1, r1 // Set the bit
-#endif
-
- mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable,
- // super page enabled, correct read per assembly option
-
- // Mbox/Dcache init
-//orig lda r1, <1@<mcsr$v_sp1>>(r31)
- lda r1,BIT(mcsr_v_sp1)(zero)
-
- mtpr r1, mcsr // MCSR - Super page enabled
- lda r1, BIT(dc_mode_v_dc_ena)(r31)
- ALIGN_BRANCH
-// mtpr r1, dc_mode // turn Dcache on
- nop
-
- mfpr r31, pt0 // No Mbox instr in 1,2,3,4
- mfpr r31, pt0
- mfpr r31, pt0
- mfpr r31, pt0
- mtpr r31, dc_flush // flush Dcache
-
- // build PS (IPL=7,CM=K,VMM=0,SW=0)
- lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7
- lda r1, 0x1F(r31)
- mtpr r1, ipl // set internal <ipl>=1F
- mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy
- mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy
-
- // Create the PALtemp pt_intmask -
- // MAP:
- // OSF IPL EV5 internal IPL(hex) note
- // 0 0
- // 1 1
- // 2 2
- // 3 14 device
- // 4 15 device
- // 5 16 device
- // 6 1E device,performance counter, powerfail
- // 7 1F
- //
-
- ldah r1, 0x1f1E(r31) // Create upper lw of int_mask
- lda r1, 0x1615(r1)
-
- sll r1, 32, r1
- ldah r1, 0x1402(r1) // Create lower lw of int_mask
-
- lda r1, 0x0100(r1)
- mtpr r1, pt_intmask // Stash in PALtemp
-
- // Unlock a bunch of chip internal IPRs
- mtpr r31, exc_sum // clear out exeception summary and exc_mask
- mfpr r31, va // unlock va, mmstat
-//rig lda r8, <<1@icperr_stat$v_dpe> ! <1@icperr_stat$v_tpe> ! <1@icperr_stat$v_tmr>>(r31)
- lda r8,(BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(zero)
-
- mtpr r8, icperr_stat // Clear Icache parity error & timeout status
-//orig lda r8, <<1@dcperr_stat$v_lock> ! <1@dcperr_stat$v_seo>>(r31)
- lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
-
- mtpr r8, dcperr_stat // Clear Dcache parity error status
-
- rc r0 // clear intr_flag
- mtpr r31, pt_trap
-
- mfpr r0, pt_misc
- srl r0, pt_misc_v_switch, r1
- blbs r1, sys_reset_switch // see if we got here from swppal
-
- // Rest of the "real" reset flow
- // ASN
- mtpr r31, dtb_asn
- mtpr r31, itb_asn
-
- lda r1, 0x67(r31)
- sll r1, hwint_clr_v_pc0c, r1
- mtpr r1, hwint_clr // Clear hardware interrupt requests
-
- lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error
- mfpr r0, pt1 // get whami
- insbl r0, 1, r0 // isolate whami in correct pt_misc position
- or r0, r1, r1 // combine whami and mces
- mtpr r1, pt_misc // store whami and mces, swap bit clear
-
- zapnot r3, 1, r0 // isolate halt code
- mtpr r0, pt0 // save entry type
-
- // Cycle counter
- or r31, 1, r9 // get a one
- sll r9, 32, r9 // shift to <32>
- mtpr r31, cc // clear Cycle Counter
- mtpr r9, cc_ctl // clear and enable the Cycle Counter
- mtpr r31, pt_scc // clear System Cycle Counter
-
-
- // Misc PALtemps
- mtpr r31, maf_mode // no mbox instructions for 3 cycles
- or r31, 1, r1 // get bogus scbb value
- mtpr r1, pt_scbb // load scbb
- mtpr r31, pt_prbr // clear out prbr
-#ifdef SIMOS
-// or zero,kludge_initial_pcbb,r1
- GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
-#else
- mfpr r1, pal_base
-//orig sget_addr r1, (kludge_initial_pcbb-pal$base), r1, verify=0// get address for temp pcbb
- GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
-#endif
- mtpr r1, pt_pcbb // load pcbb
- lda r1, 2(r31) // get a two
- sll r1, 32, r1 // gen up upper bits
- mtpr r1, mvptbr
- mtpr r1, ivptbr
- mtpr r31, pt_ptbr
- // Performance counters
- mtpr r31, pmctr
-
-#if init_cbox != 0
-// .if ne init_cbox
- // Only init the Scache and the Bcache if there have been no previous
- // cacheable dstream loads or stores.
- //
- // Inputs:
- // r5 - sc_ctl
- // r6 - bc_ctl
- // r7 - bc_cnfg
-
- ldah r0, 0xfff0(r31)
- zap r0, 0xE0, r0 // Get Cbox IPR base
- ldqp r19, ev5__sc_ctl(r0) // read current sc_ctl
-temp = <<<1@bc_ctl$v_ei_dis_err> + <1@bc_ctl$v_ei_ecc_or_parity> + <1@bc_ctl$v_corr_fill_dat>>@-1>
- lda r20, temp(r31) // create default bc_ctl (bc disabled, errors disabled, ecc mode)
- sll r20, 1, r20
-temp = 0x017441 // default bc_config
- get_addr r21, temp, r31 // create default bc_config
- lda r23, <1@sc_ctl_v_sc_flush>(r31) //set flag to invalidate scache in set_sc_bc_ctl
-
-// XXX bugnion pvc$jsr scbcctl, bsr=1
- bsr r10, set_sc_bc_ctl
- update_bc_ctl_shadow r6, r23 // update bc_ctl shadow using r6 as input// r23 gets adjusted impure pointer
- store_reg1 bc_config, r7, r23, ipr=1 // update bc_config shadow in impure area
-// .endc
-#endif
- // Clear pmctr_ctl in impure area
-
-#ifndef SIMOS
- // can't assemble ???
- update_pmctr_ctl r31, r1 // clear pmctr_ctl // r1 trashed
-#endif
-
- ldah r14, 0xfff0(r31)
- zap r14, 0xE0, r14 // Get Cbox IPR base
-#ifndef SIMOS
- ldqp r31, sc_stat(r14) // Clear sc_stat and sc_addr
- ldqp r31, ei_stat(r14)
- ldqp r31, ei_stat(r14) // Clear ei_stat, ei_addr, bc_tag_addr, fill_syn
-#endif
- GET_IMPURE(r13)
- stqpc r31, 0(r13) // Clear lock_flag
-
- mfpr r0, pt0 // get entry type
- br r31, sys_enter_console // enter the cosole
-
-#endif /* rax_mode == 0 */
-
-
-
-
-//.if ne rax_mode
-#if rax_mode != 0
-
- // For RAX:
- // r0 - icsr at first, then used for cbox ipr base offset
- // r2 - mcsr
- // r3 - dc_mode
- // r4 - maf_mode
- // r5 - sc_ctl
- // r6 - bc_ctl
- // r7 - bc_cnfg
- .globl sys_reset
-sys_reset:
- mtpr r31, ev5__dtb_cm // set mbox mode to kernel
- mtpr r31, ev5__ps // set Ibox mode to kernel - E1
-
- mtpr r0, ev5__icsr // Load ICSR - E1
-
- mtpr r2, ev5__mcsr
- mfpr r8, pal_base
-
- ldah r0, 0xfff0(r31)
- zap r0, 0xE0, r0 // Get Cbox IPR base
-
- mtpr r31, ev5__itb_asn // clear asn - E1
- ldqp r19, ev5__sc_ctl(r0) // read current sc_ctl
-
-temp = <<<1@bc_ctl$v_ei_dis_err> + <1@bc_ctl$v_ei_ecc_or_parity> + <1@bc_ctl$v_corr_fill_dat>>@-1>
- lda r20, temp(r31) // create default bc_ctl (bc disabled, errors disabled, ecc mode)
- sll r20, 1, r20
-
-temp = 0x017441 // default bc_config
- get_addr r21, temp, r31 // create default bc_config
- lda r23, <1@sc_ctl_v_sc_flush>(r31) //set flag to invalidate scache in set_sc_bc_ctl
-
-// XXX bugnion pvc$jsr scbcctl, bsr=1
- bsr r10, set_sc_bc_ctl
- update_bc_ctl_shadow r6, r2 // initialize bc_ctl shadow// adjusted impure pointer in r2
- store_reg1 pmctr_ctl, r31, r2, ipr=1 // clear pmctr_ctl
- store_reg1 bc_config, r7, r2, ipr=1 // initialize bc_config shadow
-
- mtpr r3, ev5__dc_mode // write dc_mode
- mtpr r31, ev5__dc_flush // flush dcache
-
- mtpr r31, ev5__exc_sum // clear exc_sum - E1
- mtpr r31, ev5__exc_mask // clear exc_mask - E1
-
- ldah r2, 4(r31) // For EXC_ADDR
- mtpr r2, ev5__exc_addr // EXC_ADDR to 40000 (hex)
-
- mtpr r31, ev5__sirr // Clear SW interrupts (for ISP)
- mtpr r4, ev5__maf_mode // write maf_mode
-
- mtpr r31, ev5__alt_mode // set alt_mode to kernel
- mtpr r31, ev5__itb_ia // clear ITB - E1
-
- lda r1, 0x1F(r31) // For IPL
- mtpr r1, ev5__ipl // IPL to 1F
-
- mtpr r31, ev5__hwint_clr // clear hardware interrupts
- mtpr r31, ev5__aster // disable AST interrupts
-
- mtpr r31, ev5__astrr // clear AST requests
- mtpr r31, ev5__dtb_ia // clear dtb
-
- nop
- mtpr r31, pt_trap
-
- srl r2, page_offset_size_bits, r9 // Start to make PTE for address 40000
- sll r9, 32, r9
-
- lda r9, 0x7F01(r9) // Make PTE, V set, all RE set, all but UWE set
- nop
-
- mtpr r9, dtb_pte // ACORE hack, load TB with 1-1 translation for address 40000
- mtpr r2, itb_tag // ACORE hack, load TB with 1-1 translation for address 40000
-
- mtpr r2, dtb_tag
- mtpr r9, itb_pte
-
- and r31, r31, r0 // clear deposited registers, note: r2 already overwritten
- and r31, r31, r3
-
- and r31, r31, r4
- and r31, r31, r5
-
- and r31, r31, r6
- and r31, r31, r7
-
- hw_rei //May need to be a rei_stall since
- //we write to TB's above
- //However, it currently works ok. (JH)
-
-
-// .endc
-#endif /*rax_mode != 0 */
-
-
- // swppal entry
- // r0 - pt_misc
- // r17 - new PC
- // r18 - new PCBB
- // r19 - new VPTB
-sys_reset_switch:
- or r31, 1, r9
- sll r9, pt_misc_v_switch, r9
- bic r0, r9, r0 // clear switch bit
- mtpr r0, pt_misc
-
- rpcc r1 // get cyccounter
-
- ldqp r22, osfpcb_q_fen(r18) // get new fen/pme
- ldlp r23, osfpcb_l_cc(r18) // get cycle counter
- ldlp r24, osfpcb_l_asn(r18) // get new asn
-
-
- ldqp r25, osfpcb_q_Mmptr(r18)// get new mmptr
- sll r25, page_offset_size_bits, r25 // convert pfn to pa
- mtpr r25, pt_ptbr // load the new mmptr
- mtpr r18, pt_pcbb // set new pcbb
-
- bic r17, 3, r17 // clean use pc
- mtpr r17, exc_addr // set new pc
- mtpr r19, mvptbr
- mtpr r19, ivptbr
-
- ldqp r30, osfpcb_q_Usp(r18) // get new usp
- mtpr r30, pt_usp // save usp
-
- sll r24, dtb_asn_v_asn, r8
- mtpr r8, dtb_asn
- sll r24, itb_asn_v_asn, r24
- mtpr r24, itb_asn
-
- mfpr r25, icsr // get current icsr
- lda r24, 1(r31)
- sll r24, icsr_v_fpe, r24 // 1 in icsr<fpe> position
- bic r25, r24, r25 // clean out old fpe
- and r22, 1, r22 // isolate new fen bit
- sll r22, icsr_v_fpe, r22
- or r22, r25, r25 // or in new fpe
- mtpr r25, icsr // update ibox ipr
-
- subl r23, r1, r1 // gen new cc offset
- insll r1, 4, r1 // << 32
- mtpr r1, cc // set new offset
-
- or r31, r31, r0 // set success
- ldqp r30, osfpcb_q_Ksp(r18) // get new ksp
- mfpr r31, pt0 // stall
- hw_rei_stall
-
-// .sbttl "SYS_MACHINE_CHECK - Machine check PAL"
- ALIGN_BLOCK
-//+
-//sys$machine_check
-// A machine_check trap has occurred. The Icache has been flushed.
-//
-//-
-
-EXPORT(sys_machine_check)
- // Need to fill up the refill buffer (32 instructions) and
- // then flush the Icache again.
- // Also, due to possible 2nd Cbox register file write for
- // uncorrectable errors, no register file read or write for 7 cycles.
-
- nop
- mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites r0 later
-
- nop
- nop
-
- nop
- nop
-
- nop
- nop
-
- nop
- nop
- // 10 instructions// 5 cycles
-
- nop
- nop
-
- nop
- nop
-
- // Register file can now be written
- lda r0, scb_v_procmchk(r31) // SCB vector
- mfpr r13, pt_mces // Get MCES
- sll r0, 16, r0 // Move SCBv to correct position
-// bis r13, #<1@mces$v_mchk>, r14 // Set MCES<MCHK> bit
- bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
-
-
- zap r14, 0x3C, r14 // Clear mchk_code word and SCBv word
- mtpr r14, pt_mces
- // 20 instructions
-
- nop
- or r14, r0, r14 // Insert new SCB vector
- lda r0, mchk_c_proc_hrd_error(r31) // MCHK code
- mfpr r12, exc_addr
-
- sll r0, 32, r0 // Move MCHK code to correct position
- mtpr r4, pt4
- or r14, r0, r14 // Insert new MCHK code
- mtpr r14, pt_misc // Store updated MCES, MCHK code, and SCBv
-
- ldah r14, 0xfff0(r31)
- mtpr r1, pt1 // Stash for scratch - 30 instructions
-
- zap r14, 0xE0, r14 // Get Cbox IPR base
- mtpr r12, pt10 // Stash exc_addr
-
-
-
- mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed.
- blbs r13, sys_double_machine_check // MCHK halt if double machine check
-
- mtpr r6, pt6
- mtpr r5, pt5
-
- // Look for the powerfail cases here....
- mfpr r4, isr
- srl r4, isr_v_pfl, r4
- blbc r4, sys_mchk_collect_iprs // skip if no powerfail interrupt pending
- lda r4, 0xffc4(r31) // get GBUS$MISCR address bits
- sll r4, 24, r4 // shift to proper position
- ldqp r4, 0(r4) // read GBUS$MISCR
- srl r4, 5, r4 // isolate bit <5>
- blbc r4, sys_mchk_collect_iprs // skip if already cleared
- // No missed CFAIL mchk
- lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits
- sll r5, 24, r5 // shift to proper position
- lda r6, 0x40(r31) // get bit <6> mask
- ldqp r4, 0(r5) // read GBUS$SERNUM
- or r4, r6, r6 // set bit <6>
- stqp r6, 0(r5) // clear GBUS$SERNUM<6>
- mb
- mb
-
-
- //+
- // Start to collect the IPRs. Common entry point for mchk flows.
- //
- // Current state:
- // pt0 - saved r0
- // pt1 - saved r1
- // pt4 - saved r4
- // pt5 - saved r5
- // pt6 - saved r6
- // pt10 - saved exc_addr
- // pt_misc<47:32> - mchk code
- // pt_misc<31:16> - scb vector
- // r14 - base of Cbox IPRs in IO space
- // r0, r1, r4, r5, r6, r12, r13, r25 - available
- // r8, r9, r10 - available as all loads are physical
- // MCES<mchk> is set
- //
- //-
-
-EXPORT(sys_mchk_collect_iprs)
- mb // MB before reading Scache IPRs
- mfpr r1, icperr_stat
-
- mfpr r8, dcperr_stat
- mtpr r31, dc_flush // Flush the Dcache
-
- mfpr r31, pt0 // Pad Mbox instructions from dc_flush
- mfpr r31, pt0
- nop
- nop
-
- ldqp r9, sc_addr(r14) // SC_ADDR IPR
- bis r9, r31, r31 // Touch ld to make sure it completes before
- // read of SC_STAT
- ldqp r10, sc_stat(r14) // SC_STAT, also unlocks SC_ADDR
-
- ldqp r12, ei_addr(r14) // EI_ADDR IPR
- ldqp r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR
- ldqp r0, fill_syn(r14) // FILL_SYN IPR
- bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT
- bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT
- ldqp r25, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
- ldqp r31, ei_stat(r14) // Read again to insure it is unlocked
-
-
-
-
- //+
- // Look for nonretryable cases
- // In this segment:
- // r5<0> = 1 means retryable
- // r4, r6, and r14 are available for scratch
- //
- //-
-
-
- bis r31, r31, r5 // Clear local retryable flag
- srl r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits to low bits
-
- lda r4, 1(r31)
- sll r4, icperr_stat_v_tmr, r4
- and r1, r4, r4 // Timeout reset
- bne r4, sys_cpu_mchk_not_retryable
-
- and r8, BIT(dcperr_stat_v_lock), r4 // DCache parity error locked
- bne r4, sys_cpu_mchk_not_retryable
-
- lda r4, 1(r31)
- sll r4, sc_stat_v_sc_scnd_err, r4
- and r10, r4, r4 // 2nd Scache error occurred
- bne r4, sys_cpu_mchk_not_retryable
-
-
- bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control
- // Parity Error, Interface Parity Error, 2nd Error
-
- and r25, r4, r4
- bne r4, sys_cpu_mchk_not_retryable
-
-// bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4
- bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
- and r25, r4, r4 // Isolate the Uncorrectable Error Bit
-// bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6
- bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit
- cmovne r6, 0, r4 // r4 = 0 if IRD or if No Uncorrectable Error
- bne r4, sys_cpu_mchk_not_retryable
-
- lda r4, 7(r31)
- and r10, r4, r4 // Isolate the Scache Tag Parity Error bits
- bne r4, sys_cpu_mchk_not_retryable // All Scache Tag PEs are not retryable
-
-
- lda r4, 0x7f8(r31)
- and r10, r4, r4 // Isolate the Scache Data Parity Error bits
- srl r10, sc_stat_v_cbox_cmd, r6
- and r6, 0x1f, r6 // Isolate Scache Command field
- subq r6, 1, r6 // Scache Iread command = 1
- cmoveq r6, 0, r4 // r4 = 0 if IRD or if No Parity Error
- bne r4, sys_cpu_mchk_not_retryable
-
- // Look for the system unretryable cases here....
-
- mfpr r4, isr // mchk_interrupt pin asserted
- srl r4, isr_v_mck, r4
- blbs r4, sys_cpu_mchk_not_retryable
-
-
-
- //+
- // Look for retryable cases
- // In this segment:
- // r5<0> = 1 means retryable
- // r6 - holds the mchk code
- // r4 and r14 are available for scratch
- //
- //-
-
-
- // Within the chip, the retryable cases are Istream errors
- lda r4, 3(r31)
- sll r4, icperr_stat_v_dpe, r4
- and r1, r4, r4
- cmovne r4, 1, r5 // Retryable if just Icache parity error
-
-
- lda r4, 0x7f8(r31)
- and r10, r4, r4 // Isolate the Scache Data Parity Error bits
- srl r10, sc_stat_v_cbox_cmd, r14
- and r14, 0x1f, r14 // Isolate Scache Command field
- subq r14, 1, r14 // Scache Iread command = 1
- cmovne r4, 1, r4 // r4 = 1 if Scache data parity error bit set
- cmovne r14, 0, r4 // r4 = 1 if Scache PE and Iread
- bis r4, r5, r5 // Accumulate
-
-
- bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
- and r25, r4, r4 // Isolate the Uncorrectable Error Bit
- and r25, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r14 // Isolate the Iread bit
- cmovne r4, 1, r4 // r4 = 1 if uncorr error
- cmoveq r14, 0, r4 // r4 = 1 if uncorr and Iread
- bis r4, r5, r5 // Accumulate
-
- mfpr r6, pt_misc
- extwl r6, 4, r6 // Fetch mchk code
- bic r6, 1, r6 // Clear flag from interrupt flow
- cmovne r5, mchk_c_retryable_ird, r6 // Set mchk code
-
-
-
- // In the system, the retryable cases are ...
- // (code here handles beh model read NXM)
-
-#if beh_model != 0
-// .if ne beh_model
- ldah r4, 0xC000(r31) // Get base of demon space
- lda r4, 0x550(r4) // Add NXM demon flag offset
-
- ldqp r4, 0(r4) // Read the demon register
- lda r14, mchk_c_read_nxm(r31)
- cmovlbs r4, r14, r6 // Set mchk code if read NXM
- cmovlbs r4, 1, r4
- bis r4, r5, r5 // Accumulate retry bit
-#endif
-
-
- //+
- // Write the logout frame
- //
- // Current state:
- // r0 - fill_syn
- // r1 - icperr_stat
- // r4 - available
- // r5<0> - retry flag
- // r6 - mchk code
- // r8 - dcperr_stat
- // r9 - sc_addr
- // r10 - sc_stat
- // r12 - ei_addr
- // r13 - bc_tag_addr
- // r14 - available
- // r25 - ei_stat (shifted)
- // pt0 - saved r0
- // pt1 - saved r1
- // pt4 - saved r4
- // pt5 - saved r5
- // pt6 - saved r6
- // pt10 - saved exc_addr
- //
- //-
-
-sys_mchk_write_logout_frame:
- // Get base of the logout area.
- GET_IMPURE(r14) // addr of per-cpu impure area
- GET_ADDR(r14,pal_logout_area+mchk_mchk_base,r14)
-
- // Write the first 2 quadwords of the logout area:
-
- sll r5, 63, r5 // Move retry flag to bit 63
- lda r4, mchk_size(r5) // Combine retry flag and frame size
- stqp r4, mchk_flag(r14) // store flag/frame size
- lda r4, mchk_sys_base(r31) // sys offset
- sll r4, 32, r4
- lda r4, mchk_cpu_base(r4) // cpu offset
- stqp r4, mchk_offsets(r14) // store sys offset/cpu offset into logout frame
-
- //+
- // Write the mchk code to the logout area
- // Write error IPRs already fetched to the logout area
- // Restore some GPRs from PALtemps
- //-
-
- mfpr r5, pt5
- stqp r6, mchk_mchk_code(r14)
- mfpr r4, pt4
- stqp r1, mchk_ic_perr_stat(r14)
- mfpr r6, pt6
- stqp r8, mchk_dc_perr_stat(r14)
- mfpr r1, pt1
- stqp r9, mchk_sc_addr(r14)
- stqp r10, mchk_sc_stat(r14)
- stqp r12, mchk_ei_addr(r14)
- stqp r13, mchk_bc_tag_addr(r14)
- stqp r0, mchk_fill_syn(r14)
- mfpr r0, pt0
- sll r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits back to expected position
- // retrieve lower 28 bits again from ei_stat and restore before storing to logout frame
- ldah r13, 0xfff0(r31)
- zapnot r13, 0x1f, r13
- ldqp r13, ei_stat(r13)
- sll r13, 64-ei_stat_v_bc_tperr, r13
- srl r13, 64-ei_stat_v_bc_tperr, r13
- or r25, r13, r25
- stqp r25, mchk_ei_stat(r14)
-
-
-
-
- //+
- // complete the CPU-specific part of the logout frame
- //-
-
-#ifndef SIMOS
- // cant' assemble.Where is the macro ?
- mchk_logout mm_stat
- mchk_logout va // Unlocks VA and MM_STAT
- mchk_logout isr
- mchk_logout icsr
- mchk_logout pal_base
- mchk_logout exc_mask
- mchk_logout exc_sum
-#endif
-
- ldah r13, 0xfff0(r31)
- zap r13, 0xE0, r13 // Get Cbox IPR base
- ldqp r13, ld_lock(r13) // Get ld_lock IPR
- stqp r13, mchk_ld_lock(r14) // and stash it in the frame
-
- //+
- // complete the PAL-specific part of the logout frame
- //-
-#ifdef vms
- t = 0
- .repeat 24
- pt_mchk_logout \t
- t = t + 1
- .endr
-#endif
-#ifndef SIMOS
- //can't assemble ?
- pt_mchk_logout 0
- pt_mchk_logout 1
- pt_mchk_logout 2
- pt_mchk_logout 3
- pt_mchk_logout 4
- pt_mchk_logout 5
- pt_mchk_logout 6
- pt_mchk_logout 7
- pt_mchk_logout 8
- pt_mchk_logout 9
- pt_mchk_logout 10
- pt_mchk_logout 11
- pt_mchk_logout 12
- pt_mchk_logout 13
- pt_mchk_logout 14
- pt_mchk_logout 15
- pt_mchk_logout 16
- pt_mchk_logout 17
- pt_mchk_logout 18
- pt_mchk_logout 19
- pt_mchk_logout 20
- pt_mchk_logout 21
- pt_mchk_logout 22
- pt_mchk_logout 23
-#endif
-
-
- //+
- // Log system specific info here
- //-
-
-#if alpha_fw != 0
-// .if ne alpha_fw
-storeTLEP_:
- lda r13, 0xffc4(r31) // Get GBUS$MISCR address
- sll r13, 24, r13
- ldqp r13, 0(r13) // Read GBUS$MISCR
- sll r13, 16, r13 // shift up to proper field
- mfpr r8, pt_whami // get our node id
- extbl r8, 1, r8 // shift to bit 0
- or r13, r8, r13 // merge MISCR and WHAMI
- stlp r13, mchk$gbus(r14) // write to logout area
- srl r8, 1, r8 // shift off cpu number
-
- Get_TLSB_Node_Address r8,r13 // compute our nodespace address
-
- OSFmchk_TLEPstore tldev, tlsb=1
- OSFmchk_TLEPstore tlber, tlsb=1, clr=1
- OSFmchk_TLEPstore tlcnr, tlsb=1
- OSFmchk_TLEPstore tlvid, tlsb=1
- OSFmchk_TLEPstore tlesr0, tlsb=1, clr=1
- OSFmchk_TLEPstore tlesr1, tlsb=1, clr=1
- OSFmchk_TLEPstore tlesr2, tlsb=1, clr=1
- OSFmchk_TLEPstore tlesr3, tlsb=1, clr=1
- OSFmchk_TLEPstore tlmodconfig
- OSFmchk_TLEPstore tlepaerr, clr=1
- OSFmchk_TLEPstore tlepderr, clr=1
- OSFmchk_TLEPstore tlepmerr, clr=1
- OSFmchk_TLEPstore tlintrmask0
- OSFmchk_TLEPstore tlintrmask1
- OSFmchk_TLEPstore tlintrsum0
- OSFmchk_TLEPstore tlintrsum1
- OSFmchk_TLEPstore tlep_vmg
-// .endc
-#endif /*alpha_fw != 0 */
- // Unlock IPRs
- lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
- mtpr r8, dcperr_stat // Clear Dcache parity error status
-
- lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31)
- mtpr r8, icperr_stat // Clear Icache parity error & timeout status
-
-1: ldqp r8, mchk_ic_perr_stat(r14) // get ICPERR_STAT value
- GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value
- and r0, r8, r0 // compare
- beq r0, 2f // check next case if nothing set
- lda r0, mchk_c_retryable_ird(r31) // set new MCHK code
- br r31, do_670 // setup new vector
-
-2: ldqp r8, mchk_dc_perr_stat(r14) // get DCPERR_STAT value
- GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value
- and r0, r8, r0 // compare
- beq r0, 3f // check next case if nothing set
- lda r0, mchk_c_dcperr(r31) // set new MCHK code
- br r31, do_670 // setup new vector
-
-3: ldqp r8, mchk_sc_stat(r14) // get SC_STAT value
- GET_ADDR(r0,0x107ff,r31) // get SC_STAT value
- and r0, r8, r0 // compare
- beq r0, 4f // check next case if nothing set
- lda r0, mchk_c_scperr(r31) // set new MCHK code
- br r31, do_670 // setup new vector
-
-4: ldqp r8, mchk_ei_stat(r14) // get EI_STAT value
- GET_ADDR(r0,0x30000000,r31) // get EI_STAT value
- and r0, r8, r0 // compare
- beq r0, 5f // check next case if nothing set
- lda r0, mchk_c_bcperr(r31) // set new MCHK code
- br r31, do_670 // setup new vector
-
-5: ldlp r8, mchk_tlber(r14) // get TLBER value
- GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value
- sll r0, 16, r0 // shift into proper position
- GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value
- or r0, r1, r0 // merge mask values
- and r0, r8, r0 // compare
- beq r0, 6f // check next case if nothing set
- GET_ADDR(r0, 0xfff0, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-6: ldlp r8, mchk_tlepaerr(r14) // get TLEPAERR value
- GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value
- and r0, r8, r0 // compare
- beq r0, 7f // check next case if nothing set
- GET_ADDR(r0, 0xfffa, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-7: ldlp r8, mchk_tlepderr(r14) // get TLEPDERR value
- GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value
- and r0, r8, r0 // compare
- beq r0, 8f // check next case if nothing set
- GET_ADDR(r0, 0xfffb, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-8: ldlp r8, mchk_tlepmerr(r14) // get TLEPMERR value
- GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value
- and r0, r8, r0 // compare
- beq r0, 9f // check next case if nothing set
- GET_ADDR(r0, 0xfffc, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-9: ldqp r8, mchk_ei_stat(r14) // get EI_STAT value
- GET_ADDR(r0,0xb,r31) // get EI_STAT mask value
- sll r0, 32, r0 // shift to upper lw
- and r0, r8, r0 // compare
- beq r0, 1f // check next case if nothing set
- GET_ADDR(r0,0xfffd,r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-1: ldlp r8, mchk_tlepaerr(r14) // get TLEPAERR value
- GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value
- and r0, r8, r0 // compare
- beq r0, cont_logout_frame // check next case if nothing set
- GET_ADDR(r0, 0xfffe, r31) // set new MCHK code
- br r31, do_660 // setup new vector
-
-do_670: lda r8, scb_v_procmchk(r31) // SCB vector
- br r31, do_6x0_cont
-do_660: lda r8, scb_v_sysmchk(r31) // SCB vector
-do_6x0_cont:
- sll r8, 16, r8 // shift to proper position
- mfpr r1, pt_misc // fetch current pt_misc
- GET_ADDR(r4,0xffff, r31) // mask for vector field
- sll r4, 16, r4 // shift to proper position
- bic r1, r4, r1 // clear out old vector field
- or r1, r8, r1 // merge in new vector
- mtpr r1, pt_misc // save new vector field
- stlp r0, mchk_mchk_code(r14) // save new mchk code
-
-cont_logout_frame:
- // Restore some GPRs from PALtemps
- mfpr r0, pt0
- mfpr r1, pt1
- mfpr r4, pt4
-
- mfpr r12, pt10 // fetch original PC
- blbs r12, sys_machine_check_while_in_pal // MCHK halt if machine check in pal
-
-//XXXbugnion pvc_jsr armc, bsr=1
- bsr r12, sys_arith_and_mchk // go check for and deal with arith trap
-
- mtpr r31, exc_sum // Clear Exception Summary
-
- mfpr r25, pt10 // write exc_addr after arith_and_mchk to pickup new pc
- stqp r25, mchk_exc_addr(r14)
-
- //+
- // Set up the km trap
- //-
-
-
-sys_post_mchk_trap:
- mfpr r25, pt_misc // Check for flag from mchk interrupt
- extwl r25, 4, r25
- blbs r25, sys_mchk_stack_done // Stack from already pushed if from interrupt flow
-
- bis r14, r31, r12 // stash pointer to logout area
- mfpr r14, pt10 // get exc_addr
-
- sll r11, 63-3, r25 // get mode to msb
- bge r25, 3f
-
- mtpr r31, dtb_cm
- mtpr r31, ev5__ps
-
- mtpr r30, pt_usp // save user stack
- mfpr r30, pt_ksp
-
-3:
- lda sp, 0-osfsf_c_size(sp) // allocate stack space
- nop
-
- stq r18, osfsf_a2(sp) // a2
- stq r11, osfsf_ps(sp) // save ps
-
- stq r14, osfsf_pc(sp) // save pc
- mfpr r25, pt_entint // get the VA of the interrupt routine
-
- stq r16, osfsf_a0(sp) // a0
- lda r16, osfint_c_mchk(r31) // flag as mchk in a0
-
- stq r17, osfsf_a1(sp) // a1
- mfpr r17, pt_misc // get vector
-
- stq r29, osfsf_gp(sp) // old gp
- mtpr r25, exc_addr //
-
- or r31, 7, r11 // get new ps (km, high ipl)
- subq r31, 1, r18 // get a -1
-
- extwl r17, 2, r17 // a1 <- interrupt vector
- bis r31, ipl_machine_check, r25
-
- mtpr r25, ipl // Set internal ipl
- srl r18, 42, r18 // shift off low bits of kseg addr
-
- sll r18, 42, r18 // shift back into position
- mfpr r29, pt_kgp // get the kern r29
-
- or r12, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
- hw_rei_spe // out to interrupt dispatch routine
-
-
- //+
- // The stack is pushed. Load up a0,a1,a2 and vector via entInt
- //
- //-
- ALIGN_BRANCH
-sys_mchk_stack_done:
- lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
- lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector
-
- subq r31, 1, r18 // get a -1
- mfpr r25, pt_entInt
-
- srl r18, 42, r18 // shift off low bits of kseg addr
- mtpr r25, exc_addr // load interrupt vector
-
- sll r18, 42, r18 // shift back into position
- or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
-
- hw_rei_spe // done
-
-
- ALIGN_BRANCH
-sys_cpu_mchk_not_retryable:
- mfpr r6, pt_misc
- extwl r6, 4, r6 // Fetch mchk code
- br r31, sys_mchk_write_logout_frame //
-
-
-
-//+
-//sys$double_machine_check - a machine check was started, but MCES<MCHK> was
-// already set. We will now double machine check halt.
-//
-// pt0 - old R0
-//
-//+
-
-EXPORT(sys_double_machine_check)
-#ifndef SIMOS
- pvc$jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
-#endif
- lda r0, hlt_c_dbl_mchk(r31)
- br r31, sys_enter_console
-
-//+
-//sys$machine_check_while_in_pal - a machine check was started, exc_addr points to
-// a PAL PC. We will now machine check halt.
-//
-// pt0 - old R0
-//
-//+
-sys_machine_check_while_in_pal:
- stqp r12, mchk_exc_addr(r14) // exc_addr has not yet been written
-
-#ifndef SIMOS
- pvc$jsr updpcb, bsr=1
- bsr r0, pal_update_pcb // update the pcb
-#endif
- lda r0, hlt_c_mchk_from_pal(r31)
- br r31, sys_enter_console
-
-
-//ARITH and MCHK
-// Check for arithmetic errors and build trap frame,
-// but don't post the trap.
-// on entry:
-// pt10 - exc_addr
-// r12 - return address
-// r14 - logout frame pointer
-// r13 - available
-// r8,r9,r10 - available except across stq's
-// pt0,1,6 - available
-//
-// on exit:
-// pt10 - new exc_addr
-// r17 = exc_mask
-// r16 = exc_sum
-// r14 - logout frame pointer
-//
- ALIGN_BRANCH
-sys_arith_and_mchk:
- mfpr r13, ev5__exc_sum
- srl r13, exc_sum_v_swc, r13
- bne r13, handle_arith_and_mchk
-
-// XXX bugnion pvc$jsr armc, bsr=1, dest=1
- ret r31, (r12) // return if no outstanding arithmetic error
-
-handle_arith_and_mchk:
- mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
- // no virt ref for next 2 cycles
- mtpr r14, pt0
-
- mtpr r1, pt1 // get a scratch reg
- and r11, osfps_m_mode, r1 // get mode bit
-
- bis r11, r31, r25 // save ps
- beq r1, 1f // if zero we are in kern now
-
- bis r31, r31, r25 // set the new ps
- mtpr r30, pt_usp // save user stack
-
- mfpr r30, pt_ksp // get kern stack
-1:
- mfpr r14, exc_addr // get pc into r14 in case stack writes fault
-
- lda sp, 0-osfsf_c_size(sp) // allocate stack space
- mtpr r31, ev5__ps // Set Ibox current mode to kernel
-
- mfpr r1, pt_entArith
- stq r14, osfsf_pc(sp) // save pc
-
- stq r17, osfsf_a1(sp)
- mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
-
- stq r29, osfsf_gp(sp)
- stq r16, osfsf_a0(sp) // save regs
-
- bis r13, r31, r16 // move exc_sum to r16
- stq r18, osfsf_a2(sp)
-
- stq r11, osfsf_ps(sp) // save ps
- mfpr r29, pt_kgp // get the kern gp
-
- mfpr r14, pt0 // restore logout frame pointer from pt0
- bis r25, r31, r11 // set new ps
-
- mtpr r1, pt10 // Set new PC
- mfpr r1, pt1
-
-// XXX bugnion pvc$jsr armc, bsr=1, dest=1
- ret r31, (r12) // return if no outstanding arithmetic error
-
-
-
-// .sbttl "SYS$ENTER_CONSOLE - Common PALcode for ENTERING console"
-
- ALIGN_BLOCK
-
-// SYS$enter_console
-//
-// Entry:
-// Entered when PAL wants to enter the console.
-// usually as the result of a HALT instruction or button,
-// or catastrophic error.
-//
-// Regs on entry...
-//
-// R0 = halt code
-// pt0 <- r0
-//
-// Function:
-//
-// Save all readable machine state, and "call" the console
-//
-// Returns:
-//
-//
-// Notes:
-//
-// In these routines, once the save state routine has been executed,
-// the remainder of the registers become scratchable, as the only
-// "valid" copy of them is the "saved" copy.
-//
-// Any registers or PTs that are modified before calling the save
-// routine will have there data lost. The code below will save all
-// state, but will loose pt 0,4,5.
-//
-//-
-
-EXPORT(sys_enter_console)
- mtpr r1, pt4
- mtpr r3, pt5
-#ifdef SIMOS
- subq r31, 1, r1
- sll r1, 42, r1
- ldah r1, 1(r1)
-#else /* SIMOS */
- lda r3, pal_enter_console_ptr(r31) //find stored vector
- ldqp r1, 0(r3)
-#endif /* SIMOS */
-
-#ifdef SIMOS
- /* taken from scrmax, seems like the obvious thing to do */
- mtpr r1, exc_addr
- mfpr r1, pt4
- mfpr r3, pt5
- STALL
- STALL
- hw_rei_stall
-#else
- pvc$violate 1007
- jmp r31, (r1) // off to common routine
-#endif
-
-
-// .sbttl "SYS$EXIT_CONSOLE - Common PALcode for ENTERING console"
-//+
-// sys$exit_console
-//
-// Entry:
-// Entered when console wants to reenter PAL.
-// usually as the result of a CONTINUE.
-//
-//
-// Regs' on entry...
-//
-//
-// Function:
-//
-// Restore all readable machine state, and return to user code.
-//
-//
-//
-//-
- ALIGN_BLOCK
-sys_exit_console:
- //Disable physical mode:
-#if enable_physical_console != 0
-// .if ne enable_physical_console
- mfpr r25, pt_ptbr
- bic r25, 1, r25 // clear physical console flag
- mtpr r25, pt_ptbr
-#endif
-
- GET_IMPURE(r1)
-
- // clear lock and intr_flags prior to leaving console
- rc r31 // clear intr_flag
- // lock flag cleared by restore_state
-#ifndef SIMOS
- pvc$jsr rststa, bsr=1
- bsr r3, pal_restore_state // go restore all state
- // note, R1 and R3 are NOT restored
- // by restore_state.
-#endif
- // TB's have been flushed
-
- ldqp r3, (cns_gpr+(8*3))(r1) // restore r3
- ldqp r1, (cns_gpr+8)(r1) // restore r1
- hw_rei_stall // back to user
-
-#if turbo_pcia_intr_fix != 0
-// .if ne turbo_pcia_intr_fix
-check_pcia_intr:
- mfpr r14, pt14 // fetch saved PCIA interrupt info
- beq r14, check_done // don't bother checking if no info
- mfpr r13, ipl // check the current IPL
- bic r13, 3, r25 // isolate ipl<5:2>
- cmpeq r25, 0x14, r25 // is it an I/O interrupt?
- beq r25, check_done // no, return
- and r13, 3, r25 // get I/O interrupt index
- extbl r14, r25, r13 // extract info for this interrupt
- beq r13, check_done // if no info, return
-
- // This is an RTI from a PCIA interrupt
- lda r12, 1(r31) // get initial bit mask
- sll r12, r25, r25 // shift to select interrupt index
- zap r14, r25, r14 // clear out info from this interrupt
- mtpr r14, pt14 // and save it
-
- and r13, 3, r25 // isolate HPC field
- subq r25, 1, r25 // subtract 1 to get HPC number
- srl r13, 2, r13 // generate base register address
- sll r13, 6, r13 // get slot/hose address bits
- lda r13, 0x38(r13) // insert other high bits
- sll r13, 28, r13 // shift high bits into position
-
- // Read the IPROGx register
- sll r25, 21, r14 // HPC address bit position
- or r13, r14, r14 // add in upper bits
- lda r14, 0x400(r14) // add in lower bits
- ldqp r14, 0(r14) // read IPROG
- srl r14, 4, r12 // check the In Progress bit
- blbc r12, 1f // skip if none in progress
- and r14, 0xf, r14 // isolate interrupt source
- lda r12, 1(r31) // make initial mask
- sll r12, r14, r14 // shift to make new intr source mask
- br r31, 2f
- // Write the SMPLIRQx register
-1: or r31, r31, r14 // default interrupt source mask
-2: GET_ADDR(r12, 0xffff, r31) // default SMPLIRQx data
- bic r12, r14, r12 // clear any interrupts in progres
-//orig lda r14, <0xbffc@-2>(r31) // get register address bits
- lda r14,(0xbffc>>2)(r31)
-
- sll r14, 10, r14 // shift into position
- or r14, r13, r14 // add in upper bits
- sll r25, 8, r25 // shift HPC number into position
- or r14, r25, r14 // add in lower bits
- stqp r12, 0(r14) // write SMPLIRQx register
- mb
- ldqp r12, 0(r14) // read it back
- bis r12, r12, r12 // touch register to insure completion
-
-check_done: // do these now and return
- lda r25, osfsf_c_size(sp) // get updated sp
- bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr
- br r31, pcia_check_return
-#endif
-
-
-// .sbttl KLUDGE_INITIAL_PCBB - PCB for Boot use only
-
- ALIGN_128
-
-kludge_initial_pcbb: // PCB is 128 bytes long
-// .repeat 16
-// .quad 0
-// .endr
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
- nop
- nop
- nop
- nop
-
-// .sbttl "SET_SC_BC_CTL subroutine"
-//
-// Subroutine to set the SC_CTL, BC_CONFIG, and BC_CTL registers and flush the Scache
-// There must be no outstanding memory references -- istream or dstream -- when
-// these registers are written. EV5 prefetcher is difficult to turn off. So,
-// this routine needs to be exactly 32 instructions long// the final jmp must
-// be in the last octaword of a page (prefetcher doesn't go across page)
-//
-//
-// Register expecations:
-// r0 base address of CBOX iprs
-// r5 value to set sc_ctl to (flush bit is added in)
-// r6 value to set bc_ctl to
-// r7 value to set bc_config to
-// r10 return address
-// r19 old sc_ctl value
-// r20 old value of bc_ctl
-// r21 old value of bc_config
-// r23 flush scache flag
-// Register usage:
-// r17 sc_ctl with flush bit cleared
-// r22 loop address
-//
-//
-#ifndef SIMOS
- align_page <32*4> // puts start of routine at next page boundary minus 32 longwords.
-#endif
-
-set_sc_bc_ctl:
-
-#ifndef SIMOS
- br r22, sc_ctl_loop //this branch must be in the same 4 instruction block as it's dest
-sc_ctl_loop:
-// XXX bugnion pvc$jsr scloop, dest=1
- mb
- mb
-
- bis r5, r23, r5 //r5 <- same sc_ctl with flush bit set (if flag set in r23)
-
- stqp r19, ev5__sc_ctl(r0) // write sc_ctl
- stqp r20, ev5__bc_ctl(r0) // write bc_ctl
- bis r31, r6, r20 // update r20 with new bc_ctl for 2nd time through loop
- stqp r21, bc_config(r0) // write bc_config register
- bis r31, r7, r21 // update r21 with new bc_config for 2nd time through loop
-
- bic r19, BIT(sc_ctl_v_sc_flush), r17 //r17 <- same sc_ctl without flush bit set
- //NOTE: only works because flush bit is in lower 16 bits
-
- wmb // don't merge with other writes
- stqp r17, ev5__sc_ctl(r0) // write sc_ctl without flush bit
- ldqp r17, ev5__sc_ctl(r0) // read sc_ctl
- bis r17, r17, r17 // stall until the data comes back
- bis r31, r5, r19 // update r19 with new sc_ctl for 2nd time through loop
-
- // fill with requisite number of nops (unops ok) to make exactly 32 instructions in loop
- t = 0
- .repeat 15
- unop
- t = t + 1
- .endr
- $opdef mnemonic= myjmp, -
- format= <custom=iregister, iregister, branch_offset>, -
- encoding= <26:31=0x1A, 21:25=%OP1,16:20=%OP2,14:15=0x00,0:13=%op3>
-
-// XXXbugnion pvc$jsr scloop
- myjmp r22,r22,sc_ctl_loop // first time, jump to sc_ctl_loop (hint will cause prefetcher to go to loop instead
- // of straight) // r22 gets sc_ctl_done
- // 2nd time, code continues at sc_ctl_done (I hope)
-sc_ctl_done:
-// XXX bugnion pvc$jsr scloop, dest=1
-// XXX bugnion pvc$jsr scbcctl
-#endif /*SIMOS*/
- ret r31, (r10) // return to where we came from
-
-
-.end
-
-
-
-
projects / gem5.git / commitdiff