arch-riscv: fault on mstatus accesses from lower privilege modes.

Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 04121513e3df434794c5a4d4d83d5ec16f84a481..d80c671f26a467691c571c726d0ee40860756bdd 100644 (file)
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -2,6 +2,7 @@
 
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016-2017 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -306,6 +307,18 @@ def template CSRExecute {{
             olddata = xc->readMiscReg(MISCREG_FFLAGS) |
                       (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
             break;
+          case CSR_MSTATUS: {
+            auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
+            if (pm != PrivilegeMode::PRV_M) {
+                std::string error = csprintf(
+                    "MSTATUS is only accessibly in machine mode\n");
+                fault = make_shared<IllegalInstFault>(error, machInst);
+                olddata = 0;
+            } else {
+                olddata = xc->readMiscReg(CSRData.at(csr).physIndex);
+            }
+            break;
+          }
           default:
             if (CSRData.find(csr) != CSRData.end()) {
                 olddata = xc->readMiscReg(CSRData.at(csr).physIndex);