clarify

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index a42df4b2c8a75f8a87faee8c8fd2d01576d78196..90dc372bef1bb296183ed730bedcbe349d8e79dd 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -124,7 +124,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 # Simple-V Architectural Resources
 
 * No new Interrupt types are required.
-  (**No modifications to existing Power ISA are required either**).
+  (**No modifications to existing Power ISA opcodes are required either**).
 * GPR FPR and CR Field Register extend to 128.  A future
   version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx]
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)