re PR target/70525 (generating 'vpandn' without the mode suffix, gnu as fails to...

	PR target/70525
	* config/i386/sse.md (*andnot<mode>3): Simplify assertions.
	Use vpandn<ssemodesuffix> for V16SI/V8DImode, vpandnq for
	V32HI/V64QImode, don't use <mask_operand3_1>, fix up formatting.
	(*andnot<mode>3_mask): Remove insn with VI12_AVX512VL iterator.

	* gcc.target/i386/pr70525.c: New test.

From-SVN: r234739

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b97f4ac848fa59e4452857ddc55fe688b507bea1..c0a8f729505b1c59e9660e2eea170f8929d5e5f0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2016-04-05  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/70525
+       * config/i386/sse.md (*andnot<mode>3): Simplify assertions.
+       Use vpandn<ssemodesuffix> for V16SI/V8DImode, vpandnq for
+       V32HI/V64QImode, don't use <mask_operand3_1>, fix up formatting.
+       (*andnot<mode>3_mask): Remove insn with VI12_AVX512VL iterator.
+
 2016-04-05  Richard Biener  <rguenther@suse.de>
 
        PR middle-end/70499
@@ -9,7 +17,7 @@
        PR ipa/66223
        * ipa-devirt.c (maybe_record_node): Do not optimize cxa_pure_virtual
        calls when sanitizing.
-       (possible_polymorphic_call_target_p)" FIx formating.
+       (possible_polymorphic_call_target_p): Fix formating.
 
 2016-04-04  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
            Jakub Jelinek <jakub@redhat.com>

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5fd650fde4ace23a91a88a7b3c8eb1595d2d216e..8e9d5ec7cd9e4d95acb7e652e0b7925a1f40fb1b 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -11377,45 +11377,46 @@
     case MODE_XI:
       gcc_assert (TARGET_AVX512F);
     case MODE_OI:
-      gcc_assert (TARGET_AVX2 || TARGET_AVX512VL);
+      gcc_assert (TARGET_AVX2);
     case MODE_TI:
-      gcc_assert (TARGET_SSE2 || TARGET_AVX512VL);
+      gcc_assert (TARGET_SSE2);
       switch (<MODE>mode)
-      {
-        case V16SImode:
-        case V8DImode:
-          if (TARGET_AVX512F)
-          {
-            tmp = "pandn<ssemodesuffix>";
-            break;
-          }
-        case V8SImode:
-        case V4DImode:
-        case V4SImode:
-        case V2DImode:
-          if (TARGET_AVX512VL)
-          {
-            tmp = "pandn<ssemodesuffix>";
-            break;
-          }
-        default:
-          tmp = TARGET_AVX512VL ? "pandnq" : "pandn";
-      }
+       {
+       case V64QImode:
+       case V32HImode:
+         /* There is no vpandnb or vpandnw instruction, nor vpandn for
+            512-bit vectors. Use vpandnq instead.  */
+         tmp = "pandnq";
+         break;
+       case V16SImode:
+       case V8DImode:
+         tmp = "pandn<ssemodesuffix>";
+         break;
+       case V8SImode:
+       case V4DImode:
+       case V4SImode:
+       case V2DImode:
+         tmp = TARGET_AVX512VL ? "pandn<ssemodesuffix>" : "pandn";
+         break;
+       default:
+         tmp = TARGET_AVX512VL ? "pandnq" : "pandn";
+         break;
+       }
       break;
 
-   case MODE_V16SF:
+    case MODE_V16SF:
       gcc_assert (TARGET_AVX512F);
-   case MODE_V8SF:
+    case MODE_V8SF:
       gcc_assert (TARGET_AVX);
-   case MODE_V4SF:
+    case MODE_V4SF:
       gcc_assert (TARGET_SSE);
 
       tmp = "andnps";
       break;
 
-   default:
+    default:
       gcc_unreachable ();
-   }
+    }
 
   switch (which_alternative)
     {
@@ -11423,7 +11424,7 @@
       ops = "%s\t{%%2, %%0|%%0, %%2}";
       break;
     case 1:
-      ops = "v%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
+      ops = "v%s\t{%%2, %%1, %%0|%%0, %%1, %%2}";
       break;
     default:
       gcc_unreachable ();
@@ -11473,21 +11474,6 @@
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "*andnot<mode>3_mask"
-  [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
-       (vec_merge:VI12_AVX512VL
-         (and:VI12_AVX512VL
-           (not:VI12_AVX512VL
-             (match_operand:VI12_AVX512VL 1 "register_operand" "v"))
-           (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm"))
-         (match_operand:VI12_AVX512VL 3 "vector_move_operand" "0C")
-         (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
-  "TARGET_AVX512BW"
-  "vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}";
-  [(set_attr "type" "sselog")
-   (set_attr "prefix" "evex")
-   (set_attr "mode" "<sseinsnmode>")])
-
 (define_expand "<code><mode>3"
   [(set (match_operand:VI 0 "register_operand")
        (any_logic:VI

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index baebdb0a21b89fde7fd678fe564e4b716d5e3bfd..f3d1a6e69198cad9f9a1072c1a054a07602a3806 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-04-05  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/70525
+       * gcc.target/i386/pr70525.c: New test.
+
 2016-04-05  Richard Biener  <rguenther@suse.de>
 
        PR middle-end/70499

diff --git a/gcc/testsuite/gcc.target/i386/pr70525.c b/gcc/testsuite/gcc.target/i386/pr70525.c
new file mode 100644 (file)
index 0000000..78ba752
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr70525.c
@@ -0,0 +1,32 @@
+/* PR target/70525 */
+/* { dg-do assemble { target avx512bw } } */
+/* { dg-options "-O2 -mavx512bw -mno-avx512vl" } */
+
+typedef char v64qi __attribute__ ((vector_size (64)));
+typedef short v32hi __attribute__ ((vector_size (64)));
+typedef int v16si __attribute__ ((vector_size (64)));
+typedef long long v8di __attribute__ ((vector_size (64)));
+
+v64qi
+f1 (v64qi x, v64qi y)
+{
+  return x & ~y;
+}
+
+v32hi
+f2 (v32hi x, v32hi y)
+{
+  return x & ~y;
+}
+
+v16si
+f3 (v16si x, v16si y)
+{
+  return x & ~y;
+}
+
+v8di
+f4 (v8di x, v8di y)
+{
+  return x & ~y;
+}