Merge pull request #60 from q3k/for-upstream/top-level-module-selection

Top module selection (for Verilator and Diamond)

diff --cc litex/build/sim/core/Makefile
index 782ac46b3024a494e8f60fcbafdf1ad0a967a0c0,8ccb4ff0e897a2ecd39a56a386e42eff33436b8f..733ea531bb003df9b75e15f103be9abac28c2e7e
--- 1/litex/build/sim/core/Makefile
--- 2/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@@ -24,8 -24,9 +24,9 @@@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.
  
  .PHONY: sim
  sim: mkdir $(OBJS_SIM)
 -      verilator -Wno-fatal -O3 --cc dut.v --exe \
 +      verilator -Wno-fatal -O3 --cc dut.v --top-module dut --exe \
                $(SRCS_SIM_CPP) $(OBJS_SIM) \
+               --top-module dut \
                -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
                -LDFLAGS "$(LDFLAGS)" \
                -trace $(INC_DIR)