+++ /dev/null
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A = x + y;
-assign B = x - y;
-
-endmodule
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-reset\r
-);\r
- output [7:0] out;\r
- input clk, reset;\r
- reg [7:0] out;\r
-\r
- always @(posedge clk, posedge reset)\r
- if (reset) begin\r
- out <= 8'b0 ;\r
- end else\r
- out <= out + 1;\r
-\r
-\r
-endmodule\r
-read_verilog counter.v
+read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module dff
- ( input d, clk, output reg q );
- always @( posedge clk )
- q <= d;
-endmodule
-
-module dffe
- ( input d, clk, en, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk )
- if ( en )
- q <= d;
-endmodule
-read_verilog dffs.v
+read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
+++ /dev/null
- module fsm (\r
- clock,\r
- reset,\r
- req_0,\r
- req_1,\r
- gnt_0,\r
- gnt_1\r
- );\r
- input clock,reset,req_0,req_1;\r
- output gnt_0,gnt_1;\r
- wire clock,reset,req_0,req_1;\r
- reg gnt_0,gnt_1;\r
-\r
- parameter SIZE = 3 ;\r
- parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
-\r
- reg [SIZE-1:0] state;\r
- reg [SIZE-1:0] next_state;\r
-\r
- always @ (posedge clock)\r
- begin : FSM\r
- if (reset == 1'b1) begin\r
- state <= #1 IDLE;\r
- gnt_0 <= 0;\r
- gnt_1 <= 0;\r
- end else\r
- case(state)\r
- IDLE : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- gnt_0 <= 1;\r
- end else if (req_1 == 1'b1) begin\r
- gnt_1 <= 1;\r
- state <= #1 GNT0;\r
- end else begin\r
- state <= #1 IDLE;\r
- end\r
- GNT0 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- end else begin\r
- gnt_0 <= 0;\r
- state <= #1 IDLE;\r
- end\r
- GNT1 : if (req_1 == 1'b1) begin\r
- state <= #1 GNT2;\r
- gnt_1 <= req_0;\r
- end\r
- GNT2 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT1;\r
- gnt_1 <= req_1;\r
- end\r
- default : state <= #1 IDLE;\r
- endcase\r
- end\r
-\r
-endmodule\r
-read_verilog fsm.v
+read_verilog ../common/fsm.v
hierarchy -top fsm
proc
#flatten
+++ /dev/null
-module latchp
- ( input d, clk, en, output reg q );
- always @*
- if ( en )
- q <= d;
-endmodule
-
-module latchn
- ( input d, clk, en, output reg q );
- always @*
- if ( !en )
- q <= d;
-endmodule
-
-module latchsr
- ( input d, clk, en, clr, pre, output reg q );
- always @*
- if ( clr )
- q <= 1'b0;
- else if ( pre )
- q <= 1'b1;
- else if ( en )
- q <= d;
-endmodule
-read_verilog latches.v
+read_verilog ../common/latches.v
design -save read
hierarchy -top latchp
--- /dev/null
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:AL_MAP_LUT1
+select -assert-count 6 t:AL_MAP_LUT2
+select -assert-count 2 t:AL_MAP_LUT4
+select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D
+++ /dev/null
-module mux2 (S,A,B,Y);
- input S;
- input A,B;
- output reg Y;
-
- always @(*)
- Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- 4 : Y = D[4];
- 5 : Y = D[5];
- 6 : Y = D[6];
- 7 : Y = D[7];
- endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- input [15:0] D;
- input [3:0] S;
- output Y;
-
-assign Y = D[S];
-
-endmodule
-read_verilog mux.v
+read_verilog ../common/mux.v
design -save read
hierarchy -top mux2
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-in\r
-);\r
- output [7:0] out;\r
- input signed clk, in;\r
- reg signed [7:0] out = 0;\r
-\r
- always @(posedge clk)\r
- begin\r
- out <= out >> 1;\r
- out[7] <= in;\r
- end\r
-\r
-endmodule\r
-read_verilog shifter.v
+read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module tristate (en, i, o);
- input en;
- input i;
- output o;
-
- assign o = en ? i : 1'bz;
-
-endmodule
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
flatten
--- /dev/null
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A = x + y;
+assign B = x - y;
+
+endmodule
--- /dev/null
+module adff
+ ( input d, clk, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk, posedge clr )
+ if ( clr )
+ q <= 1'b0;
+ else
+ q <= d;
+endmodule
+
+module adffn
+ ( input d, clk, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk, negedge clr )
+ if ( !clr )
+ q <= 1'b0;
+ else
+ q <= d;
+endmodule
+
+module dffs
+ ( input d, clk, pre, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk )
+ if ( pre )
+ q <= 1'b1;
+ else
+ q <= d;
+endmodule
+
+module ndffnr
+ ( input d, clk, pre, clr, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( negedge clk )
+ if ( !clr )
+ q <= 1'b0;
+ else
+ q <= d;
+endmodule
--- /dev/null
+module top (\r
+out,\r
+clk,\r
+reset\r
+);\r
+ output [7:0] out;\r
+ input clk, reset;\r
+ reg [7:0] out;\r
+\r
+ always @(posedge clk, posedge reset)\r
+ if (reset) begin\r
+ out <= 8'b0 ;\r
+ end else\r
+ out <= out + 1;\r
+\r
+\r
+endmodule\r
--- /dev/null
+module dff
+ ( input d, clk, output reg q );
+ always @( posedge clk )
+ q <= d;
+endmodule
+
+module dffe
+ ( input d, clk, en, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk )
+ if ( en )
+ q <= d;
+endmodule
--- /dev/null
+ module fsm (\r
+ clock,\r
+ reset,\r
+ req_0,\r
+ req_1,\r
+ gnt_0,\r
+ gnt_1\r
+ );\r
+ input clock,reset,req_0,req_1;\r
+ output gnt_0,gnt_1;\r
+ wire clock,reset,req_0,req_1;\r
+ reg gnt_0,gnt_1;\r
+\r
+ parameter SIZE = 3 ;\r
+ parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
+\r
+ reg [SIZE-1:0] state;\r
+ reg [SIZE-1:0] next_state;\r
+\r
+ always @ (posedge clock)\r
+ begin : FSM\r
+ if (reset == 1'b1) begin\r
+ state <= #1 IDLE;\r
+ gnt_0 <= 0;\r
+ gnt_1 <= 0;\r
+ end else\r
+ case(state)\r
+ IDLE : if (req_0 == 1'b1) begin\r
+ state <= #1 GNT0;\r
+ gnt_0 <= 1;\r
+ end else if (req_1 == 1'b1) begin\r
+ gnt_1 <= 1;\r
+ state <= #1 GNT0;\r
+ end else begin\r
+ state <= #1 IDLE;\r
+ end\r
+ GNT0 : if (req_0 == 1'b1) begin\r
+ state <= #1 GNT0;\r
+ end else begin\r
+ gnt_0 <= 0;\r
+ state <= #1 IDLE;\r
+ end\r
+ GNT1 : if (req_1 == 1'b1) begin\r
+ state <= #1 GNT2;\r
+ gnt_1 <= req_0;\r
+ end\r
+ GNT2 : if (req_0 == 1'b1) begin\r
+ state <= #1 GNT1;\r
+ gnt_1 <= req_1;\r
+ end\r
+ default : state <= #1 IDLE;\r
+ endcase\r
+ end\r
+\r
+endmodule\r
--- /dev/null
+module latchp
+ ( input d, clk, en, output reg q );
+ always @*
+ if ( en )
+ q <= d;
+endmodule
+
+module latchn
+ ( input d, clk, en, output reg q );
+ always @*
+ if ( !en )
+ q <= d;
+endmodule
+
+module latchsr
+ ( input d, clk, en, clr, pre, output reg q );
+ always @*
+ if ( clr )
+ q <= 1'b0;
+ else if ( pre )
+ q <= 1'b1;
+ else if ( en )
+ q <= d;
+endmodule
--- /dev/null
+module top
+(
+ input [0:7] in,
+ output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+ );
+
+ assign B1 = in[0] & in[1];
+ assign B2 = in[0] | in[1];
+ assign B3 = in[0] ~& in[1];
+ assign B4 = in[0] ~| in[1];
+ assign B5 = in[0] ^ in[1];
+ assign B6 = in[0] ~^ in[1];
+ assign B7 = ~in[0];
+ assign B8 = in[0];
+ assign B9 = in[0:1] && in [2:3];
+ assign B10 = in[0:1] || in [2:3];
+
+endmodule
--- /dev/null
+module top
+(
+ input [5:0] x,
+ input [5:0] y,
+
+ output [11:0] A,
+ );
+
+assign A = x * y;
+
+endmodule
--- /dev/null
+module mux2 (S,A,B,Y);
+ input S;
+ input A,B;
+ output reg Y;
+
+ always @(*)
+ Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ 4 : Y = D[4];
+ 5 : Y = D[5];
+ 6 : Y = D[6];
+ 7 : Y = D[7];
+ endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ input [15:0] D;
+ input [3:0] S;
+ output Y;
+
+assign Y = D[S];
+
+endmodule
--- /dev/null
+module top (\r
+out,\r
+clk,\r
+in\r
+);\r
+ output [7:0] out;\r
+ input signed clk, in;\r
+ reg signed [7:0] out = 0;\r
+\r
+ always @(posedge clk)\r
+ begin\r
+ out <= out >> 1;\r
+ out[7] <= in;\r
+ end\r
+\r
+endmodule\r
--- /dev/null
+module tristate (en, i, o);
+ input en;
+ input i;
+ output reg o;
+
+ always @(en or i)
+ o <= (en)? i : 1'bZ;
+endmodule
+++ /dev/null
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A = x + y;
-assign B = x - y;
-
-endmodule
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+++ /dev/null
-module adff
- ( input d, clk, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, posedge clr )
- if ( clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-
-module adffn
- ( input d, clk, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, negedge clr )
- if ( !clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-
-module dffs
- ( input d, clk, pre, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk )
- if ( pre )
- q <= 1'b1;
- else
- q <= d;
-endmodule
-
-module ndffnr
- ( input d, clk, pre, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( negedge clk )
- if ( !clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-read_verilog adffs.v
+read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-reset\r
-);\r
- output [7:0] out;\r
- input clk, reset;\r
- reg [7:0] out;\r
-\r
- always @(posedge clk, posedge reset)\r
- if (reset) begin\r
- out <= 8'b0 ;\r
- end else\r
- out <= out + 1;\r
-\r
-\r
-endmodule\r
-read_verilog counter.v
+read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module dff
- ( input d, clk, output reg q );
- always @( posedge clk )
- q <= d;
-endmodule
-
-module dffe
- ( input d, clk, en, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk )
- if ( en )
- q <= d;
-endmodule
-read_verilog dffs.v
+read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
+++ /dev/null
- module fsm (\r
- clock,\r
- reset,\r
- req_0,\r
- req_1,\r
- gnt_0,\r
- gnt_1\r
- );\r
- input clock,reset,req_0,req_1;\r
- output gnt_0,gnt_1;\r
- wire clock,reset,req_0,req_1;\r
- reg gnt_0,gnt_1;\r
-\r
- parameter SIZE = 3 ;\r
- parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
-\r
- reg [SIZE-1:0] state;\r
- reg [SIZE-1:0] next_state;\r
-\r
- always @ (posedge clock)\r
- begin : FSM\r
- if (reset == 1'b1) begin\r
- state <= #1 IDLE;\r
- gnt_0 <= 0;\r
- gnt_1 <= 0;\r
- end else\r
- case(state)\r
- IDLE : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- gnt_0 <= 1;\r
- end else if (req_1 == 1'b1) begin\r
- gnt_1 <= 1;\r
- state <= #1 GNT0;\r
- end else begin\r
- state <= #1 IDLE;\r
- end\r
- GNT0 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- end else begin\r
- gnt_0 <= 0;\r
- state <= #1 IDLE;\r
- end\r
- GNT1 : if (req_1 == 1'b1) begin\r
- state <= #1 GNT2;\r
- gnt_1 <= req_0;\r
- end\r
- GNT2 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT1;\r
- gnt_1 <= req_1;\r
- end\r
- default : state <= #1 IDLE;\r
- endcase\r
- end\r
-\r
-endmodule\r
-read_verilog fsm.v
+read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
+++ /dev/null
-module latchp
- ( input d, clk, en, output reg q );
- always @*
- if ( en )
- q <= d;
-endmodule
-
-module latchn
- ( input d, clk, en, output reg q );
- always @*
- if ( !en )
- q <= d;
-endmodule
-
-module latchsr
- ( input d, clk, en, clr, pre, output reg q );
- always @*
- if ( clr )
- q <= 1'b0;
- else if ( pre )
- q <= 1'b1;
- else if ( en )
- q <= d;
-endmodule
-
-read_verilog latches.v
+read_verilog ../common/latches.v
design -save read
hierarchy -top latchp
+++ /dev/null
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
- assign B1 = in[0] & in[1];
- assign B2 = in[0] | in[1];
- assign B3 = in[0] ~& in[1];
- assign B4 = in[0] ~| in[1];
- assign B5 = in[0] ^ in[1];
- assign B6 = in[0] ~^ in[1];
- assign B7 = ~in[0];
- assign B8 = in[0];
- assign B9 = in[0:1] && in [2:3];
- assign B10 = in[0:1] || in [2:3];
-
-endmodule
-read_verilog logic.v
+read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+++ /dev/null
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A = x * y;
-
-endmodule
-read_verilog mul.v
+read_verilog ../common/mul.v
hierarchy -top top
proc
# Blocked by issue #1358 (Missing ECP5 simulation models)
+++ /dev/null
-module mux2 (S,A,B,Y);
- input S;
- input A,B;
- output reg Y;
-
- always @(*)
- Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- 4 : Y = D[4];
- 5 : Y = D[5];
- 6 : Y = D[6];
- 7 : Y = D[7];
- endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- input [15:0] D;
- input [3:0] S;
- output Y;
-
-assign Y = D[S];
-
-endmodule
-
-read_verilog mux.v
+read_verilog ../common/mux.v
design -save read
hierarchy -top mux2
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-in\r
-);\r
- output [7:0] out;\r
- input signed clk, in;\r
- reg signed [7:0] out = 0;\r
-\r
- always @(posedge clk)\r
- begin\r
- out <= out >> 1;\r
- out[7] <= in;\r
- end\r
-\r
-endmodule\r
-read_verilog shifter.v
+read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module tristate (en, i, o);
- input en;
- input i;
- output o;
-
- assign o = en ? i : 1'bz;
-
-endmodule
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
flatten
+++ /dev/null
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A = x + y;
-assign B = x - y;
-
-endmodule
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+++ /dev/null
-module adff
- ( input d, clk, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, posedge clr )
- if ( clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-
-module adffn
- ( input d, clk, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, negedge clr )
- if ( !clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-
-module dffs
- ( input d, clk, pre, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk )
- if ( pre )
- q <= 1'b1;
- else
- q <= d;
-endmodule
-
-module ndffnr
- ( input d, clk, pre, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( negedge clk )
- if ( !clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-read_verilog adffs.v
+read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-reset\r
-);\r
- output [7:0] out;\r
- input clk, reset;\r
- reg [7:0] out;\r
-\r
- always @(posedge clk, posedge reset)\r
- if (reset) begin\r
- out <= 8'b0 ;\r
- end else\r
- out <= out + 1;\r
-\r
-\r
-endmodule\r
-read_verilog counter.v
+read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module dff
- ( input d, clk, output reg q );
- always @( posedge clk )
- q <= d;
-endmodule
-
-module dffe
- ( input d, clk, en, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk )
- if ( en )
- q <= d;
-endmodule
-read_verilog dffs.v
+read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
+++ /dev/null
- module fsm (\r
- clock,\r
- reset,\r
- req_0,\r
- req_1,\r
- gnt_0,\r
- gnt_1\r
- );\r
- input clock,reset,req_0,req_1;\r
- output gnt_0,gnt_1;\r
- wire clock,reset,req_0,req_1;\r
- reg gnt_0,gnt_1;\r
-\r
- parameter SIZE = 3 ;\r
- parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
-\r
- reg [SIZE-1:0] state;\r
- reg [SIZE-1:0] next_state;\r
-\r
- always @ (posedge clock)\r
- begin : FSM\r
- if (reset == 1'b1) begin\r
- state <= #1 IDLE;\r
- gnt_0 <= 0;\r
- gnt_1 <= 0;\r
- end else\r
- case(state)\r
- IDLE : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- gnt_0 <= 1;\r
- end else if (req_1 == 1'b1) begin\r
- gnt_1 <= 1;\r
- state <= #1 GNT0;\r
- end else begin\r
- state <= #1 IDLE;\r
- end\r
- GNT0 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- end else begin\r
- gnt_0 <= 0;\r
- state <= #1 IDLE;\r
- end\r
- GNT1 : if (req_1 == 1'b1) begin\r
- state <= #1 GNT2;\r
- gnt_1 <= req_0;\r
- end\r
- GNT2 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT1;\r
- gnt_1 <= req_1;\r
- end\r
- default : state <= #1 IDLE;\r
- endcase\r
- end\r
-\r
-endmodule\r
-read_verilog fsm.v
+read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
+++ /dev/null
-module latchp
- ( input d, clk, en, output reg q );
- always @*
- if ( en )
- q <= d;
-endmodule
-
-module latchn
- ( input d, clk, en, output reg q );
- always @*
- if ( !en )
- q <= d;
-endmodule
-
-module latchsr
- ( input d, clk, en, clr, pre, output reg q );
- always @*
- if ( clr )
- q <= 1'b0;
- else if ( pre )
- q <= 1'b1;
- else if ( en )
- q <= d;
-endmodule
-read_verilog latches.v
+read_verilog ../common/latches.v
design -save read
hierarchy -top latchp
+++ /dev/null
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
- assign B1 = in[0] & in[1];
- assign B2 = in[0] | in[1];
- assign B3 = in[0] ~& in[1];
- assign B4 = in[0] ~| in[1];
- assign B5 = in[0] ^ in[1];
- assign B6 = in[0] ~^ in[1];
- assign B7 = ~in[0];
- assign B8 = in[0];
- assign B9 = in[0:1] && in [2:3];
- assign B10 = in[0:1] || in [2:3];
-
-endmodule
-read_verilog logic.v
+read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+++ /dev/null
-module mux2 (S,A,B,Y);
- input S;
- input A,B;
- output reg Y;
-
- always @(*)
- Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- 4 : Y = D[4];
- 5 : Y = D[5];
- 6 : Y = D[6];
- 7 : Y = D[7];
- endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- input [15:0] D;
- input [3:0] S;
- output Y;
-
-assign Y = D[S];
-
-endmodule
-read_verilog mux.v
+read_verilog ../common/mux.v
design -save read
hierarchy -top mux2
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-in\r
-);\r
- output [7:0] out;\r
- input signed clk, in;\r
- reg signed [7:0] out = 0;\r
-\r
- always @(posedge clk)\r
- begin\r
- out <= out << 1;\r
- out[7] <= in;\r
- end\r
-\r
-endmodule\r
-read_verilog shifter.v
+read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module tristate (en, i, o);
- input en;
- input i;
- output reg o;
-
- always @(en or i)
- o <= (en)? i : 1'bZ;
-endmodule
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
+++ /dev/null
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A = x + y;
-assign B = x - y;
-
-endmodule
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+++ /dev/null
-module adff
- ( input d, clk, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, posedge clr )
- if ( clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-
-module adffn
- ( input d, clk, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, negedge clr )
- if ( !clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-
-module dffs
- ( input d, clk, pre, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, posedge pre )
- if ( pre )
- q <= 1'b1;
- else
- q <= d;
-endmodule
-
-module ndffnr
- ( input d, clk, pre, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( negedge clk, negedge pre )
- if ( !pre )
- q <= 1'b1;
- else
- q <= d;
-endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
- .clk (clk ),
- .clr (clr),
- .pre (pre),
- .d (a ),
- .q (b )
- );
-
-ndffnr u_ndffnr (
- .clk (clk ),
- .clr (clr),
- .pre (pre),
- .d (a ),
- .q (b1 )
- );
-
-adff u_adff (
- .clk (clk ),
- .clr (clr),
- .d (a ),
- .q (b2 )
- );
-
-adffn u_adffn (
- .clk (clk ),
- .clr (clr),
- .d (a ),
- .q (b3 )
- );
-
-endmodule
-read_verilog adffs.v
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
proc
-flatten
-equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNS
-select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFS
-select -assert-count 2 t:SB_LUT4
-select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFR
+select -assert-none t:SB_DFFR %% t:* %D
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFR
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFSS
+select -assert-none t:SB_DFFSS %% t:* %D
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFNSR
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-reset\r
-);\r
- output [7:0] out;\r
- input clk, reset;\r
- reg [7:0] out;\r
-\r
- always @(posedge clk, posedge reset)\r
- if (reset) begin\r
- out <= 8'b0 ;\r
- end else\r
- out <= out + 1;\r
-\r
-\r
-endmodule\r
-read_verilog counter.v
+read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module dff
- ( input d, clk, output reg q );
- always @( posedge clk )
- q <= d;
-endmodule
-
-module dffe
- ( input d, clk, en, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk )
- if ( en )
- q <= d;
-endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
- .clk (clk ),
- .d (a ),
- .q (b )
- );
-
-dffe u_ndffe (
- .clk (clk ),
- .en (en),
- .d (a ),
- .q (b1 )
- );
-
-endmodule
-read_verilog dffs.v
-hierarchy -top top
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
proc
-flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF
+select -assert-none t:SB_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
+select -assert-none t:SB_DFFE %% t:* %D
\ No newline at end of file
+++ /dev/null
- module fsm (\r
- clock,\r
- reset,\r
- req_0,\r
- req_1,\r
- gnt_0,\r
- gnt_1\r
- );\r
- input clock,reset,req_0,req_1;\r
- output gnt_0,gnt_1;\r
- wire clock,reset,req_0,req_1;\r
- reg gnt_0,gnt_1;\r
-\r
- parameter SIZE = 3 ;\r
- parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
-\r
- reg [SIZE-1:0] state;\r
- reg [SIZE-1:0] next_state;\r
-\r
- always @ (posedge clock)\r
- begin : FSM\r
- if (reset == 1'b1) begin\r
- state <= #1 IDLE;\r
- gnt_0 <= 0;\r
- gnt_1 <= 0;\r
- end else\r
- case(state)\r
- IDLE : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- gnt_0 <= 1;\r
- end else if (req_1 == 1'b1) begin\r
- gnt_1 <= 1;\r
- state <= #1 GNT0;\r
- end else begin\r
- state <= #1 IDLE;\r
- end\r
- GNT0 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- end else begin\r
- gnt_0 <= 0;\r
- state <= #1 IDLE;\r
- end\r
- GNT1 : if (req_1 == 1'b1) begin\r
- state <= #1 GNT2;\r
- gnt_1 <= req_0;\r
- end\r
- GNT2 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT1;\r
- gnt_1 <= req_1;\r
- end\r
- default : state <= #1 IDLE;\r
- endcase\r
- end\r
-\r
- endmodule\r
-\r
- module top (\r
-input clk,\r
-input rst,\r
-input a,\r
-input b,\r
-output g0,\r
-output g1\r
-);\r
-\r
-fsm u_fsm ( .clock(clk),\r
- .reset(rst),\r
- .req_0(a),\r
- .req_1(b),\r
- .gnt_0(g0),\r
- .gnt_1(g1));\r
-\r
-endmodule\r
-read_verilog fsm.v
-hierarchy -top top
+read_verilog ../common/fsm.v
+hierarchy -top fsm
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_DFFESR
select -assert-count 2 t:SB_DFFSR
+++ /dev/null
-module latchp
- ( input d, clk, en, output reg q );
- always @*
- if ( en )
- q <= d;
-endmodule
-
-module latchn
- ( input d, clk, en, output reg q );
- always @*
- if ( !en )
- q <= d;
-endmodule
-
-module latchsr
- ( input d, clk, en, clr, pre, output reg q );
- always @*
- if ( clr )
- q <= 1'b0;
- else if ( pre )
- q <= 1'b1;
- else if ( en )
- q <= d;
-endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
- .en (clk ),
- .d (a ),
- .q (b )
- );
-
-
-latchn u_latchn (
- .en (clk ),
- .d (a ),
- .q (b1 )
- );
-
-
-latchsr u_latchsr (
- .en (clk ),
- .clr (clr),
- .pre (pre),
- .d (a ),
- .q (b2 )
- );
-
-endmodule
-read_verilog latches.v
+read_verilog ../common/latches.v
+design -save read
+hierarchy -top latchp
proc
-flatten
# Can't run any sort of equivalence check because latches are blown to LUTs
-#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+synth_ice40
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ice40
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
-#design -load preopt
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40
-cd top
-select -assert-count 4 t:SB_LUT4
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:SB_LUT4
+
select -assert-none t:SB_LUT4 %% t:* %D
+++ /dev/null
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
- assign B1 = in[0] & in[1];
- assign B2 = in[0] | in[1];
- assign B3 = in[0] ~& in[1];
- assign B4 = in[0] ~| in[1];
- assign B5 = in[0] ^ in[1];
- assign B6 = in[0] ~^ in[1];
- assign B7 = ~in[0];
- assign B8 = in[0];
- assign B9 = in[0:1] && in [2:3];
- assign B10 = in[0:1] || in [2:3];
-
-endmodule
-read_verilog logic.v
+read_verilog ../common/logic.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+++ /dev/null
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A = x * y;
-
-endmodule
-read_verilog mul.v
+read_verilog ../common/mul.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+++ /dev/null
-module mux2 (S,A,B,Y);
- input S;
- input A,B;
- output reg Y;
-
- always @(*)
- Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- 4 : Y = D[4];
- 5 : Y = D[5];
- 6 : Y = D[6];
- 7 : Y = D[7];
- endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- input [15:0] D;
- input [3:0] S;
- output Y;
-
-assign Y = D[S];
-
-endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
- .S (S[0]),
- .A (D[0]),
- .B (D[1]),
- .Y (M2)
- );
-
-
-mux4 u_mux4 (
- .S (S[1:0]),
- .D (D[3:0]),
- .Y (M4)
- );
-
-mux8 u_mux8 (
- .S (S[2:0]),
- .D (D[7:0]),
- .Y (M8)
- );
-
-mux16 u_mux16 (
- .S (S[3:0]),
- .D (D[15:0]),
- .Y (M16)
- );
-
-endmodule
-read_verilog mux.v
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
proc
-flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 19 t:SB_LUT4
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 2 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 5 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 11 t:SB_LUT4
+
select -assert-none t:SB_LUT4 %% t:* %D
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-in\r
-);\r
- output [7:0] out;\r
- input signed clk, in;\r
- reg signed [7:0] out = 0;\r
-\r
- always @(posedge clk)\r
- begin\r
-`ifndef BUG\r
- out <= out >> 1;\r
- out[7] <= in;\r
-`else\r
-\r
- out <= out << 1;\r
- out[7] <= in;\r
-`endif\r
- end\r
-\r
-endmodule\r
-read_verilog shifter.v
+read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module tristate (en, i, o);
- input en;
- input i;
- output o;
-
- assign o = en ? i : 1'bz;
-
-endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
- .en (en ),
- .i (a ),
- .o (b )
- );
-
-endmodule
-read_verilog tribuf.v
-hierarchy -top top
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
proc
+tribuf
flatten
+synth
equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D
+++ /dev/null
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A = x + y;
-assign B = x - y;
-
-endmodule
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+++ /dev/null
-module adff
- ( input d, clk, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, posedge clr )
- if ( clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-
-module adffn
- ( input d, clk, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk, negedge clr )
- if ( !clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-
-module dffs
- ( input d, clk, pre, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk )
- if ( pre )
- q <= 1'b1;
- else
- q <= d;
-endmodule
-
-module ndffnr
- ( input d, clk, pre, clr, output reg q );
- initial begin
- q = 0;
- end
- always @( negedge clk )
- if ( !clr )
- q <= 1'b0;
- else
- q <= d;
-endmodule
-read_verilog adffs.v
+read_verilog ../common/adffs.v
design -save read
hierarchy -top adff
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-reset\r
-);\r
- output [7:0] out;\r
- input clk, reset;\r
- reg [7:0] out;\r
-\r
- always @(posedge clk, posedge reset)\r
- if (reset) begin\r
- out <= 8'b0 ;\r
- end else\r
- out <= out + 1;\r
-\r
-\r
-endmodule\r
-read_verilog counter.v
+read_verilog ../common/counter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module dff
- ( input d, clk, output reg q );
- always @( posedge clk )
- q <= d;
-endmodule
-
-module dffe
- ( input d, clk, en, output reg q );
- initial begin
- q = 0;
- end
- always @( posedge clk )
- if ( en )
- q <= d;
-endmodule
-read_verilog dffs.v
+read_verilog ../common/dffs.v
design -save read
hierarchy -top dff
+++ /dev/null
- module fsm (\r
- clock,\r
- reset,\r
- req_0,\r
- req_1,\r
- gnt_0,\r
- gnt_1\r
- );\r
- input clock,reset,req_0,req_1;\r
- output gnt_0,gnt_1;\r
- wire clock,reset,req_0,req_1;\r
- reg gnt_0,gnt_1;\r
-\r
- parameter SIZE = 3 ;\r
- parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
-\r
- reg [SIZE-1:0] state;\r
- reg [SIZE-1:0] next_state;\r
-\r
- always @ (posedge clock)\r
- begin : FSM\r
- if (reset == 1'b1) begin\r
- state <= #1 IDLE;\r
- gnt_0 <= 0;\r
- gnt_1 <= 0;\r
- end else\r
- case(state)\r
- IDLE : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- gnt_0 <= 1;\r
- end else if (req_1 == 1'b1) begin\r
- gnt_1 <= 1;\r
- state <= #1 GNT0;\r
- end else begin\r
- state <= #1 IDLE;\r
- end\r
- GNT0 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT0;\r
- end else begin\r
- gnt_0 <= 0;\r
- state <= #1 IDLE;\r
- end\r
- GNT1 : if (req_1 == 1'b1) begin\r
- state <= #1 GNT2;\r
- gnt_1 <= req_0;\r
- end\r
- GNT2 : if (req_0 == 1'b1) begin\r
- state <= #1 GNT1;\r
- gnt_1 <= req_1;\r
- end\r
- default : state <= #1 IDLE;\r
- endcase\r
- end\r
-\r
-endmodule\r
-read_verilog fsm.v
+read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten
+++ /dev/null
-module latchp
- ( input d, clk, en, output reg q );
- always @*
- if ( en )
- q <= d;
-endmodule
-
-module latchn
- ( input d, clk, en, output reg q );
- always @*
- if ( !en )
- q <= d;
-endmodule
-
-module latchsr
- ( input d, clk, en, clr, pre, output reg q );
- always @*
- if ( clr )
- q <= 1'b0;
- else if ( pre )
- q <= 1'b1;
- else if ( en )
- q <= d;
-endmodule
-read_verilog latches.v
+read_verilog ../common/latches.v
design -save read
hierarchy -top latchp
+++ /dev/null
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
- assign B1 = in[0] & in[1];
- assign B2 = in[0] | in[1];
- assign B3 = in[0] ~& in[1];
- assign B4 = in[0] ~| in[1];
- assign B5 = in[0] ^ in[1];
- assign B6 = in[0] ~^ in[1];
- assign B7 = ~in[0];
- assign B8 = in[0];
- assign B9 = in[0:1] && in [2:3];
- assign B10 = in[0:1] || in [2:3];
-
-endmodule
-read_verilog logic.v
+read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+++ /dev/null
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A = x * y;
-
-endmodule
-read_verilog mul.v
+read_verilog ../common/mul.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+++ /dev/null
-module mux2 (S,A,B,Y);
- input S;
- input A,B;
- output reg Y;
-
- always @(*)
- Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
- case( S )
- 0 : Y = D[0];
- 1 : Y = D[1];
- 2 : Y = D[2];
- 3 : Y = D[3];
- 4 : Y = D[4];
- 5 : Y = D[5];
- 6 : Y = D[6];
- 7 : Y = D[7];
- endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- input [15:0] D;
- input [3:0] S;
- output Y;
-
-assign Y = D[S];
-
-endmodule
-read_verilog mux.v
+read_verilog ../common/mux.v
design -save read
hierarchy -top mux2
+++ /dev/null
-module top (\r
-out,\r
-clk,\r
-in\r
-);\r
- output [7:0] out;\r
- input signed clk, in;\r
- reg signed [7:0] out = 0;\r
-\r
- always @(posedge clk)\r
- begin\r
- out <= out >> 1;\r
- out[7] <= in;\r
- end\r
-\r
-endmodule\r
-read_verilog shifter.v
+read_verilog ../common/shifter.v
hierarchy -top top
proc
flatten
+++ /dev/null
-module tristate (en, i, o);
- input en;
- input i;
- output reg o;
-
- always @(en or i)
- o <= (en)? i : 1'bZ;
-endmodule
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
hierarchy -top tristate
proc
tribuf
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