ISA: Replace the translate functions in the TLBs with translateAtomic.

diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index be02293d60fb5f0cf598595dcd836fa9542632e3..82d4109876ad80c9e664c591795c54480140b618 100644 (file)
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -317,7 +317,7 @@ ITB::regStats()
 }
 
 Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
     if (FULL_SYSTEM && PcPAL(req->getPC()))
@@ -479,7 +479,7 @@ DTB::regStats()
 }
 
 Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
 {
     Addr pc = tc->readPC();
 

diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 9267aa57345be1f705ecc4885f9e8334df033134..f5d2dbca9365f0ecb7e6e36704f7a6813074d85d 100644 (file)
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -131,7 +131,7 @@ class ITB : public TLB
     ITB(const Params *p);
     virtual void regStats();
 
-    Fault translate(RequestPtr &req, ThreadContext *tc);
+    Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
 };
 
 class DTB : public TLB
@@ -155,7 +155,7 @@ class DTB : public TLB
     DTB(const Params *p);
     virtual void regStats();
 
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
 };
 
 } // namespace AlphaISA

diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index e91da4eeae508a34c55dbe7d7c4622dcc38001a5..db21c791937b860f9d2285cb46c5ef612296c3f9 100644 (file)
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -310,7 +310,7 @@ TLB::regStats()
 }
 
 Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -427,7 +427,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
 }
 
 Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 4a8fc32acaad156574db7e6584cec30e97cb9237..acb393116781cef7732178e119a74ea1877e8d18 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -145,7 +145,7 @@ class ITB : public TLB {
     typedef MipsTLBParams Params;
     ITB(const Params *p);
 
-    Fault translate(RequestPtr &req, ThreadContext *tc);
+    Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
 };
 
 class DTB : public TLB {
@@ -153,7 +153,8 @@ class DTB : public TLB {
     typedef MipsTLBParams Params;
     DTB(const Params *p);
 
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write = false);
+    Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
+            bool write = false);
 };
 
 class UTB : public ITB, public DTB {

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 9e5230674af2c3d6aa342633feb8b604cf305065..683d916df403433892471822ddf4598b8851ba13 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -436,7 +436,7 @@ DTB::writeSfsr(Addr a, bool write, ContextType ct,
 }
 
 Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
 {
     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 
@@ -549,7 +549,7 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
 }
 
 Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
 {
     /*
      * @todo this could really use some profiling and fixing to make

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 504a40cbbd65281e9d26b181cc4b13d1f2a5e420..d563772e6ac8ea69c7dd294764be24c53388b17d 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -177,7 +177,7 @@ class ITB : public TLB
         cacheEntry = NULL;
     }
 
-    Fault translate(RequestPtr &req, ThreadContext *tc);
+    Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
   private:
     void writeSfsr(bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);
@@ -199,7 +199,7 @@ class DTB : public TLB
         cacheEntry[1] = NULL;
     }
 
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
 #if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 34829848c96a13abe033f254b1502a9a0468478c..33017a6aadf41ec1c58f18a42aa10d8935a3b45d 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -190,7 +190,8 @@ TLB::demapPage(Addr va, uint64_t asn)
 
 template<class TlbFault>
 Fault
-TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
+TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
+        bool write, bool execute)
 {
     Addr vaddr = req->getVaddr();
     DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
@@ -662,15 +663,15 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
 };
 
 Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
 {
-    return TLB::translate<FakeDTLBFault>(req, tc, write, false);
+    return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
 }
 
 Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc)
+ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
 {
-    return TLB::translate<FakeITLBFault>(req, tc, false, true);
+    return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
 }
 
 #if FULL_SYSTEM

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 56d635a90b140854fcad7333c4908d414d3e08e5..91bb4a761306ca0a7553e0825675d800a96560d2 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -138,7 +138,7 @@ namespace X86ISA
         EntryList entryList;
 
         template<class TlbFault>
-        Fault translate(RequestPtr &req, ThreadContext *tc,
+        Fault translateAtomic(RequestPtr &req, ThreadContext *tc,
                 bool write, bool execute);
 
       public:
@@ -159,7 +159,7 @@ namespace X86ISA
             _allowNX = false;
         }
 
-        Fault translate(RequestPtr &req, ThreadContext *tc);
+        Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
 
         friend class DTB;
     };
@@ -172,7 +172,7 @@ namespace X86ISA
         {
             _allowNX = true;
         }
-        Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+        Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
 #if FULL_SYSTEM
         Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
         Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index f58bf7cf855ed832f39e8b227bef43d4c5e8e685..41c57cf3925089aea380fb359de36a227ecc8381 100644 (file)
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -860,7 +860,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
     req->setThreadContext(thread->contextId(), threadNumber);
 
-    fault = cpu->dtb->translate(req, thread->getTC(), false);
+    fault = cpu->dtb->translateAtomic(req, thread->getTC(), false);
 
     if (req->isUncacheable())
         isUncacheable = true;
@@ -916,7 +916,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
     req->setThreadContext(thread->contextId(), threadNumber);
 
-    fault = cpu->dtb->translate(req, thread->getTC(), true);
+    fault = cpu->dtb->translateAtomic(req, thread->getTC(), true);
 
     if (req->isUncacheable())
         isUncacheable = true;

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index e530e601414eea2bad0ae9331d641a8e8e87d9dd..14777bc126de5a95c96f205353219b9c8843706f 100644 (file)
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -159,7 +159,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags)
     memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
     // translate to physical address
-    dtb->translate(memReq, tc, false);
+    dtb->translateAtomic(memReq, tc, false);
 
     PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
 
@@ -229,7 +229,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 
     // translate to physical address
-    dtb->translate(memReq, tc, true);
+    dtb->translateAtomic(memReq, tc, true);
 
     // Can compare the write data and result only if it's cacheable,
     // not a store conditional, or is a store conditional that

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index e1ecc151ccafa71b1fede53ce240e2db2082e909..26571ed6886f51c74ee86b46be26b9b03eca2cce 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -155,7 +155,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
                              fetch_PC, thread->contextId(),
                              inst->threadNumber);
 
-        bool succeeded = itb->translate(memReq, thread);
+        bool succeeded = itb->translateAtomic(memReq, thread);
 
         if (!succeeded) {
             if (inst->getFault() == NoFault) {

diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 4eeb4727b55c327bf63884b35d9949b77321f0df..321ac90f80f8d794a9cf66100096ea345341b488 100644 (file)
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -98,7 +98,7 @@ TLBUnit::execute(int slot_idx)
       case FetchLookup:
         {
             tlb_req->fault =
-                this->cpu->itb->translate(tlb_req->memReq,
+                this->cpu->itb->translateAtomic(tlb_req->memReq,
                         cpu->thread[tid]->getTC());
 
             if (tlb_req->fault != NoFault) {
@@ -129,7 +129,7 @@ TLBUnit::execute(int slot_idx)
                     tid, seq_num, tlb_req->memReq->getVaddr());
 
             tlb_req->fault =
-                this->cpu->itb->translate(tlb_req->memReq,
+                this->cpu->itb->translateAtomic(tlb_req->memReq,
                         cpu->thread[tid]->getTC());
 
             if (tlb_req->fault != NoFault) {

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 4beb34a857818b8ea0bbe14441db5e815f4952ab..06df46c2bc8b9a4ed1b951f6756f4631b7385da3 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -599,7 +599,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
     memReq[tid] = mem_req;
 
     // Translate the instruction request.
-    fault = cpu->itb->translate(mem_req, cpu->thread[tid]->getTC());
+    fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC());
 
     // In the case of faults, the fetch stage may need to stall and wait
     // for the ITB miss to be handled.

diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 2a9b107d4598a28c078bf4b1c1222259468a0223..6b47ef539c693c7e03e53c1ca31f773bcd179bae 100644 (file)
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -480,7 +480,7 @@ FrontEnd<Impl>::fetchCacheLine()
                          PC, cpu->thread->contextId());
 
     // Translate the instruction request.
-    fault = cpu->itb->translate(memReq, thread);
+    fault = cpu->itb->translateAtomic(memReq, thread);
 
     // Now do the timing access to see whether or not the instruction
     // exists within the cache.

diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index 8850fa737bb6f7a2b281ce4f5620aa5cc9da2404..0840591e02cf4db0aab5ba275f8965eedaa75ef7 100644 (file)
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -204,7 +204,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
     memReq->reset(addr, sizeof(T), flags);
 
     // translate to physical address
-    Fault fault = cpu->dtb->translate(memReq, thread->getTC(), false);
+    Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), false);
 
     // if we have a cache, do cache access too
     if (fault == NoFault && dcacheInterface) {
@@ -245,7 +245,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     memReq->reset(addr, sizeof(T), flags);
 
     // translate to physical address
-    Fault fault = cpu->dtb->translate(memReq, thread->getTC(), true);
+    Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), true);
 
     if (fault == NoFault && dcacheInterface) {
         memReq->cmd = Write;

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index cd07a9fe3dfc6dee3061fca82cdba16933ab0531..7a1cf71c4b477e6ea48fd988441d69b3c58a3a6b 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->dtb->translate(req, tc, false);
+        Fault fault = thread->dtb->translateAtomic(req, tc, false);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -452,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->dtb->translate(req, tc, true);
+        Fault fault = thread->dtb->translateAtomic(req, tc, true);
 
         // Now do the access.
         if (fault == NoFault) {

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index f9fa8d8354ef1b715f2241f4fe9e39e6df84acf6..ddeb9a7c89e5797be36c9c66beab03f056506351 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -347,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
     Addr fetchPC = (threadPC & PCMask) + fetchOffset;
     req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
 
-    Fault fault = thread->itb->translate(req, tc);
+    Fault fault = thread->itb->translateAtomic(req, tc);
 
     return fault;
 }

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 844eccc75c5748888b4ac632b4eea93792b3c809..65222266e96b04a1c0448e1be94aed928e8440ca 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -314,7 +314,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 Fault
 TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read)
 {
-    Fault fault = thread->dtb->translate(req, tc, !read);
+    Fault fault = thread->dtb->translateAtomic(req, tc, !read);
     MemCmd cmd;
     if (fault != NoFault) {
         delete req;

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index c2ddeca06dcde36aa2d011cd7144cec7a259b6de..4eba493c32e140593bdd206cd309ccd03529826e 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -139,7 +139,7 @@ class SimpleThread : public ThreadState
 
     /***************************************************************
      *  SimpleThread functions to provide CPU with access to various
-     *  state, and to provide address translation methods.
+     *  state.
      **************************************************************/
 
     /** Returns the pointer to this SimpleThread's ThreadContext. Used

diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc
index 7292a69e0e9e5d64135df9d3c9e37f522fac8e3b..f7b57cbbc9309d7fa2e32a1810523721222c3fa2 100644 (file)
--- a/src/sim/tlb.cc
+++ b/src/sim/tlb.cc
@@ -34,7 +34,7 @@
 #include "sim/tlb.hh"
 
 Fault
-GenericTLB::translate(RequestPtr req, ThreadContext * tc, bool)
+GenericTLB::translateAtomic(RequestPtr req, ThreadContext * tc, bool)
 {
 #if FULL_SYSTEM
         panic("Generic translation shouldn't be used in full system mode.\n");

diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index 011cc114460fd280bb786c65b3d3ff12ea82e319..8429c0df55e32da76e7cc31466560c71fcc798d9 100644 (file)
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -58,7 +58,7 @@ class GenericTLB : public BaseTLB
   public:
     void demapPage(Addr vaddr, uint64_t asn);
 
-    Fault translate(RequestPtr req, ThreadContext *tc, bool=false);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool=false);
 };
 
 #endif // __ARCH_SPARC_TLB_HH__