opt_mem_feedback: Respect write port priority.

diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc
index 90e5cea9bc2f017b5e3ac9b61533087a809ef924..8e93c93b9246670417ef32e55a7489ef232a21b3 100644 (file)
--- a/passes/opt/opt_mem_feedback.cc
+++ b/passes/opt/opt_mem_feedback.cc
@@ -237,6 +237,21 @@ struct OptMemFeedbackWorker
 
                log("Populating enable bits on write ports of memory %s.%s with async read feedback:\n", log_id(module), log_id(mem.memid));
 
+               // If a write port has a feedback path that we're about to bypass,
+               // but also has priority over some other write port, the feedback
+               // path is not necessarily a NOP — it may overwrite the other port.
+               // Emulate this effect by converting the priority to soft logic
+               // (this will affect the other port's enable signal).
+               for (auto &it : portbit_conds)
+               {
+                       int wrport_idx = it.first.first;
+                       auto &port = mem.wr_ports[wrport_idx];
+
+                       for (int i = 0; i < wrport_idx; i++)
+                               if (port.priority_mask[i])
+                                       mem.emulate_priority(i, wrport_idx);
+               }
+
                for (auto &it : portbit_conds)
                {
                        int wrport_idx = it.first.first;

diff --git a/tests/opt/opt_mem_feedback.ys b/tests/opt/opt_mem_feedback.ys
index 6a68921c361005f9573d8c5cbcee4da9e97ac6e4..56078ec278d0b44a39114ac1e41e12f242c0e9f7 100644 (file)
--- a/tests/opt/opt_mem_feedback.ys
+++ b/tests/opt/opt_mem_feedback.ys
@@ -140,3 +140,50 @@ memory_map
 design -save postopt
 
 equiv_opt -assert -run prepare: :
+
+
+
+design -reset
+
+# Tricky case: legit feedback path, but priority needs to be preserved.
+
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input sel;
+input [3:0] wa1;
+input [3:0] wa2;
+input [15:0] wd1;
+input [3:0] ra;
+output [15:0] rd;
+
+reg [15:0] mem [0:15];
+
+always @(posedge clk) begin
+       mem[wa1] <= sel ? wd1 : mem[wa1];
+       mem[wa2] <= mem[wa2];
+end
+
+assign rd = mem[ra];
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -save start
+memory_map
+design -save preopt
+
+design -load start
+opt_mem_feedback
+select -assert-count 1 t:$memrd
+memory_map
+design -save postopt
+
+equiv_opt -assert -run prepare: :