All callers set this parameter to true.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
else
q->num_pipes = r300screen->info.r300_num_gb_pipes;
- q->buf = r300->rws->buffer_create(r300->rws, 4096, 4096, TRUE,
+ q->buf = r300->rws->buffer_create(r300->rws, 4096, 4096,
RADEON_DOMAIN_GTT, 0);
if (!q->buf) {
FREE(q);
r300->vbo = rws->buffer_create(rws,
MAX2(R300_MAX_DRAW_VBO_SIZE, size),
- R300_BUFFER_ALIGNMENT, TRUE,
+ R300_BUFFER_ALIGNMENT,
RADEON_DOMAIN_GTT, 0);
if (!r300->vbo) {
return FALSE;
/* Create a new one in the same pipe_resource. */
new_buf = r300->rws->buffer_create(r300->rws, rbuf->b.b.width0,
- R300_BUFFER_ALIGNMENT, TRUE,
+ R300_BUFFER_ALIGNMENT,
rbuf->domain, 0);
if (new_buf) {
/* Discard the old buffer. */
rbuf->buf =
r300screen->rws->buffer_create(r300screen->rws, rbuf->b.b.width0,
- R300_BUFFER_ALIGNMENT, TRUE,
+ R300_BUFFER_ALIGNMENT,
rbuf->domain, 0);
if (!rbuf->buf) {
FREE(rbuf);
/* Create the backing buffer if needed. */
if (!tex->buf) {
- tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048, TRUE,
+ tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048,
tex->domain, 0);
if (!tex->buf) {
/* Allocate a new resource. */
new_buf = rscreen->ws->buffer_create(rscreen->ws, size, alignment,
- true,
res->domains, flags);
if (!new_buf) {
return false;
/* TODO: 2D tiling workaround */
alignment *= 2;
- pb = ws->buffer_create(ws, size, alignment, TRUE, RADEON_DOMAIN_VRAM, 0);
+ pb = ws->buffer_create(ws, size, alignment, RADEON_DOMAIN_VRAM, 0);
if (!pb)
return;
struct pb_buffer *(*buffer_create)(struct radeon_winsys *ws,
uint64_t size,
unsigned alignment,
- boolean use_reusable_pool,
enum radeon_bo_domain domain,
enum radeon_bo_flag flags);
amdgpu_bo_create(struct radeon_winsys *rws,
uint64_t size,
unsigned alignment,
- boolean use_reusable_pool,
enum radeon_bo_domain domain,
enum radeon_bo_flag flags)
{
usage |= 1 << (flags + 3);
/* Get a buffer from the cache. */
- if (use_reusable_pool) {
- bo = (struct amdgpu_winsys_bo*)
- pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment,
- usage);
- if (bo)
- return &bo->base;
- }
+ bo = (struct amdgpu_winsys_bo*)
+ pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, usage);
+ if (bo)
+ return &bo->base;
/* Create a new one. */
bo = amdgpu_create_bo(ws, size, alignment, usage, domain, flags);
return NULL;
}
- bo->use_reusable_pool = use_reusable_pool;
+ bo->use_reusable_pool = true;
return &bo->base;
}
ib->used_ib_space = 0;
ib->big_ib_buffer = ws->buffer_create(ws, buffer_size,
- 4096, true,
+ 4096,
RADEON_DOMAIN_GTT,
RADEON_FLAG_CPU_ACCESS);
if (!ib->big_ib_buffer)
radeon_winsys_bo_create(struct radeon_winsys *rws,
uint64_t size,
unsigned alignment,
- boolean use_reusable_pool,
enum radeon_bo_domain domain,
enum radeon_bo_flag flags)
{
assert(flags < sizeof(usage) * 8 - 3);
usage |= 1 << (flags + 3);
- if (use_reusable_pool) {
- bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, usage));
- if (bo)
- return &bo->base;
- }
+ bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, usage));
+ if (bo)
+ return &bo->base;
bo = radeon_create_bo(ws, size, alignment, usage, domain, flags);
if (!bo) {
return NULL;
}
- bo->use_reusable_pool = use_reusable_pool;
+ bo->use_reusable_pool = true;
pipe_mutex_lock(ws->bo_handles_mutex);
util_hash_table_set(ws->bo_handles, (void*)(uintptr_t)bo->handle, bo);
struct pb_buffer *fence;
/* Create a fence, which is a dummy BO. */
- fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1, TRUE,
+ fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1,
RADEON_DOMAIN_GTT, 0);
/* Add the fence as a dummy relocation. */
cs->ws->base.cs_add_buffer(rcs, fence,