[Patch ARM/ AArch64] Fix typo in vcvt_f16.c testcase .

This test worked by accident. While looking at why this was failing randomly in my builds, I discovered a bug in the way in which the testcases were written up in this case.

2015-10-05  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c (TEST_MSG): Fix typo.
	(exec_vcvt): Add comments.

From-SVN: r228470

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c1282b357a87e3b583bb76b93cb449476d3015e2..3cb201ea59cf7b0decf46c8115111673e13a92d4 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-10-05  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+       * gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c (TEST_MSG): Fix typo.
+       (exec_vcvt): Add comments.
+
 2015-10-04  Uros Bizjak  <ubizjak@gmail.com>
 
        PR rtl-optimization/67447

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c
index 48e50e182634b8964fcd9ecf4cdca89d71f19496..c3e4d4f6e16919786250ab9fb57b46d5d4f53f3a 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_f16.c
@@ -21,7 +21,7 @@ exec_vcvt (void)
 {
   clean_results ();
 
-#define TEST_MSG vcvt_f32_f16
+#define TEST_MSG "vcvt_f32_f16"
   {
     VECT_VAR_DECL (buffer_src, float, 16, 4) [] = { 16.0, 15.0, 14.0, 13.0 };
 
@@ -39,7 +39,7 @@ exec_vcvt (void)
 
   clean_results ();
 
-#define TEST_MSG vcvt_f16_f32
+#define TEST_MSG "vcvt_f16_f32"
   {
     VECT_VAR_DECL (buffer_src, float, 32, 4) [] = { 1.5, 2.5, 3.5, 4.5 };
     DECL_VARIABLE (vector_src, float, 32, 4);
@@ -54,6 +54,8 @@ exec_vcvt (void)
   }
 #undef TEST_MSG
 
+  /* We run more tests for AArch64 as the relevant intrinsics
+     do not exist on AArch32.  */
 #if defined (__aarch64__)
   clean_results ();