add external core option

diff --git a/Makefile b/Makefile
index a9a008a22beaa413a7ab4c278afb4dd51563b3de..509cfdb9e4f866571b2f45bc56619b8843eb7c8e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -224,9 +224,14 @@ soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
 soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v
 endif
 
-GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
+ GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
        -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \
-       $(LITEDRAM_GHDL_ARG)
+       $(LITEDRAM_GHDL_ARG) -gEXTERNAL_CORE=$(EXTERNAL_CORE)
+       
+#GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
+#      -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) \
+#      -gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT) ...
+       
 
 
 ifeq ($(FPGA_TARGET), verilator)

diff --git a/soc.vhdl b/soc.vhdl
index fd059b9e1027cda2f0732641084efbd2d6bcac92..77d64565031bf3dce1f721a88c041b2192f1a3e3 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -400,6 +400,7 @@ begin
     end process;
 
     -- Processor core
+    processor_internal: if not EXTERNAL_CORE generate --UNTESTED --LZ@PLATEN
     processor: entity work.core
        generic map(
            SIM => SIM,
@@ -432,8 +433,39 @@ begin
            dmi_wr => dmi_wr,
            dmi_ack => dmi_core_ack,
            dmi_req => dmi_core_req,
-           ext_irq => core_ext_irq
+           ext_irq => core_ext_irq, --LZ
+           nia_req           => nia_req,
+        nia               => nia,
+        msr_o             => msr_o,
+        insn              => insn,
+        ldst_req          => ldst_req,
+        ldst_addr         => ldst_addr
            );
+    end generate;
+
+    processor_external: if EXTERNAL_CORE generate
+       processor: external_core_top
+       port map(
+           clk => system_clk,
+           rst => rst_core,
+           alt_reset => alt_reset_d,
+           wishbone_insn_in => wishbone_icore_in,
+           wishbone_insn_out => wishbone_icore_out,
+           wishbone_data_in => wishbone_dcore_in,
+           wishbone_data_out => wishbone_dcore_out,
+           dmi_addr => dmi_addr(3 downto 0),
+           dmi_dout => dmi_core_dout,
+           dmi_din => dmi_dout,
+           dmi_wr => dmi_wr,
+           dmi_ack => dmi_core_ack,
+           dmi_req => dmi_core_req,
+           ext_irq => core_ext_irq,
+        nia_req           => nia_req,
+        nia               => nia,
+        msr_o             => msr_o,
+        insn              => insn
+           );
+    end generate;
 
     -- Wishbone bus master arbiter & mux
     wb_masters_out <= (0 => wishbone_dcore_out,