Remove useless signal

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 9f76e34be896575d81d6fcb290e63644e55fe04e..a286c8f9df207d65e505fa4fda8d8ab18fb23621 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -235,7 +235,6 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                     m.d.sync += rdly.eq(0)
                 with m.Elif(self._rdly_dq_inc.w_stb):
                     m.d.sync += rdly.eq(rdly + 1)
-            datavalid = Signal()
             burstdet = Signal()
             dqs_read = Signal()
             dqs_bitslip = Signal(2)