;; 'L' Print the opcode suffix for a 32-bit integer opcode.
;; 'W' Print the opcode suffix for a 16-bit integer opcode.
;; 'B' Print the opcode suffix for an 8-bit integer opcode.
-;; 'S' Print the opcode suffix for a 32-bit float opcode.
;; 'Q' Print the opcode suffix for a 64-bit float opcode.
+;; 'S' Print the opcode suffix for a 32-bit float opcode.
;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
;; 'J' Print the appropriate jump operand.
else if (which_alternative == 1)
{
/* r <- cond ? r : arg */
- output_asm_insn (AS2 (cmov%N1,%3,%0), operands);
+ output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
}
else if (which_alternative == 2)
{
/* r <- cond ? arg1 : arg2 */
output_asm_insn (AS2 (cmov%C1,%2,%0), operands);
- output_asm_insn (AS2 (cmov%N1,%3,%0), operands);
+ output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
}
else
{
else if (which_alternative == 1)
{
/* r <- cond ? r : arg */
- output_asm_insn (AS2 (cmov%N1,%3,%0), operands);
+ output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
}
else if (which_alternative == 2)
{
/* r <- cond ? arg1 : arg2 */
output_asm_insn (AS2 (cmov%C1,%2,%0), operands);
- output_asm_insn (AS2 (cmov%N1,%3,%0), operands);
+ output_asm_insn (AS2 (cmov%c1,%3,%0), operands);
}
else
{
RET;
}")
+(define_expand "movsfcc"
+ [(match_dup 4)
+ (set (match_operand 0 "register_operand" "")
+ (if_then_else:SF (match_operand 1 "comparison_operator" "")
+ (match_operand:SF 2 "register_operand" "")
+ (match_operand:SF 3 "register_operand" "")))]
+ "TARGET_CMOVE"
+ "
+{
+ operands[4] = i386_compare_gen (i386_compare_op0, i386_compare_op1);
+}")
+
+(define_expand "movdfcc"
+ [(match_dup 4)
+ (set (match_operand 0 "register_operand" "")
+ (if_then_else:DF (match_operand 1 "comparison_operator" "")
+ (match_operand:DF 2 "register_operand" "")
+ (match_operand:DF 3 "register_operand" "")))]
+ "TARGET_CMOVE"
+ "
+{
+ operands[4] = i386_compare_gen (i386_compare_op0, i386_compare_op1);
+}")
+
+(define_expand "movxfcc"
+ [(match_dup 4)
+ (set (match_operand 0 "register_operand" "")
+ (if_then_else:XF (match_operand 1 "comparison_operator" "")
+ (match_operand:XF 2 "register_operand" "")
+ (match_operand:XF 3 "register_operand" "")))]
+ "TARGET_CMOVE"
+ "
+{
+ operands[4] = i386_compare_gen (i386_compare_op0, i386_compare_op1);
+}")
+
+(define_insn "movsfcc_1"
+ [(set (match_operand:SF 0 "register_operand" "=t,t")
+ (if_then_else:SF (match_operator 1 "comparison_operator"
+ [(cc0) (const_int 0)])
+ (match_operand:SF 2 "register_operand" "0,f")
+ (match_operand:SF 3 "register_operand" "f,0")))]
+ "TARGET_CMOVE"
+ "*
+{
+ if (which_alternative == 0)
+ {
+ /* r <- cond ? arg : r */
+ output_asm_insn (AS2 (fcmov%f1,%3,%0), operands);
+ }
+ else if (which_alternative == 1)
+ {
+ /* r <- cond ? r : arg */
+ output_asm_insn (AS2 (fcmov%F1,%2,%0), operands);
+ }
+ RET;
+}")
+
+(define_insn "movdfcc_1"
+ [(set (match_operand:DF 0 "register_operand" "=t,t")
+ (if_then_else:DF (match_operator 1 "comparison_operator"
+ [(cc0) (const_int 0)])
+ (match_operand:DF 2 "register_operand" "0,f")
+ (match_operand:DF 3 "register_operand" "f,0")))]
+ "TARGET_CMOVE"
+ "*
+{
+ if (which_alternative == 0)
+ {
+ /* r <- cond ? arg : r */
+ output_asm_insn (AS2 (fcmov%F1,%3,%0), operands);
+ }
+ else if (which_alternative == 1)
+ {
+ /* r <- cond ? r : arg */
+ output_asm_insn (AS2 (fcmov%f1,%2,%0), operands);
+ }
+ RET;
+}")
+
+(define_insn "movxfcc_1"
+ [(set (match_operand:XF 0 "register_operand" "=t,t")
+ (if_then_else:XF (match_operator 1 "comparison_operator"
+ [(cc0) (const_int 0)])
+ (match_operand:XF 2 "register_operand" "0,f")
+ (match_operand:XF 3 "register_operand" "f,0")))]
+ "TARGET_CMOVE"
+ "*
+{
+ if (which_alternative == 0)
+ {
+ /* r <- cond ? arg : r */
+ output_asm_insn (AS2 (fcmov%F1,%3,%0), operands);
+ }
+ else if (which_alternative == 1)
+ {
+ /* r <- cond ? r : arg */
+ output_asm_insn (AS2 (fcmov%f1,%2,%0), operands);
+ }
+ RET;
+}")
(define_insn "strlensi_unroll"
[(set (match_operand:SI 0 "register_operand" "=&r,&r")