rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
res->domains = RADEON_DOMAIN_VRAM;
flags &= ~RADEON_FLAG_CPU_ACCESS;
+ flags |= RADEON_FLAG_NO_CPU_ACCESS;
}
/* Allocate a new resource. */
};
#ifndef RADEON_GEM_GTT_WC
-#define RADEON_GEM_GTT_WC (1 << 2)
+#define RADEON_GEM_GTT_WC (1 << 2)
#endif
-#ifndef RADEON_GTM_CPU_ACCESS
+#ifndef RADEON_GEM_CPU_ACCESS
/* BO is expected to be accessed by the CPU */
-#define RADEON_GEM_CPU_ACCESS (1 << 3)
+#define RADEON_GEM_CPU_ACCESS (1 << 3)
+#endif
+#ifndef RADEON_GEM_NO_CPU_ACCESS
+/* CPU access is not expected to work for this BO */
+#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
#endif
static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
args.flags |= RADEON_GEM_GTT_WC;
if (rdesc->flags & RADEON_FLAG_CPU_ACCESS)
args.flags |= RADEON_GEM_CPU_ACCESS;
+ if (rdesc->flags & RADEON_FLAG_NO_CPU_ACCESS)
+ args.flags |= RADEON_GEM_NO_CPU_ACCESS;
if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
&args, sizeof(args))) {
};
enum radeon_bo_flag { /* bitfield */
- RADEON_FLAG_GTT_WC = (1 << 0),
- RADEON_FLAG_CPU_ACCESS = (1 << 1),
+ RADEON_FLAG_GTT_WC = (1 << 0),
+ RADEON_FLAG_CPU_ACCESS = (1 << 1),
+ RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
};
enum radeon_bo_usage { /* bitfield */