bios/sdram: revert capability to do manual read leveling since still needed with...

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index ba1bd216d64e7a581d37c62ac9a795f00f79da40..d9e3023d03e0383c2624d52d8fcdfe21365f6788 100644 (file)
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -598,7 +598,33 @@ int memtest(void)
 }
 
 #ifdef CSR_DDRPHY_BASE
-int sdrlevel(void)
+#ifdef READ_LEVELING_BITSLIP
+int sdrlevel(void) /* manual */
+{
+       int bitslip, delay, module;
+       int i;
+       sdram_dfii_control_write(DFII_CONTROL_SEL);
+       for(module=0; module<8; module++) {
+               ddrphy_dly_sel_write(1<<module);
+               ddrphy_rdly_dq_rst_write(1);
+           /* configure bitslip */
+#ifdef KUSDDRPHY
+                       ddrphy_rdly_dq_bitslip_write(1);
+#else
+               for(bitslip=0; bitslip<READ_LEVELING_BITSLIP; bitslip++) {
+                       // 7-series SERDES in DDR mode needs 3 pulses for 1 bitslip
+                       for(i=0; i<3; i++)
+                               ddrphy_rdly_dq_bitslip_write(1);
+               }
+#endif
+               /* configure delay */
+               for(delay=0; delay<READ_LEVELING_DELAY; delay++)
+                       ddrphy_rdly_dq_inc_write(1);
+       }
+       return 1;
+}
+#else
+int sdrlevel(void) /* automatic */
 {
        int delay[DFII_PIX_DATA_SIZE/2];
        int high_skew[DFII_PIX_DATA_SIZE/2];
@@ -619,6 +645,7 @@ int sdrlevel(void)
        return 1;
 }
 #endif
+#endif
 
 int sdrinit(void)
 {