{
unsigned int unBit;
unsigned int i;
- GLuint ui;
/* match fp inputs with vp exports. */
struct evergreen_vertex_program_cont *vpc =
pAsm->pR700Shader->depthIsExported = 1;
}
- pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);
- for(ui=0; ui<pAsm->number_of_exports; ui++)
- {
- pAsm->pucOutMask[ui] = 0x0;
- }
-
pAsm->flag_reg_index = pAsm->number_used_registers++;
pAsm->uFirstHelpReg = pAsm->number_used_registers;
struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp)
{
- GLuint ui;
r700_AssemblerBase *pAsm = &(vp->r700AsmCode);
unsigned int num_inputs;
pAsm->number_used_registers += pAsm->number_of_exports;
- pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);
-
- for(ui=0; ui<pAsm->number_of_exports; ui++)
- {
- pAsm->pucOutMask[ui] = 0x0;
- }
-
/* Map temporary registers (GPRs) */
pAsm->starting_temp_register_number = pAsm->number_used_registers;
if (pAsm->D.dst.rtype == DST_REG_OUT)
{
assert(pAsm->D.dst.reg >= pAsm->starting_export_register_number);
-
- if (pAsm->D.dst.op3)
- {
- // There is no mask for OP3 instructions, so all channels are written
- pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF;
- }
- else
- {
- pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number]
- |= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask;
- }
}
//reset for next inst.
{
assert(starting_register_number >= pAsm->starting_export_register_number);
- ucWriteMask = pAsm->pucOutMask[starting_register_number - pAsm->starting_export_register_number];
+ ucWriteMask = 0x0F;
/* exports Z as a float into Red channel */
if (GL_TRUE == is_depth_export)
ucWriteMask = 0x1;
GLboolean Clean_Up_Assembler(r700_AssemblerBase *pR700AsmCode)
{
- FREE(pR700AsmCode->pucOutMask);
FREE(pR700AsmCode->pInstDeps);
if(NULL != pR700AsmCode->subs)
unsigned char ucVP_AttributeMap[VERT_ATTRIB_MAX];
unsigned char ucVP_OutputMap[VERT_RESULT_MAX];
- unsigned char * pucOutMask;
-
//-----------------------------------------------------------------------------------
// flow control members
//-----------------------------------------------------------------------------------
{
unsigned int unBit;
unsigned int i;
- GLuint ui;
/* match fp inputs with vp exports. */
struct r700_vertex_program_cont *vpc =
}
}
- pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);
- for(ui=0; ui<pAsm->number_of_exports; ui++)
- {
- pAsm->pucOutMask[ui] = 0x0;
- }
-
pAsm->flag_reg_index = pAsm->number_used_registers++;
pAsm->uFirstHelpReg = pAsm->number_used_registers;
struct r700_vertex_program *vp,
struct gl_vertex_program *mesa_vp)
{
- GLuint ui;
r700_AssemblerBase *pAsm = &(vp->r700AsmCode);
unsigned int num_inputs;
pAsm->number_used_registers += pAsm->number_of_exports;
- pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);
-
- for(ui=0; ui<pAsm->number_of_exports; ui++)
- {
- pAsm->pucOutMask[ui] = 0x0;
- }
-
/* Map temporary registers (GPRs) */
pAsm->starting_temp_register_number = pAsm->number_used_registers;