Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

diff --cc techlibs/common/mul2dsp.v
Simple merge

diff --cc techlibs/xilinx/cells_sim.v
index 5410983aeae6dec2782acbf3140977ef095a010e,ea5a3b788b89256ed46fcd9fe3105f043d4d1d0d..1262fc8c1a8352f5eef1be065e2f741a3c22085e
--- 1/techlibs/xilinx/cells_sim.v
--- 2/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -516,12 -506,6 +516,12 @@@ module DSP48E1 
          if (PCIN != 48'b0)          $fatal(1, "Unsupported PCIN value");
          if (CARRYIN != 1'b0)        $fatal(1, "Unsupported CARRYIN value");
  `endif
-         Pr[42:0] <= Ar[24:0] * Br;
 -        P[42:0] <= $signed(A[24:0]) * $signed(B);
++        Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br);
      end
 +
 +    generate
 +        if (PREG == 1) begin always @(posedge CLK) if (CEP) P <= Pr; end
 +        else           always @* P <= Pr;
 +    endgenerate
 +
  endmodule

diff --cc techlibs/xilinx/dsp_map.v
index da1d6f3a9ffe78a69803267d04e13cddc77c94f4,0000000000000000000000000000000000000000..2063c45e2c3488091f4f64f2f8198435efaba4e7
mode 100644,000000..100644
--- 1/techlibs/xilinx/dsp_map.v
--- /dev/null
+++ b/techlibs/xilinx/dsp_map.v
@@@ -1,40 -1,0 +1,40 @@@
- module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
++module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y);
 +      wire [47:0] P_48;
 +      DSP48E1 #(
 +              // Disable all registers
 +              .ACASCREG(0),
 +              .ADREG(0),
 +              .A_INPUT("DIRECT"),
 +              .ALUMODEREG(0),
 +              .AREG(0),
 +              .BCASCREG(0),
 +              .B_INPUT("DIRECT"),
 +              .BREG(0),
 +              .CARRYINREG(0),
 +              .CARRYINSELREG(0),
 +              .CREG(0),
 +              .DREG(0),
 +              .INMODEREG(0),
 +              .MREG(0),
 +              .OPMODEREG(0),
 +              .PREG(0)
 +      ) _TECHMAP_REPLACE_ (
 +              //Data path
-               .A({5'b0, A}),
-               .B(B),
++              .A({6'b0, A}),
++              .B({1'b0, B}),
 +              .C(48'b0),
 +              .D(24'b0),
 +              .P(P_48),
 +
 +              .INMODE(4'b0000),
 +              .ALUMODE(4'b0000),
 +              .OPMODE(7'b000101),
 +              .CARRYINSEL(3'b000),
 +
 +              .ACIN(30'b0),
 +              .BCIN(18'b0),
 +              .PCIN(48'b0),
 +              .CARRYIN(1'b0)
 +      );
 +      assign Y = P_48;
 +endmodule

diff --cc techlibs/xilinx/synth_xilinx.cc
Simple merge