X86: Make far ret modify CS instead of some random selector.

diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
index b18d4826457142ad1bcab268457729a12917a1db..d1a8245e6f374b8426f27aa57e28c4251f7e3991 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py
@@ -109,8 +109,8 @@ processDescriptor:
     chks t2, t3, IretCheck, dataSize=8
     # There should be validity checks on the RIP checks here, but I'll do
     # that later.
-    wrdl reg, t3, t2
-    wrsel reg, t2
+    wrdl cs, t3, t2
+    wrsel cs, t2
     wrip t0, t1
     bri t0, label("end")