add missing sync up meeting

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+# Tuesday 7th Nov
+
+TODO: Finish filling up from notes
+
+* Previous weeks' notes: NA
+* Next weeks' notes: [[meetings/sync_up/2023-11-14_15]]
+
+## Sadoon
+
+-
+
+## Jacob
+
+- Made necessary fixes to pseudo-code to get a whole bunch of simulator
+tests working. [bug #1177](https://bugs.libre-soc.org/show_bug.cgi?id=1177)
+- Quoting Jacob:
+  - "yeah, i made the changes since coping all insn inputs made TRAP
+    not quite work since it modifies the SRR0/1 in self.spr instead of
+    the locals in the compiled pseudo-code 
+    otherwise i'd have to change the parser to feed all locals into TRAP"
+
+## Andrey
+
+# Wednesday 8th November
+
+## Cesar
+
+- nextpnr-xilinx has issues with 2.5V I/O.
+  - FPGA split I/O split into banks, each bank has its own voltage.
+  - For now ignore switches/LEDs, test UART as it's at 3.3V
+(and that's enough for Libre-SOC).
+  - Need to make a bug report in upstream nextpnr-xilinx.
+
+- LD/ST CompUnit (CU) formal verification:
+  - During test, CompUnit communicates with scoreboard and registerfiles.
+  - Issue instruction to CU, fetch operands, store in reg's, send to ALU,
+store result to regfile.
+  - Put counters for those tests. Counter values must match
+(fetch reg's only once, read ALU only *after* operands have been written).
+
+- FOSDEM:
+  - Suggested people to invite:
+    - [Matt Venn](https://www.mattvenn.net/)
+([Zero to ASIC](https://www.zerotoasiccourse.com/) course author)
+    - Mohamed Kassem ([e-fabless](https://efabless.com/))
+  - Shouldn't make all about LibreSOC (since we were lucky to get a devroom,
+should also make the space available to other projects in the same area).
+
+[[!tag meeting2023]]
+[[!tag meeting_sync_up]]