vt->postfix.shared_memory = batch->framebuffer.gpu;
}
+void
+panfrost_vt_update_occlusion_query(struct panfrost_context *ctx,
+ struct midgard_payload_vertex_tiler *tp)
+{
+ SET_BIT(tp->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query);
+ if (ctx->occlusion_query)
+ tp->postfix.occlusion_counter = ctx->occlusion_query->bo->gpu;
+ else
+ tp->postfix.occlusion_counter = 0;
+}
+
void
panfrost_emit_shader_meta(struct panfrost_batch *batch,
enum pipe_shader_type st,
panfrost_vt_attach_framebuffer(struct panfrost_context *ctx,
struct midgard_payload_vertex_tiler *vt);
+void
+panfrost_vt_update_occlusion_query(struct panfrost_context *ctx,
+ struct midgard_payload_vertex_tiler *tp);
+
void
panfrost_emit_shader_meta(struct panfrost_batch *batch,
enum pipe_shader_type st,
panfrost_batch_set_requirements(batch);
- if (ctx->occlusion_query) {
- ctx->payloads[PIPE_SHADER_FRAGMENT].gl_enables |= MALI_OCCLUSION_QUERY;
- ctx->payloads[PIPE_SHADER_FRAGMENT].postfix.occlusion_counter = ctx->occlusion_query->bo->gpu;
- }
+ panfrost_vt_update_occlusion_query(ctx, &ctx->payloads[PIPE_SHADER_FRAGMENT]);
panfrost_patch_shader_state(ctx, PIPE_SHADER_VERTEX);
panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX,