if (str == endptr)
len_in_bits = -1;
- // The "<bits>'s?[bodh]<digits>" syntax
+ // The "<bits>'s?[bodhBODH]<digits>" syntax
if (*endptr == '\'')
{
std::vector<RTLIL::State> data;
switch (*(endptr+1))
{
case 'b':
+ case 'B':
my_strtobin(data, endptr+2, len_in_bits, 2, case_type);
break;
case 'o':
+ case 'O':
my_strtobin(data, endptr+2, len_in_bits, 8, case_type);
break;
case 'd':
+ case 'D':
my_strtobin(data, endptr+2, len_in_bits, 10, case_type);
break;
case 'h':
+ case 'H':
my_strtobin(data, endptr+2, len_in_bits, 16, case_type);
break;
default:
"genvar" { return TOK_GENVAR; }
"real" { return TOK_REAL; }
-[0-9]+ {
+[0-9][0-9_]* {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_CONST;
}
-[0-9]*[ \t]*\'s?[bodh][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
+[0-9]*[ \t]*\'s?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_CONST;
}