verilog backend: Emit a `wire` for ports as well.

Fixes #3177.

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 32003cf549d26f4b9f24eca890c86fa8096d8d7b..aa1d4558c34d51093c898d20207e28a49fab2b5d 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -432,7 +432,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
                        dump_const(f, wire->attributes.at(ID::init));
                }
                f << stringf(";\n");
-       } else if (!wire->port_input && !wire->port_output)
+       } else
                f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
 #endif
 }