(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index ffd8dfe0a816492f01d965bc29f04e738ac2f2a6..43b7560af6d50ed6ce4ad42f2346d1272d6948fb 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -212,7 +212,7 @@ adding the various sub-extensions to the Base Scalar Power ISA.
 
 It also has to be pointed out that normally this work would be covered by
 multiple separate full-time Workgroups with multiple Members contributing
-their time and resources!
+their time and resources.
 
 Overall the contributions that we are developing take the Power ISA out of
 the specialist highly-focussed market it is presently best known for, and
@@ -227,7 +227,8 @@ to a 3D GPU / High Performance Compute ISA WG RFC:
 
 (Failure to add Transcendentals to a 3D GPU is directly equivalent to
 *willfully* designing a product that is 100% destined for commercial
-failure.)
+rejection, due to the extremely high competitive performance/watt achieved
+by today's mass-volume GPUs.)
 
 I mention these because they will be encountered in every single
 commercial GPU ISA, but they're not part of the "Base" (core design)
@@ -240,20 +241,15 @@ Actual 3D GPU Architectures and ISAs:
 
 * Broadcom Videocore
   <https://github.com/hermanhermitage/videocoreiv>
-
 * Etnaviv
   <https://github.com/etnaviv/etna_viv/tree/master/doc>
-
 * Nyuzi
   <http://www.cs.binghamton.edu/~millerti/nyuziraster.pdf>
-
 * MALI
   <https://github.com/cwabbott0/mali-isa-docs>
-
 * AMD
   <https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf>  
   <https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf>
-
 * MIAOW which is *NOT* a 3D GPU, it is a processor which happens to implement a subset of the AMDGPU ISA (Southern Islands), aka a "GPGPU"
   <https://miaowgpu.org/>
 
@@ -263,7 +259,6 @@ Actual Vector Processor Architectures and ISAs:
 
 * NEC SX Aurora
   <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>
-
 * Cray ISA
   <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
 * RISC-V RVV