ac/surface: enable DCC for the first level in the mip tail on gfx10

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5424>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index be55e6deaaa458352bcd7ea388b85bd7ea199af3..206cdd26dbe043504599efb2e915c215d42c49ab 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1481,7 +1481,16 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib,
                         */
                        for (unsigned i = 0; i < in->numMipLevels; i++) {
                                if (meta_mip_info[i].inMiptail) {
-                                       surf->num_dcc_levels = i;
+                                       /* GFX10 can only compress the first level
+                                        * in the mip tail.
+                                        *
+                                        * TODO: Try to do the same thing for gfx9
+                                        *       if there are no regressions.
+                                        */
+                                       if (info->chip_class >= GFX10)
+                                               surf->num_dcc_levels = i + 1;
+                                       else
+                                               surf->num_dcc_levels = i;
                                        break;
                                }
                        }