ram addr calculation ram_addr

diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl
index 9a0358b07114ad8951687f121c747ec8a65858b0..fcf528b47a44cf6bb5a04746bbdbab5cb093fdfa 100644 (file)
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@@ -76,7 +76,7 @@ begin
     bram_re <= ram_re;
 
     -- Wishbone interface
-    ram_addr <= wishbone_in.adr(ram_addr_bits - 1 downto 0);
+    ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3);
     ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
     ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we;
     wishbone_out.stall <= '0';