sv_analysis: use is instead of eq for enums

diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index 013ba8ab89883cfff6d507fffc936679f5776657..7cfc65f3ef8cea9dc554932d3a138e1e35d47964 100644 (file)
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -685,10 +685,10 @@ def process_csvs(format):
     csvcols = ['insn', 'Ptype', 'Etype']
     csvcols += ['in1', 'in2', 'in3', 'out', 'out2', 'CR in', 'CR out']
 
-    if format == Format.VHDL:
+    if format is Format.VHDL:
         # and a nice microwatt VHDL file
         file_path = find_wiki_file("sv_decode.vhdl")
-    elif format == Format.BINUTILS:
+    elif format is Format.BINUTILS:
         file_path = find_wiki_file("binutils.c")
 
     with open(file_path, 'w') as stream:
@@ -710,7 +710,7 @@ def output_autogen_disclaimer(format, stream):
 def output(format, svt, csvcols, insns, csvs_svp64, stream):
     output_autogen_disclaimer(format, stream)
 
-    if format == Format.BINUTILS:
+    if format is Format.BINUTILS:
         stream.write("/* TODO: implement proper support */\n")
         return