litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization

self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.

diff --git a/misoclib/mem/litesata/phy/k7/trx.py b/misoclib/mem/litesata/phy/k7/trx.py
index 1ca9c9f475ff85fe7d4696df705db010ae25cea3..e22982844d210fd9737a518abcc554b36f5b66d2 100644 (file)
--- a/misoclib/mem/litesata/phy/k7/trx.py
+++ b/misoclib/mem/litesata/phy/k7/trx.py
@@ -575,7 +575,7 @@ class K7LiteSATAPHYTRX(Module):
 
                 # Receive Ports - CDR Ports
                     i_RXCDRFREQRESET=0,
-                    i_RXCDRHOLD=0,
+                    i_RXCDRHOLD=self.rxelecidle,
                     #o_RXCDRLOCK=,
                     i_RXCDROVRDEN=0,
                     i_RXCDRRESET=0,