constraints.md (Pe): New constraint.

2012-04-13  Joey Ye  <joey.ye@arm.com>

	* config/arm/constraints.md (Pe): New constraint.
	* config/arm/arm.md: New split for imm 256-510.

testsuite:

	* gcc.target/arm/thumb1-imm.c: New testcase.

From-SVN: r186406

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c3c0c4adc9f037413d7d576f8f632d042077456d..4b688ea43aebdee85fa5d53f387dc540737dfd71 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2012-04-13  Joey Ye  <joey.ye@arm.com>
+
+       * config/arm/constraints.md (Pe): New constraint.
+       * config/arm/arm.md: New split for imm 256-510.
+
 2012-04-13  Terry Guo  <terry.guo@arm.com>
 
        * config/arm/arm-cores.def: Added core cortex-m0plus.

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 3cdc1535f3a77b9426416d2e56b268825825298e..79eff0e4fe4ab2064b629eb95b1737ae2e0778e6 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -5652,6 +5652,21 @@
   }"
 )
 
+;; For thumb1 split imm move [256-510] into mov [1-255] and add #255
+(define_split 
+  [(set (match_operand:SI 0 "register_operand" "")
+       (match_operand:SI 1 "const_int_operand" ""))]
+  "TARGET_THUMB1 && satisfies_constraint_Pe (operands[1])"
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
+  "
+  {
+    operands[1] = GEN_INT (INTVAL (operands[1]) - 255);
+    operands[2] = can_create_pseudo_p () ? gen_reg_rtx (SImode) : operands[0];
+    operands[3] = GEN_INT (255);
+  }"
+)
+
 ;; When generating pic, we need to load the symbol offset into a register.
 ;; So that the optimizer does not confuse this with a normal symbol load
 ;; we use an unspec.  The offset will be loaded from a constant pool entry,

diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index 3ff968b98eadb56c4222227e8b05e945aaea8916..6b59e8772e512b382f947e39676f1561903c2a65 100644 (file)
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -30,7 +30,7 @@
 
 ;; The following multi-letter normal constraints have been used:
 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di, Dt, Dz
-;; in Thumb-1 state: Pa, Pb, Pc, Pd
+;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
 ;; in Thumb-2 state: Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py
 
 ;; The following memory constraints have been used:
@@ -172,6 +172,11 @@
   (and (match_code "const_int")
        (match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))
 
+(define_constraint "Pe"
+  "@internal In Thumb-1 state a constant in the range 256 to +510"
+  (and (match_code "const_int")
+       (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
+
 (define_constraint "Ps"
   "@internal In Thumb-2 state a constant in the range -255 to +255"
   (and (match_code "const_int")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d3f14645f1aa9630ace65c5b0f9e775406a85090..2884b93955563850a9ae376b0e530d69ada2ff8f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2012-04-13  Joey Ye  <joey.ye@arm.com>
+
+       * gcc.target/arm/thumb1-imm.c: New testcase.
+
 2012-04-12  Uros Bizjak  <ubizjak@gmail.com>
 
        PR target/52932

diff --git a/gcc/testsuite/gcc.target/arm/thumb1-imm.c b/gcc/testsuite/gcc.target/arm/thumb1-imm.c
new file mode 100644 (file)
index 0000000..b47c08c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/thumb1-imm.c
@@ -0,0 +1,10 @@
+/* Check for thumb1 imm [255-510] moves.  */
+/* { dg-require-effective-target arm_thumb1_ok } */
+
+int f()
+{
+  return 257;
+}
+
+/* { dg-final { scan-assembler-not "ldr" } } */
+