* cgen-asm.in (extract_normal): Ditto.
* fr30-asm.c,fr30-dis.c,fr30-opc.h,fr30-opc.c: Regenerate.
* i960c-asm.c,i960c-dis.c,i960c-opc.h,i960c-opc.c: Regenerate.
* m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate.
+1999-01-05 Doug Evans <devans@casey.cygnus.com>
+
+start-sanitize-cygnus
+ * cgen-asm.in (insert_normal): Use CGEN_BOOL_ATTR.
+ * cgen-asm.in (extract_normal): Ditto.
+end-sanitize-cygnus
+start-sanitize-fr30
+ * fr30-asm.c,fr30-dis.c,fr30-opc.h,fr30-opc.c: Regenerate.
+end-sanitize-fr30
+ * i960c-asm.c,i960c-dis.c,i960c-opc.h,i960c-opc.c: Regenerate.
+ * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate.
+
1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com)
* configure.in: Require autoconf 2.12.1 or higher.
#include "@prefix@-opc.h"
#include "opintl.h"
-/* ??? The layout of this stuff is still work in progress.
- For speed in assembly/disassembly, we use inline functions. That of course
- will only work for GCC. When this stuff is finished, we can decide whether
- to keep the inline functions (and only get the performance increase when
- compiled with GCC), or switch to macros, or use something else.
-*/
+#undef min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+#undef INLINE
+#ifdef __GNUC__
+#define INLINE __inline__
+#else
+#define INLINE
+#endif
+
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
static const char * insert_normal
- PARAMS ((long, unsigned int, int, int, int, char *));
+ PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
static const char * parse_insn_normal
- PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *));
+ PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *,
+ const char **, CGEN_FIELDS *));
static const char * insert_insn_normal
- PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *, bfd_vma));
+ PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *,
+ CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma));
\f
/* -- assembler routines inserted here */
\f
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal. */
+
+static INLINE void
+insert_1 (od, value, start, length, word_length, bufp)
+ CGEN_OPCODE_DESC od;
+ unsigned long value;
+ int start,length,word_length;
+ unsigned char *bufp;
+{
+ unsigned long x,mask;
+ int shift;
+ int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG;
+
+ switch (word_length)
+ {
+ case 8:
+ x = *bufp;
+ break;
+ case 16:
+ if (big_p)
+ x = bfd_getb16 (bufp);
+ else
+ x = bfd_getl16 (bufp);
+ break;
+ case 24:
+ /* ??? This may need reworking as these cases don't necessarily
+ want the first byte and the last two bytes handled like this. */
+ if (big_p)
+ x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
+ else
+ x = bfd_getl16 (bufp) | (bufp[2] << 16);
+ break;
+ case 32:
+ if (big_p)
+ x = bfd_getb32 (bufp);
+ else
+ x = bfd_getl32 (bufp);
+ break;
+ default :
+ abort ();
+ }
+
+ /* Written this way to avoid undefined behaviour. */
+ mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = (word_length - (start + length));
+ x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+ switch (word_length)
+ {
+ case 8:
+ *bufp = x;
+ break;
+ case 16:
+ if (big_p)
+ bfd_putb16 (x, bufp);
+ else
+ bfd_putl16 (x, bufp);
+ break;
+ case 24:
+ /* ??? This may need reworking as these cases don't necessarily
+ want the first byte and the last two bytes handled like this. */
+ if (big_p)
+ {
+ bufp[0] = x >> 16;
+ bfd_putb16 (x, bufp + 1);
+ }
+ else
+ {
+ bfd_putl16 (x, bufp);
+ bufp[2] = x >> 16;
+ }
+ break;
+ case 32:
+ if (big_p)
+ bfd_putb32 (x, bufp);
+ else
+ bfd_putl32 (x, bufp);
+ break;
+ default :
+ abort ();
+ }
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
/* Default insertion routine.
ATTRS is a mask of the boolean attributes.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
LENGTH is the length of VALUE in bits.
- TOTAL_LENGTH is the total length of the insn (currently 8,16,32).
+ TOTAL_LENGTH is the total length of the insn in bits.
The result is an error message or NULL if success. */
/* ??? This duplicates functionality with bfd's howto table and
bfd_install_relocation. */
-/* ??? For architectures where insns can be representable as ints,
- store insn in `field' struct and add registers, etc. while parsing? */
+/* ??? This doesn't handle bfd_vma's. Create another function when
+ necessary. */
static const char *
-insert_normal (value, attrs, start, length, total_length, buffer)
+insert_normal (od, value, attrs, word_offset, start, length, word_length,
+ total_length, buffer)
+ CGEN_OPCODE_DESC od;
long value;
unsigned int attrs;
- int start;
- int length;
- int total_length;
- char * buffer;
+ unsigned int word_offset, start, length, word_length, total_length;
+ CGEN_INSN_BYTES_PTR buffer;
{
- bfd_vma x;
- static char buf[100];
- /* Written this way to avoid undefined behaviour.
- Yes, `long' will be bfd_vma but not yet. */
- long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ static char errbuf[100];
+ /* Written this way to avoid undefined behaviour. */
+ unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
/* If LENGTH is zero, this operand doesn't contribute to the value. */
if (length == 0)
return NULL;
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
+
+ if (word_length > 32)
+ abort ();
+
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+#endif
+
/* Ensure VALUE will fit. */
- if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0)
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
{
- unsigned long max = mask;
- if ((unsigned long) value > max)
+ unsigned long maxval = mask;
+ if ((unsigned long) value > maxval)
{
/* xgettext:c-format */
- sprintf (buf, _("operand out of range (%lu not between 0 and %lu)"),
- value, max);
- return buf;
+ sprintf (errbuf,
+ _("operand out of range (%lu not between 0 and %lu)"),
+ value, maxval);
+ return errbuf;
}
}
else
{
- long min = - (1L << (length - 1));
- long max = (1L << (length - 1)) - 1;
- if (value < min || value > max)
+ long minval = - (1L << (length - 1));
+ long maxval = (1L << (length - 1)) - 1;
+ if (value < minval || value > maxval)
{
sprintf
/* xgettext:c-format */
- (buf, _("operand out of range (%ld not between %ld and %ld)"),
- value, min, max);
- return buf;
+ (errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+ value, minval, maxval);
+ return errbuf;
}
}
-#if 0 /*def CGEN_INT_INSN*/
- *buffer |= (value & mask) << (total_length - (start + length));
-#else
- switch (total_length)
- {
- case 8:
- x = * (unsigned char *) buffer;
- break;
- case 16:
- if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
- x = bfd_getb16 (buffer);
- else
- x = bfd_getl16 (buffer);
- break;
- case 32:
- if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
- x = bfd_getb32 (buffer);
- else
- x = bfd_getl32 (buffer);
- break;
- default :
- abort ();
- }
+#if CGEN_INT_INSN_P
- x |= (value & mask) << (total_length - (start + length));
+ {
+ int shift;
- switch (total_length)
- {
- case 8:
- * buffer = value;
- break;
- case 16:
- if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
- bfd_putb16 (x, buffer);
- else
- bfd_putl16 (x, buffer);
- break;
- case 32:
- if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
- bfd_putb32 (x, buffer);
- else
- bfd_putl32 (x, buffer);
- break;
- default :
- abort ();
- }
-#endif
+ if (CGEN_INSN_LSB0_P)
+ shift = (start + 1) - length;
+ else
+ shift = word_length - (start + length);
+ *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+ }
+
+#else /* ! CGEN_INT_INSN_P */
+
+ {
+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+ insert_1 (od, value, start, length, word_length, bufp);
+ }
+
+#endif /* ! CGEN_INT_INSN_P */
return NULL;
}
*/
static const char *
-parse_insn_normal (insn, strp, fields)
+parse_insn_normal (od, insn, strp, fields)
+ CGEN_OPCODE_DESC od;
const CGEN_INSN * insn;
const char ** strp;
CGEN_FIELDS * fields;
#endif
/* For now we assume the mnemonic is first (there are no leading operands).
- We can parse it without needing to set up operand parsing. */
+ We can parse it without needing to set up operand parsing.
+ GAS's input scrubber will ensure mnemonics are lowercase, but we may
+ not be called from GAS. */
p = CGEN_INSN_MNEMONIC (insn);
- while (* p && * p == * str)
- ++ p, ++ str;
+ while (*p && tolower (*p) == tolower (*str))
+ ++p, ++str;
if (* p || (* str && !isspace (* str)))
return _("unrecognized instruction");
- CGEN_INIT_PARSE ();
- cgen_init_parse_operand ();
+ CGEN_INIT_PARSE (od);
+ cgen_init_parse_operand (od);
#ifdef CGEN_MNEMONIC_OPERANDS
past_opcode_p = 0;
#endif
/* We don't check for (*str != '\0') here because we want to parse
any trailing fake arguments in the syntax string. */
- syn = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn));
+ syn = CGEN_SYNTAX_STRING (syntax);
/* Mnemonics come first for now, ensure valid string. */
if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
}
/* We have an operand of some sort. */
- errmsg = @arch@_cgen_parse_operand (CGEN_SYNTAX_FIELD (*syn),
- &str, fields);
+ errmsg = @arch@_cgen_parse_operand (od, CGEN_SYNTAX_FIELD (*syn),
+ &str, fields);
if (errmsg)
return errmsg;
}
/* We couldn't parse it. */
- return "unrecognized instruction";
+ return _("unrecognized instruction");
}
/* Default insn builder (insert handler).
- The instruction is recorded in target byte order.
+ The instruction is recorded in CGEN_INT_INSN_P byte order
+ (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is
+ recorded in host byte order, otherwise BUFFER is an array of bytes and the
+ value is recorded in target byte order).
The result is an error message or NULL if success. */
-/* FIXME: change buffer to char *? */
static const char *
-insert_insn_normal (insn, fields, buffer, pc)
+insert_insn_normal (od, insn, fields, buffer, pc)
+ CGEN_OPCODE_DESC od;
const CGEN_INSN * insn;
CGEN_FIELDS * fields;
- cgen_insn_t * buffer;
+ CGEN_INSN_BYTES_PTR buffer;
bfd_vma pc;
{
const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn);
- bfd_vma value;
+ unsigned long value;
const unsigned char * syn;
- CGEN_INIT_INSERT ();
- value = CGEN_INSN_VALUE (insn);
+ CGEN_INIT_INSERT (od);
+ value = CGEN_INSN_BASE_VALUE (insn);
/* If we're recording insns as numbers (rather than a string of bytes),
target byte order handling is deferred until later. */
-#undef min
-#define min(a,b) ((a) < (b) ? (a) : (b))
-#if 0 /*def CGEN_INT_INSN*/
+
+#if CGEN_INT_INSN_P
+
*buffer = value;
+
#else
- switch (min (CGEN_BASE_INSN_BITSIZE, CGEN_FIELDS_BITSIZE (fields)))
- {
- case 8:
- * buffer = value;
- break;
- case 16:
- if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
- bfd_putb16 (value, (char *) buffer);
- else
- bfd_putl16 (value, (char *) buffer);
- break;
- case 32:
- if (CGEN_CURRENT_ENDIAN == CGEN_ENDIAN_BIG)
- bfd_putb32 (value, (char *) buffer);
- else
- bfd_putl32 (value, (char *) buffer);
- break;
- default:
- abort ();
- }
-#endif
- /* ??? Rather than scanning the syntax string again, we could store
- in `fields' a null terminated list of the fields that are present. */
+ cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE,
+ CGEN_FIELDS_BITSIZE (fields)),
+ value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+ /* ??? It would be better to scan the format's fields.
+ Still need to be able to insert a value based on the operand though;
+ e.g. storing a branch displacement that got resolved later.
+ Needs more thought first. */
for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn)
{
if (CGEN_SYNTAX_CHAR_P (* syn))
continue;
- errmsg = @arch@_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields,
- (char *) buffer, pc);
+ errmsg = @arch@_cgen_insert_operand (od, CGEN_SYNTAX_FIELD (*syn),
+ fields, buffer, pc);
if (errmsg)
return errmsg;
}
This routine is called for each instruction to be assembled.
STR points to the insn to be assembled.
We assume all necessary tables have been initialized.
- The assembled instruction, less any fixups, is stored in buf.
- [??? What byte order?]
+ The assembled instruction, less any fixups, is stored in BUF.
+ Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+ still needs to be converted to target byte order, otherwise BUF is an array
+ of bytes in target byte order.
The result is a pointer to the insn's entry in the opcode table,
or NULL if an error occured (an error message will have already been
printed).
this function recurses. */
const CGEN_INSN *
-@arch@_cgen_assemble_insn (str, fields, buf, errmsg)
+@arch@_cgen_assemble_insn (od, str, fields, buf, errmsg)
+ CGEN_OPCODE_DESC od;
const char * str;
CGEN_FIELDS * fields;
- cgen_insn_t * buf;
+ CGEN_INSN_BYTES_PTR buf;
char ** errmsg;
{
const char * start;
/* The instructions are stored in hashed lists.
Get the first in the list. */
- ilist = CGEN_ASM_LOOKUP_INSN (str);
+ ilist = CGEN_ASM_LOOKUP_INSN (od, str);
/* Keep looking until we find a match. */
#if 0 /* not needed as unsupported opcodes shouldn't be in the hash lists */
/* Is this insn supported by the selected cpu? */
- if (! @arch@_cgen_insn_supported (insn))
+ if (! @arch@_cgen_insn_supported (od, insn))
continue;
#endif
str = start;
- /* Record a default length for the insn. This will get set to the
- correct value while parsing. */
- /* FIXME: wip */
+ /* Allow parse/insert handlers to obtain length of insn. */
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
- if (! CGEN_PARSE_FN (insn) (insn, & str, fields))
+ if (! CGEN_PARSE_FN (insn) (od, insn, & str, fields))
{
/* ??? 0 is passed for `pc' */
- if (CGEN_INSERT_FN (insn) (insn, fields, buf, (bfd_vma) 0) != NULL)
+ if (CGEN_INSERT_FN (insn) (od, insn, fields, buf, (bfd_vma) 0) != NULL)
continue;
/* It is up to the caller to actually output the insn and any
queued relocs. */
FIXME: Not currently used. */
void
-@arch@_cgen_asm_hash_keywords (opvals)
+@arch@_cgen_asm_hash_keywords (od, opvals)
+ CGEN_OPCODE_DESC od;
CGEN_KEYWORD * opvals;
{
CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL);
if (! @arch@_cgen_opval_supported (ke))
continue;
#endif
- cgen_asm_record_register (ke->name, ke->value);
+ cgen_asm_record_register (od, ke->name, ke->value);
}
}
/* Default text to print if an instruction isn't recognized. */
#define UNKNOWN_INSN_MSG _("*unknown*")
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
static int extract_normal
- PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_BYTES,
- unsigned int, int, int, int, long *));
+ PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ unsigned int, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, bfd_vma, long *));
static void print_normal
PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int));
static void print_address
PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
static int extract_insn_normal
PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
- unsigned long, CGEN_FIELDS *, bfd_vma));
+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
static void print_insn_normal
PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
bfd_vma, int));
\f
#if ! CGEN_INT_INSN_P
+/* Subroutine of extract_normal.
+ Ensure sufficient bytes are cached in EX_INFO.
+ OFFSET is the offset in bytes from the start of the insn of the value.
+ BYTES is the length of the needed value.
+ Returns 1 for success, 0 for failure. */
+
+static INLINE int
+fill_cache (od, ex_info, offset, bytes, pc)
+ CGEN_OPCODE_DESC od;
+ CGEN_EXTRACT_INFO *ex_info;
+ int offset, bytes;
+ bfd_vma pc;
+{
+ /* It's doubtful that the middle part has already been fetched so
+ we don't optimize that case. kiss. */
+ int mask;
+ disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+ /* First do a quick check. */
+ mask = (1 << bytes) - 1;
+ if (((ex_info->valid >> offset) & mask) == mask)
+ return 1;
+
+ /* Search for the first byte we need to read. */
+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+ if (! (mask & ex_info->valid))
+ break;
+
+ if (bytes)
+ {
+ int status;
+
+ pc += offset;
+ status = (*info->read_memory_func)
+ (pc, ex_info->insn_bytes + offset, bytes, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return 0;
+ }
+
+ ex_info->valid |= ((1 << bytes) - 1) << offset;
+ }
+
+ return 1;
+}
+
/* Subroutine of extract_normal. */
static INLINE long
-extract_1 (od, ex_info, start, length, word_length, bufp)
+extract_1 (od, ex_info, start, length, word_length, bufp, pc)
CGEN_OPCODE_DESC od;
- CGEN_EXTRACT_INFO *info;
+ CGEN_EXTRACT_INFO *ex_info;
int start,length,word_length;
unsigned char *bufp;
+ bfd_vma pc;
{
unsigned long x,mask;
int shift;
int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG;
- /* FIXME: Need to use ex_info to ensure bytes have been fetched. */
-
switch (word_length)
{
case 8:
/* ??? This may need reworking as these cases don't necessarily
want the first byte and the last two bytes handled like this. */
if (big_p)
- x = (bfd_getb8 (bufp) << 16) | bfd_getb16 (bufp + 1);
+ x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
else
- x = bfd_getl16 (bufp) | (bfd_getb8 (bufp + 2) << 16);
+ x = bfd_getl16 (bufp) | (bufp[2] << 16);
break;
case 32:
if (big_p)
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
if (CGEN_INSN_LSB0_P)
- shift = start;
+ shift = (start + 1) - length;
else
shift = (word_length - (start + length));
return (x >> shift) & mask;
/* Default extraction routine.
- ATTRS is a mask of the boolean attributes. We only need `unsigned',
- but for generality we take a bitmask of all of them. */
+ INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order,
+ or sometimes less for cases like the m32r where the base insn size is 32
+ but some insns are 16 bits.
+ ATTRS is a mask of the boolean attributes. We only need `UNSIGNED',
+ but for generality we take a bitmask of all of them.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ Returns 1 for success, 0 for failure. */
+
+/* ??? The return code isn't properly used. wip. */
/* ??? This doesn't handle bfd_vma's. Create another function when
necessary. */
static int
-extract_normal (od, ex_info, insn_value, attrs, start, length, total_length, valuep)
+extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length,
+ word_length, total_length, pc, valuep)
CGEN_OPCODE_DESC od;
CGEN_EXTRACT_INFO *ex_info;
- CGEN_INSN_BYTES insn_value;
+ CGEN_INSN_INT insn_value;
unsigned int attrs;
- int start, length, total_length;
+ unsigned int word_offset, start, length, word_length, total_length;
+ bfd_vma pc;
long *valuep;
{
- unsigned long value;
+ CGEN_INSN_INT value;
/* If LENGTH is zero, this operand doesn't contribute to the value
so give it a standard value of zero. */
return 1;
}
-#if CGEN_INT_INSN_P
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
- {
- /* Written this way to avoid undefined behaviour. */
- unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+ if (word_length > 32)
+ abort ();
- if (CGEN_INSN_LSB0_P)
- value = insn_value >> start;
- else
- value = insn_value >> (total_length - (start + length));
- value &= mask;
- /* sign extend? */
- if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
- && (value & (1L << (length - 1))))
- value |= ~mask;
- }
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+#endif
-#else
+ /* Does the value reside in INSN_VALUE? */
- /* The hard case is probably too slow for the normal cases.
- It's certainly more difficult to understand than the normal case.
- Thus this is split into two. Keep it that way. The hard case is defined
- to be when a field straddles a (loosely defined) word boundary
- (??? which may require target specific help to determine). */
+ if (word_offset == 0)
+ {
+ /* Written this way to avoid undefined behaviour. */
+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
-#if 0 /*wip*/
+ if (CGEN_INSN_LSB0_P)
+ value = insn_value >> ((start + 1) - length);
+ else
+ value = insn_value >> (word_length - (start + length));
+ value &= mask;
+ /* sign extend? */
+ if (! CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)
+ && (value & (1L << (length - 1))))
+ value |= ~mask;
+ }
-#define HARD_CASE_P 0 /* FIXME:wip */
+#if ! CGEN_INT_INSN_P
- if (HARD_CASE_P)
- {
- }
-#endif
else
{
- unsigned char *bufp = (unsigned char *) insn_value;
+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
- if (length > 32)
+ if (word_length > 32)
abort ();
- /* Adjust start,total_length,bufp to point to the pseudo-word that holds
- the value. For example in a 48 bit insn where the value to insert
- (say an immediate value) is the last 16 bits then word_length here
- would be 16. To handle a 24 bit insn with an 18 bit immediate,
- extract_1 handles 24 bits (using a combination of bfd_get8,16). */
-
- if (total_length > 32)
- {
- int needed_width = start % 8 + length;
- int fetch_length = (needed_width <= 8 ? 8
- : needed_width <= 16 ? 16
- : 32);
-
- if (CGEN_INSN_LSB0_P)
- {
- if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
- {
- abort (); /* wip */
- }
- else
- {
- int offset = start & ~7;
-
- bufp += offset / 8;
- start -= offset;
- total_length -= offset;
- }
- }
- else
- {
- if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
- {
- int offset = start & ~7;
-
- bufp += offset / 8;
- start -= offset;
- total_length -= offset;
- }
- else
- {
- abort (); /* wip */
- }
- }
- }
+ if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+ return 0;
- /* FIXME: which bytes are being extracted have been lost. */
- value = extract_1 (od, ex_info, start, length, total_length, bufp);
+ value = extract_1 (od, ex_info, start, length, word_length, bufp, pc);
}
#endif /* ! CGEN_INT_INSN_P */
*valuep = value;
- /* FIXME: for now */
return 1;
}
CGEN_OPCODE_DESC od;
const CGEN_INSN *insn;
CGEN_EXTRACT_INFO *ex_info;
- unsigned long insn_value;
+ CGEN_INSN_INT insn_value;
CGEN_FIELDS *fields;
bfd_vma pc;
{
ex_info.dis_info = info;
ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1;
- ex_info.bytes = buf;
+ ex_info.insn_bytes = buf;
switch (buflen)
{
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the extract
handler. */
- if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ if ((insn_value & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
{
/* Printing is handled in two passes. The first pass parses the
machine insn and extracts the fields. The second pass prints
}
static const char *
-parse_register_list (od, strp, opindex, valuep, high_low)
+parse_register_list (od, strp, opindex, valuep, high_low, load_store)
CGEN_OPCODE_DESC od;
const char **strp;
int opindex;
unsigned long *valuep;
- int high_low;
+ int high_low; /* 0 == high, 1 == low */
+ int load_store; /* 0 == load, 1 == store */
{
int regno;
*valuep = 0;
if (high_low)
regno -= 8;
- *valuep |= 1 << regno;
+ if (load_store) /* mask is reversed for store */
+ *valuep |= 0x80 >> regno;
+ else
+ *valuep |= 1 << regno;
if (**strp == ',')
{
}
static const char *
-parse_low_register_list (od, strp, opindex, valuep)
+parse_low_register_list_ld (od, strp, opindex, valuep)
CGEN_OPCODE_DESC od;
const char **strp;
int opindex;
unsigned long *valuep;
{
- return parse_register_list (od, strp, opindex, valuep, 0/*low*/);
+ return parse_register_list (od, strp, opindex, valuep, 0/*low*/, 0/*load*/);
}
static const char *
-parse_hi_register_list (od, strp, opindex, valuep)
+parse_hi_register_list_ld (od, strp, opindex, valuep)
CGEN_OPCODE_DESC od;
const char **strp;
int opindex;
unsigned long *valuep;
{
- return parse_register_list (od, strp, opindex, valuep, 1/*high*/);
+ return parse_register_list (od, strp, opindex, valuep, 1/*high*/, 0/*load*/);
+}
+
+static const char *
+parse_low_register_list_st (od, strp, opindex, valuep)
+ CGEN_OPCODE_DESC od;
+ const char **strp;
+ int opindex;
+ unsigned long *valuep;
+{
+ return parse_register_list (od, strp, opindex, valuep, 0/*low*/, 1/*store*/);
+}
+
+static const char *
+parse_hi_register_list_st (od, strp, opindex, valuep)
+ CGEN_OPCODE_DESC od;
+ const char **strp;
+ int opindex;
+ unsigned long *valuep;
+{
+ return parse_register_list (od, strp, opindex, valuep, 1/*high*/, 1/*store*/);
}
/* -- */
fields->f_rel12 = value;
}
break;
- case FR30_OPERAND_REGLIST_LOW :
- errmsg = parse_low_register_list (od, strp, FR30_OPERAND_REGLIST_LOW, &fields->f_reglist_low);
+ case FR30_OPERAND_REGLIST_LOW_LD :
+ errmsg = parse_low_register_list_ld (od, strp, FR30_OPERAND_REGLIST_LOW_LD, &fields->f_reglist_low_ld);
+ break;
+ case FR30_OPERAND_REGLIST_HI_LD :
+ errmsg = parse_hi_register_list_ld (od, strp, FR30_OPERAND_REGLIST_HI_LD, &fields->f_reglist_hi_ld);
+ break;
+ case FR30_OPERAND_REGLIST_LOW_ST :
+ errmsg = parse_low_register_list_st (od, strp, FR30_OPERAND_REGLIST_LOW_ST, &fields->f_reglist_low_st);
break;
- case FR30_OPERAND_REGLIST_HI :
- errmsg = parse_hi_register_list (od, strp, FR30_OPERAND_REGLIST_HI, &fields->f_reglist_hi);
+ case FR30_OPERAND_REGLIST_HI_ST :
+ errmsg = parse_hi_register_list_st (od, strp, FR30_OPERAND_REGLIST_HI_ST, &fields->f_reglist_hi_st);
break;
case FR30_OPERAND_CC :
errmsg = cgen_parse_unsigned_integer (od, strp, FR30_OPERAND_CC, &fields->f_cc);
}
break;
case FR30_OPERAND_DISP8 :
- errmsg = insert_normal (od, fields->f_disp8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 0, 4, 8, 16, total_length, buffer);
+ errmsg = insert_normal (od, fields->f_disp8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, buffer);
break;
case FR30_OPERAND_DISP9 :
{
long value = fields->f_disp9;
value = ((int) (value) >> (1));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 0, 4, 8, 16, total_length, buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_DISP10 :
{
long value = fields->f_disp10;
value = ((int) (value) >> (2));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 0, 4, 8, 16, total_length, buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_S10 :
{
long value = fields->f_s10;
value = ((int) (value) >> (2));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 0, 8, 8, 16, total_length, buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_U10 :
{
long value = fields->f_rel9;
value = ((int) (((value) - (((pc) + (2))))) >> (1));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 8, 8, 16, total_length, buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 16, total_length, buffer);
}
break;
case FR30_OPERAND_LABEL12 :
{
long value = fields->f_rel12;
value = ((int) (((value) - (((pc) + (2))))) >> (1));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 5, 11, 16, total_length, buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 5, 11, 16, total_length, buffer);
}
break;
- case FR30_OPERAND_REGLIST_LOW :
- errmsg = insert_normal (od, fields->f_reglist_low, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
+ case FR30_OPERAND_REGLIST_LOW_LD :
+ errmsg = insert_normal (od, fields->f_reglist_low_ld, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
+ break;
+ case FR30_OPERAND_REGLIST_HI_LD :
+ errmsg = insert_normal (od, fields->f_reglist_hi_ld, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
+ break;
+ case FR30_OPERAND_REGLIST_LOW_ST :
+ errmsg = insert_normal (od, fields->f_reglist_low_st, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
break;
- case FR30_OPERAND_REGLIST_HI :
- errmsg = insert_normal (od, fields->f_reglist_hi, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
+ case FR30_OPERAND_REGLIST_HI_ST :
+ errmsg = insert_normal (od, fields->f_reglist_hi_st, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, buffer);
break;
case FR30_OPERAND_CC :
errmsg = insert_normal (od, fields->f_cc, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 16, total_length, buffer);
#endif
/* Ensure VALUE will fit. */
- if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0)
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
{
unsigned long maxval = mask;
if ((unsigned long) value > maxval)
/* -- dis.c */
static void
-print_register_list (dis_info, value, offset)
+print_register_list (dis_info, value, offset, load_store)
PTR dis_info;
long value;
long offset;
+ int load_store; /* 0 == load, 1 == store */
{
disassemble_info *info = dis_info;
- int mask = 1;
+ int mask;
int index = 0;
+ char* comma = "";
- if (value & mask)
- (*info->fprintf_func) (info->stream, "r%i", index + offset);
+ if (load_store)
+ mask = 0x80;
+ else
+ mask = 1;
+ if (value & mask)
+ {
+ (*info->fprintf_func) (info->stream, "r%i", index + offset);
+ comma = ",";
+ }
+
for (index = 1; index <= 7; ++index)
{
- mask <<= 1;
+ if (load_store)
+ mask >>= 1;
+ else
+ mask <<= 1;
+
if (value & mask)
- (*info->fprintf_func) (info->stream, ",r%i", index + offset);
+ {
+ (*info->fprintf_func) (info->stream, "%sr%i", comma, index + offset);
+ comma = ",";
+ }
}
}
static void
-print_hi_register_list (od, dis_info, value, attrs, pc, length)
+print_hi_register_list_ld (od, dis_info, value, attrs, pc, length)
+ CGEN_OPCODE_DESC od;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ print_register_list (dis_info, value, 8, 0/*load*/);
+}
+
+static void
+print_low_register_list_ld (od, dis_info, value, attrs, pc, length)
CGEN_OPCODE_DESC od;
PTR dis_info;
long value;
bfd_vma pc;
int length;
{
- print_register_list (dis_info, value, 8);
+ print_register_list (dis_info, value, 0, 0/*load*/);
}
static void
-print_low_register_list (od, dis_info, value, attrs, pc, length)
+print_hi_register_list_st (od, dis_info, value, attrs, pc, length)
CGEN_OPCODE_DESC od;
PTR dis_info;
long value;
bfd_vma pc;
int length;
{
- print_register_list (dis_info, value, 0);
+ print_register_list (dis_info, value, 8, 1/*store*/);
+}
+
+static void
+print_low_register_list_st (od, dis_info, value, attrs, pc, length)
+ CGEN_OPCODE_DESC od;
+ PTR dis_info;
+ long value;
+ unsigned int attrs;
+ bfd_vma pc;
+ int length;
+{
+ print_register_list (dis_info, value, 0, 1/*store*/);
}
static void
}
break;
case FR30_OPERAND_DISP8 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 0, 4, 8, 16, total_length, pc, & fields->f_disp8);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, pc, & fields->f_disp8);
break;
case FR30_OPERAND_DISP9 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, pc, & value);
value = ((value) << (1));
fields->f_disp9 = value;
}
case FR30_OPERAND_DISP10 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 0, 4, 8, 16, total_length, pc, & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 4, 8, 16, total_length, pc, & value);
value = ((value) << (2));
fields->f_disp10 = value;
}
case FR30_OPERAND_S10 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), 0, 8, 8, 16, total_length, pc, & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 16, total_length, pc, & value);
value = ((value) << (2));
fields->f_s10 = value;
}
case FR30_OPERAND_LABEL9 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 8, 8, 16, total_length, pc, & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 16, total_length, pc, & value);
value = ((((value) << (1))) + (((pc) + (2))));
fields->f_rel9 = value;
}
case FR30_OPERAND_LABEL12 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), 0, 5, 11, 16, total_length, pc, & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 5, 11, 16, total_length, pc, & value);
value = ((((value) << (1))) + (((pc) + (2))));
fields->f_rel12 = value;
}
break;
- case FR30_OPERAND_REGLIST_LOW :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low);
+ case FR30_OPERAND_REGLIST_LOW_LD :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_ld);
break;
- case FR30_OPERAND_REGLIST_HI :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi);
+ case FR30_OPERAND_REGLIST_HI_LD :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld);
+ break;
+ case FR30_OPERAND_REGLIST_LOW_ST :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_low_st);
+ break;
+ case FR30_OPERAND_REGLIST_HI_ST :
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_st);
break;
case FR30_OPERAND_CC :
length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 16, total_length, pc, & fields->f_cc);
print_normal (od, info, fields->f_udisp6, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
case FR30_OPERAND_DISP8 :
- print_normal (od, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ print_normal (od, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
case FR30_OPERAND_DISP9 :
- print_normal (od, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ print_normal (od, info, fields->f_disp9, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
case FR30_OPERAND_DISP10 :
- print_normal (od, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ print_normal (od, info, fields->f_disp10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
case FR30_OPERAND_S10 :
- print_normal (od, info, fields->f_s10, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ print_normal (od, info, fields->f_s10, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
case FR30_OPERAND_U10 :
print_normal (od, info, fields->f_u10, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
print_normal (od, info, fields->f_dir10, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
case FR30_OPERAND_LABEL9 :
- print_address (od, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ print_address (od, info, fields->f_rel9, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case FR30_OPERAND_LABEL12 :
- print_address (od, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ print_address (od, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ break;
+ case FR30_OPERAND_REGLIST_LOW_LD :
+ print_low_register_list_ld (od, info, fields->f_reglist_low_ld, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ break;
+ case FR30_OPERAND_REGLIST_HI_LD :
+ print_hi_register_list_ld (od, info, fields->f_reglist_hi_ld, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
- case FR30_OPERAND_REGLIST_LOW :
- print_low_register_list (od, info, fields->f_reglist_low, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ case FR30_OPERAND_REGLIST_LOW_ST :
+ print_low_register_list_st (od, info, fields->f_reglist_low_st, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
- case FR30_OPERAND_REGLIST_HI :
- print_hi_register_list (od, info, fields->f_reglist_hi, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
+ case FR30_OPERAND_REGLIST_HI_ST :
+ print_hi_register_list_st (od, info, fields->f_reglist_hi_st, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
case FR30_OPERAND_CC :
print_normal (od, info, fields->f_cc, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
value = insn_value >> (word_length - (start + length));
value &= mask;
/* sign extend? */
- if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
+ if (! CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)
&& (value & (1L << (length - 1))))
value |= ~mask;
}
}
/* Attributes. */
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
static const CGEN_ATTR_ENTRY MACH_attr[] =
{
{ "base", MACH_BASE },
{ 0, 0 }
};
+const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
{
- { "CACHE-ADDR", NULL },
- { "FUN-ACCESS", NULL },
- { "PC", NULL },
- { "PROFILE", NULL },
- { 0, 0 }
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
};
const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
{
- { "ABS-ADDR", NULL },
- { "HASH-PREFIX", NULL },
- { "NEGATIVE", NULL },
- { "PCREL-ADDR", NULL },
- { "RELAX", NULL },
- { "SEM-ONLY", NULL },
- { "SIGN-OPT", NULL },
- { "SIGNED", NULL },
- { "UNSIGNED", NULL },
- { "VIRTUAL", NULL },
- { 0, 0 }
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
};
const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
{
- { "ALIAS", NULL },
- { "COND-CTI", NULL },
- { "DELAY-SLOT", NULL },
- { "NO-DIS", NULL },
- { "NOT-IN-DELAY-SLOT", NULL },
- { "RELAX", NULL },
- { "RELAXABLE", NULL },
- { "SKIP-CTI", NULL },
- { "UNCOND-CTI", NULL },
- { "VIRTUAL", NULL },
- { 0, 0 }
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
};
CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_gr_entries[] =
#define HW_ENT(n) fr30_cgen_hw_entries[n]
static const CGEN_HW_ENTRY fr30_cgen_hw_entries[] =
{
- { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
- { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
- { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { 0, 0, { 0 } } },
- { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, 0, { 0 } } },
- { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, 0, { 0 } } },
- { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, 0, { 0 } } },
- { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
- { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_FUN_ACCESS), { 0 } } },
+ { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
+ { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
+ { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_cr, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_DR, & HW_ENT (HW_H_DR + 1), "h-dr", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_dr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
+ { HW_H_PS, & HW_ENT (HW_H_PS + 1), "h-ps", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
+ { HW_H_R13, & HW_ENT (HW_H_R13 + 1), "h-r13", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_R14, & HW_ENT (HW_H_R14 + 1), "h-r14", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_R15, & HW_ENT (HW_H_R15 + 1), "h-r15", CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_NBIT, & HW_ENT (HW_H_NBIT + 1), "h-nbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_ZBIT, & HW_ENT (HW_H_ZBIT + 1), "h-zbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_VBIT, & HW_ENT (HW_H_VBIT + 1), "h-vbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_CBIT, & HW_ENT (HW_H_CBIT + 1), "h-cbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_IBIT, & HW_ENT (HW_H_IBIT + 1), "h-ibit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_SBIT, & HW_ENT (HW_H_SBIT + 1), "h-sbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
+ { HW_H_TBIT, & HW_ENT (HW_H_TBIT + 1), "h-tbit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_D0BIT, & HW_ENT (HW_H_D0BIT + 1), "h-d0bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_D1BIT, & HW_ENT (HW_H_D1BIT + 1), "h-d1bit", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_CCR, & HW_ENT (HW_H_CCR + 1), "h-ccr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
+ { HW_H_SCR, & HW_ENT (HW_H_SCR + 1), "h-scr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
+ { HW_H_ILM, & HW_ENT (HW_H_ILM + 1), "h-ilm", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_FUN_ACCESS), { (1<<MACH_BASE) } } },
{ 0 }
};
static const CGEN_IFLD fr30_cgen_ifld_table[] =
{
- { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
- { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
- { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
- { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
- { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
- { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_SIGNED), { 0 } } },
- { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
- { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0, 0|(1<<CGEN_IFLD_PCREL_ADDR)|(1<<CGEN_IFLD_SIGNED), { 0 } } },
- { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
+ { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_CC, "f-cc", 0, 16, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_U4, "f-u4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_I4, "f-i4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { FR30_F_M4, "f-m4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_U8, "f-u8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_I8, "f-i8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_I32, "f-i32", 16, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { FR30_F_S10, "f-s10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { FR30_F_U10, "f-u10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
{ 0 }
};
{
/* pc: program counter */
{ "pc", & HW_ENT (HW_H_PC), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* Ri: destination register */
{ "Ri", & HW_ENT (HW_H_GR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* Rj: source register */
{ "Rj", & HW_ENT (HW_H_GR), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* Ric: target register coproc insn */
{ "Ric", & HW_ENT (HW_H_GR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* Rjc: source register coproc insn */
{ "Rjc", & HW_ENT (HW_H_GR), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* CRi: coprocessor register */
{ "CRi", & HW_ENT (HW_H_CR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* CRj: coprocessor register */
{ "CRj", & HW_ENT (HW_H_CR), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* Rs1: dedicated register */
{ "Rs1", & HW_ENT (HW_H_DR), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* Rs2: dedicated register */
{ "Rs2", & HW_ENT (HW_H_DR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* R13: General Register 13 */
{ "R13", & HW_ENT (HW_H_R13), 0, 0,
- { 0, 0, { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
/* R14: General Register 14 */
{ "R14", & HW_ENT (HW_H_R14), 0, 0,
- { 0, 0, { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
/* R15: General Register 15 */
{ "R15", & HW_ENT (HW_H_R15), 0, 0,
- { 0, 0, { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
/* ps: Program Status register */
{ "ps", & HW_ENT (HW_H_PS), 0, 0,
- { 0, 0, { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
/* u4: 4 bit unsigned immediate */
{ "u4", & HW_ENT (HW_H_UINT), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", & HW_ENT (HW_H_UINT), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* u8: 8 bit unsigned immediate */
{ "u8", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* i8: 8 bit unsigned immediate */
{ "i8", & HW_ENT (HW_H_UINT), 4, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", & HW_ENT (HW_H_UINT), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* disp8: 8 bit signed immediate */
{ "disp8", & HW_ENT (HW_H_SINT), 4, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp9: 9 bit signed immediate */
{ "disp9", & HW_ENT (HW_H_SINT), 4, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp10: 10 bit signed immediate */
{ "disp10", & HW_ENT (HW_H_SINT), 4, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s10: 10 bit signed immediate */
{ "s10", & HW_ENT (HW_H_SINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u10: 10 bit unsigned immediate */
{ "u10", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* i32: 32 bit immediate */
{ "i32", & HW_ENT (HW_H_UINT), 0, 32,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* m4: 4 bit negative immediate */
{ "m4", & HW_ENT (HW_H_SINT), 8, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* i20: 20 bit immediate */
{ "i20", & HW_ENT (HW_H_UINT), 0, 20,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED)|(1<<CGEN_OPERAND_VIRTUAL), { (1<<MACH_BASE) } } },
/* dir8: 8 bit direct address */
{ "dir8", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* dir9: 9 bit direct address */
{ "dir9", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* dir10: 10 bit direct address */
{ "dir10", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* label9: 9 bit pc relative address */
{ "label9", & HW_ENT (HW_H_IADDR), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
/* label12: 12 bit pc relative address */
{ "label12", & HW_ENT (HW_H_IADDR), 5, 11,
- { 0, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_SIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
/* reglist_low_ld: 8 bit register mask for ldm */
{ "reglist_low_ld", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* reglist_hi_ld: 8 bit register mask for ldm */
{ "reglist_hi_ld", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* reglist_low_st: 8 bit register mask for ldm */
{ "reglist_low_st", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* reglist_hi_st: 8 bit register mask for ldm */
{ "reglist_hi_st", & HW_ENT (HW_H_UINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* cc: condition codes */
{ "cc", & HW_ENT (HW_H_UINT), 4, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* ccc: coprocessor calc */
{ "ccc", & HW_ENT (HW_H_UINT), 0, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* nbit: negative bit */
{ "nbit", & HW_ENT (HW_H_NBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* vbit: overflow bit */
{ "vbit", & HW_ENT (HW_H_VBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* zbit: zero bit */
{ "zbit", & HW_ENT (HW_H_ZBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* cbit: carry bit */
{ "cbit", & HW_ENT (HW_H_CBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* ibit: interrupt bit */
{ "ibit", & HW_ENT (HW_H_IBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* sbit: stack bit */
{ "sbit", & HW_ENT (HW_H_SBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* tbit: trace trap bit */
{ "tbit", & HW_ENT (HW_H_TBIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* d0bit: division 0 bit */
{ "d0bit", & HW_ENT (HW_H_D0BIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* d1bit: division 1 bit */
{ "d1bit", & HW_ENT (HW_H_D1BIT), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* ccr: condition code bits */
{ "ccr", & HW_ENT (HW_H_CCR), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* scr: system condition bits */
{ "scr", & HW_ENT (HW_H_SCR), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* ilm: condition code bits */
{ "ilm", & HW_ENT (HW_H_ILM), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
};
/* Operand references. */
#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
+static const CGEN_IFMT fmt_empty = {
+ 0, 0, 0x0, { 0 }
+};
+
static const CGEN_IFMT fmt_add = {
16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
};
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_add, { 0xa600 },
(PTR) & fmt_add_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* add $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_addi, { 0xa400 },
(PTR) & fmt_addi_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* add2 $m4,$Ri */
{
{ { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
& fmt_add2, { 0xa500 },
(PTR) & fmt_add2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addc $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_addc, { 0xa700 },
(PTR) & fmt_addc_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addn $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_addn, { 0xa200 },
(PTR) & fmt_addn_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addn $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_addni, { 0xa000 },
(PTR) & fmt_addni_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addn2 $m4,$Ri */
{
{ { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
& fmt_addn2, { 0xa100 },
(PTR) & fmt_addn2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* sub $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_add, { 0xac00 },
(PTR) & fmt_add_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subc $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_addc, { 0xad00 },
(PTR) & fmt_addc_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subn $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_addn, { 0xae00 },
(PTR) & fmt_addn_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmp $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_cmp, { 0xaa00 },
(PTR) & fmt_cmp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmp $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_cmpi, { 0xa800 },
(PTR) & fmt_cmpi_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmp2 $m4,$Ri */
{
{ { MNEM, ' ', OP (M4), ',', OP (RI), 0 } },
& fmt_cmp2, { 0xa900 },
(PTR) & fmt_cmp2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_and, { 0x8200 },
(PTR) & fmt_and_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_and, { 0x9200 },
(PTR) & fmt_and_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* eor $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_and, { 0x9a00 },
(PTR) & fmt_and_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andm, { 0x8400 },
(PTR) & fmt_andm_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* andh $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andh, { 0x8500 },
(PTR) & fmt_andh_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* andb $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andb, { 0x8600 },
(PTR) & fmt_andb_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* or $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andm, { 0x9400 },
(PTR) & fmt_andm_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* orh $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andh, { 0x9500 },
(PTR) & fmt_andh_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* orb $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andb, { 0x9600 },
(PTR) & fmt_andb_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* eor $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andm, { 0x9c00 },
(PTR) & fmt_andm_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* eorh $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andh, { 0x9d00 },
(PTR) & fmt_andh_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* eorb $Rj,@$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', '@', OP (RI), 0 } },
& fmt_andb, { 0x9e00 },
(PTR) & fmt_andb_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bandl $u4,@$Ri */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x8000 },
(PTR) & fmt_bandl_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* borl $u4,@$Ri */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x9000 },
(PTR) & fmt_bandl_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* beorl $u4,@$Ri */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x9800 },
(PTR) & fmt_bandl_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bandh $u4,@$Ri */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x8100 },
(PTR) & fmt_bandl_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* borh $u4,@$Ri */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x9100 },
(PTR) & fmt_bandl_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* beorh $u4,@$Ri */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_bandl, { 0x9900 },
(PTR) & fmt_bandl_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* btstl $u4,@$Ri */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_btstl, { 0x8800 },
(PTR) & fmt_btstl_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* btsth $u4,@$Ri */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), 0 } },
& fmt_btstl, { 0x8900 },
(PTR) & fmt_btstl_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* mul $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mul, { 0xaf00 },
(PTR) & fmt_mul_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* mulu $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mulu, { 0xab00 },
(PTR) & fmt_mulu_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* mulh $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mulh, { 0xbf00 },
(PTR) & fmt_mulh_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* muluh $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mulh, { 0xbb00 },
(PTR) & fmt_mulh_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* div0s $Ri */
{
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_div0s, { 0x9740 },
(PTR) & fmt_div0s_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div0u $Ri */
{
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_div0u, { 0x9750 },
(PTR) & fmt_div0u_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div1 $Ri */
{
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_div1, { 0x9760 },
(PTR) & fmt_div1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div2 $Ri */
{
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_div2, { 0x9770 },
(PTR) & fmt_div2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div3 */
{
{ { MNEM, 0 } },
& fmt_div3, { 0x9f60 },
(PTR) & fmt_div3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* div4s */
{
{ { MNEM, 0 } },
& fmt_div4s, { 0x9f70 },
(PTR) & fmt_div4s_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsl $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_lsl, { 0xb600 },
(PTR) & fmt_lsl_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsl $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb400 },
(PTR) & fmt_lsli_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsl2 $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb500 },
(PTR) & fmt_lsli_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsr $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_lsl, { 0xb200 },
(PTR) & fmt_lsl_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsr $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb000 },
(PTR) & fmt_lsli_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lsr2 $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb100 },
(PTR) & fmt_lsli_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* asr $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_lsl, { 0xba00 },
(PTR) & fmt_lsl_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* asr $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb800 },
(PTR) & fmt_lsli_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* asr2 $u4,$Ri */
{
{ { MNEM, ' ', OP (U4), ',', OP (RI), 0 } },
& fmt_lsli, { 0xb900 },
(PTR) & fmt_lsli_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldi:8 $i8,$Ri */
{
{ { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
& fmt_ldi8, { 0xc000 },
(PTR) & fmt_ldi8_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldi:20 $i20,$Ri */
{
{ { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
& fmt_ldi20, { 0x9b00 },
(PTR) & fmt_ldi20_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ldi:32 $i32,$Ri */
{
{ { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
& fmt_ldi32, { 0x9f80 },
(PTR) & fmt_ldi32_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ld @$Rj,$Ri */
{
{ { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
& fmt_ld, { 0x400 },
(PTR) & fmt_ld_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lduh @$Rj,$Ri */
{
{ { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
& fmt_lduh, { 0x500 },
(PTR) & fmt_lduh_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldub @$Rj,$Ri */
{
{ { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
& fmt_ldub, { 0x600 },
(PTR) & fmt_ldub_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @($R13,$Rj),$Ri */
{
{ { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
& fmt_ldr13, { 0x0 },
(PTR) & fmt_ldr13_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lduh @($R13,$Rj),$Ri */
{
{ { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
& fmt_ldr13uh, { 0x100 },
(PTR) & fmt_ldr13uh_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldub @($R13,$Rj),$Ri */
{
{ { MNEM, ' ', '@', '(', OP (R13), ',', OP (RJ), ')', ',', OP (RI), 0 } },
& fmt_ldr13ub, { 0x200 },
(PTR) & fmt_ldr13ub_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @($R14,$disp10),$Ri */
{
{ { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP10), ')', ',', OP (RI), 0 } },
& fmt_ldr14, { 0x2000 },
(PTR) & fmt_ldr14_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lduh @($R14,$disp9),$Ri */
{
{ { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP9), ')', ',', OP (RI), 0 } },
& fmt_ldr14uh, { 0x4000 },
(PTR) & fmt_ldr14uh_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldub @($R14,$disp8),$Ri */
{
{ { MNEM, ' ', '@', '(', OP (R14), ',', OP (DISP8), ')', ',', OP (RI), 0 } },
& fmt_ldr14ub, { 0x6000 },
(PTR) & fmt_ldr14ub_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @($R15,$udisp6),$Ri */
{
{ { MNEM, ' ', '@', '(', OP (R15), ',', OP (UDISP6), ')', ',', OP (RI), 0 } },
& fmt_ldr15, { 0x300 },
(PTR) & fmt_ldr15_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @$R15+,$Ri */
{
{ { MNEM, ' ', '@', OP (R15), '+', ',', OP (RI), 0 } },
& fmt_ldr15gr, { 0x700 },
(PTR) & fmt_ldr15gr_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @$R15+,$Rs2 */
{
{ { MNEM, ' ', '@', OP (R15), '+', ',', OP (RS2), 0 } },
& fmt_ldr15dr, { 0x780 },
(PTR) & fmt_ldr15dr_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld @$R15+,$ps */
{
{ { MNEM, ' ', '@', OP (R15), '+', ',', OP (PS), 0 } },
& fmt_ldr15ps, { 0x790 },
(PTR) & fmt_ldr15ps_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* st $Ri,@$Rj */
{
{ { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
& fmt_st, { 0x1400 },
(PTR) & fmt_st_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* sth $Ri,@$Rj */
{
{ { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
& fmt_sth, { 0x1500 },
(PTR) & fmt_sth_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stb $Ri,@$Rj */
{
{ { MNEM, ' ', OP (RI), ',', '@', OP (RJ), 0 } },
& fmt_stb, { 0x1600 },
(PTR) & fmt_stb_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Ri,@($R13,$Rj) */
{
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
& fmt_str13, { 0x1000 },
(PTR) & fmt_str13_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* sth $Ri,@($R13,$Rj) */
{
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
& fmt_str13h, { 0x1100 },
(PTR) & fmt_str13h_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stb $Ri,@($R13,$Rj) */
{
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R13), ',', OP (RJ), ')', 0 } },
& fmt_str13b, { 0x1200 },
(PTR) & fmt_str13b_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Ri,@($R14,$disp10) */
{
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP10), ')', 0 } },
& fmt_str14, { 0x3000 },
(PTR) & fmt_str14_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* sth $Ri,@($R14,$disp9) */
{
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP9), ')', 0 } },
& fmt_str14h, { 0x5000 },
(PTR) & fmt_str14h_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stb $Ri,@($R14,$disp8) */
{
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R14), ',', OP (DISP8), ')', 0 } },
& fmt_str14b, { 0x7000 },
(PTR) & fmt_str14b_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Ri,@($R15,$udisp6) */
{
{ { MNEM, ' ', OP (RI), ',', '@', '(', OP (R15), ',', OP (UDISP6), ')', 0 } },
& fmt_str15, { 0x1300 },
(PTR) & fmt_str15_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Ri,@-$R15 */
{
{ { MNEM, ' ', OP (RI), ',', '@', '-', OP (R15), 0 } },
& fmt_str15gr, { 0x1700 },
(PTR) & fmt_str15gr_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $Rs2,@-$R15 */
{
{ { MNEM, ' ', OP (RS2), ',', '@', '-', OP (R15), 0 } },
& fmt_str15dr, { 0x1780 },
(PTR) & fmt_str15dr_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $ps,@-$R15 */
{
{ { MNEM, ' ', OP (PS), ',', '@', '-', OP (R15), 0 } },
& fmt_str15ps, { 0x1790 },
(PTR) & fmt_str15ps_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $Rj,$Ri */
{
{ { MNEM, ' ', OP (RJ), ',', OP (RI), 0 } },
& fmt_mov, { 0x8b00 },
(PTR) & fmt_mov_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $Rs1,$Ri */
{
{ { MNEM, ' ', OP (RS1), ',', OP (RI), 0 } },
& fmt_movdr, { 0xb700 },
(PTR) & fmt_movdr_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $ps,$Ri */
{
{ { MNEM, ' ', OP (PS), ',', OP (RI), 0 } },
& fmt_movps, { 0x1710 },
(PTR) & fmt_movps_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $Ri,$Rs1 */
{
{ { MNEM, ' ', OP (RI), ',', OP (RS1), 0 } },
& fmt_mov2dr, { 0xb300 },
(PTR) & fmt_mov2dr_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $Ri,$ps */
{
{ { MNEM, ' ', OP (RI), ',', OP (PS), 0 } },
& fmt_mov2ps, { 0x710 },
(PTR) & fmt_mov2ps_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* jmp @$Ri */
{
{ { MNEM, ' ', '@', OP (RI), 0 } },
& fmt_jmp, { 0x9700 },
(PTR) & fmt_jmp_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* jmp:d @$Ri */
{
{ { MNEM, ' ', '@', OP (RI), 0 } },
& fmt_jmp, { 0x9f00 },
(PTR) & fmt_jmp_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* call @$Ri */
{
{ { MNEM, ' ', '@', OP (RI), 0 } },
& fmt_callr, { 0x9710 },
(PTR) & fmt_callr_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* call:d @$Ri */
{
{ { MNEM, ' ', '@', OP (RI), 0 } },
& fmt_callr, { 0x9f10 },
(PTR) & fmt_callr_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* call $label12 */
{
{ { MNEM, ' ', OP (LABEL12), 0 } },
& fmt_call, { 0xd000 },
(PTR) & fmt_call_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* call:d $label12 */
{
{ { MNEM, ' ', OP (LABEL12), 0 } },
& fmt_call, { 0xd800 },
(PTR) & fmt_call_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ret */
{
{ { MNEM, 0 } },
& fmt_ret, { 0x9720 },
(PTR) & fmt_ret_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* ret:d */
{
{ { MNEM, 0 } },
& fmt_ret, { 0x9f20 },
(PTR) & fmt_ret_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* int $u8 */
{
{ { MNEM, ' ', OP (U8), 0 } },
& fmt_int, { 0x1f00 },
(PTR) & fmt_int_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* inte */
{
{ { MNEM, 0 } },
& fmt_inte, { 0x9f30 },
(PTR) & fmt_inte_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* reti */
{
{ { MNEM, 0 } },
& fmt_reti, { 0x9730 },
(PTR) & fmt_reti_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bra:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_brad, { 0xf000 },
(PTR) & fmt_brad_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bra $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_brad, { 0xe000 },
(PTR) & fmt_brad_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bno:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_brad, { 0xf100 },
(PTR) & fmt_brad_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bno $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_brad, { 0xe100 },
(PTR) & fmt_brad_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* beq:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_beqd, { 0xf200 },
(PTR) & fmt_beqd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* beq $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_beqd, { 0xe200 },
(PTR) & fmt_beqd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bne:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_beqd, { 0xf300 },
(PTR) & fmt_beqd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bne $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_beqd, { 0xe300 },
(PTR) & fmt_beqd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bc:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bcd, { 0xf400 },
(PTR) & fmt_bcd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bc $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bcd, { 0xe400 },
(PTR) & fmt_bcd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bnc:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bcd, { 0xf500 },
(PTR) & fmt_bcd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bnc $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bcd, { 0xe500 },
(PTR) & fmt_bcd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bn:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bnd, { 0xf600 },
(PTR) & fmt_bnd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bn $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bnd, { 0xe600 },
(PTR) & fmt_bnd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bp:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bnd, { 0xf700 },
(PTR) & fmt_bnd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bp $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bnd, { 0xe700 },
(PTR) & fmt_bnd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bv:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bvd, { 0xf800 },
(PTR) & fmt_bvd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bv $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bvd, { 0xe800 },
(PTR) & fmt_bvd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bnv:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bvd, { 0xf900 },
(PTR) & fmt_bvd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bnv $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bvd, { 0xe900 },
(PTR) & fmt_bvd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* blt:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bltd, { 0xfa00 },
(PTR) & fmt_bltd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* blt $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bltd, { 0xea00 },
(PTR) & fmt_bltd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bge:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bltd, { 0xfb00 },
(PTR) & fmt_bltd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bge $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bltd, { 0xeb00 },
(PTR) & fmt_bltd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ble:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bled, { 0xfc00 },
(PTR) & fmt_bled_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ble $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bled, { 0xec00 },
(PTR) & fmt_bled_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bgt:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bled, { 0xfd00 },
(PTR) & fmt_bled_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bgt $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_bled, { 0xed00 },
(PTR) & fmt_bled_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bls:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_blsd, { 0xfe00 },
(PTR) & fmt_blsd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bls $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_blsd, { 0xee00 },
(PTR) & fmt_blsd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bhi:d $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_blsd, { 0xff00 },
(PTR) & fmt_blsd_ops[0],
- { 0, 0|A(COND_CTI)|A(DELAY_SLOT)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* bhi $label9 */
{
{ { MNEM, ' ', OP (LABEL9), 0 } },
& fmt_blsd, { 0xef00 },
(PTR) & fmt_blsd_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI)|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmov $R13,@$dir10 */
{
{ { MNEM, ' ', OP (R13), ',', '@', OP (DIR10), 0 } },
& fmt_dmovr13, { 0x1800 },
(PTR) & fmt_dmovr13_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmovh $R13,@$dir9 */
{
{ { MNEM, ' ', OP (R13), ',', '@', OP (DIR9), 0 } },
& fmt_dmovr13h, { 0x1900 },
(PTR) & fmt_dmovr13h_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmovb $R13,@$dir8 */
{
{ { MNEM, ' ', OP (R13), ',', '@', OP (DIR8), 0 } },
& fmt_dmovr13b, { 0x1a00 },
(PTR) & fmt_dmovr13b_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmov @$R13+,@$dir10 */
{
{ { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR10), 0 } },
& fmt_dmovr13pi, { 0x1c00 },
(PTR) & fmt_dmovr13pi_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmovh @$R13+,@$dir9 */
{
{ { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR9), 0 } },
& fmt_dmovr13pih, { 0x1d00 },
(PTR) & fmt_dmovr13pih_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmovb @$R13+,@$dir8 */
{
{ { MNEM, ' ', '@', OP (R13), '+', ',', '@', OP (DIR8), 0 } },
& fmt_dmovr13pib, { 0x1e00 },
(PTR) & fmt_dmovr13pib_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmov @$R15+,@$dir10 */
{
{ { MNEM, ' ', '@', OP (R15), '+', ',', '@', OP (DIR10), 0 } },
& fmt_dmovr15pi, { 0x1b00 },
(PTR) & fmt_dmovr15pi_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmov @$dir10,$R13 */
{
{ { MNEM, ' ', '@', OP (DIR10), ',', OP (R13), 0 } },
& fmt_dmov2r13, { 0x800 },
(PTR) & fmt_dmov2r13_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmovh @$dir9,$R13 */
{
{ { MNEM, ' ', '@', OP (DIR9), ',', OP (R13), 0 } },
& fmt_dmov2r13h, { 0x900 },
(PTR) & fmt_dmov2r13h_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmovb @$dir8,$R13 */
{
{ { MNEM, ' ', '@', OP (DIR8), ',', OP (R13), 0 } },
& fmt_dmov2r13b, { 0xa00 },
(PTR) & fmt_dmov2r13b_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* dmov @$dir10,@$R13+ */
{
{ { MNEM, ' ', '@', OP (DIR10), ',', '@', OP (R13), '+', 0 } },
& fmt_dmov2r13pi, { 0xc00 },
(PTR) & fmt_dmov2r13pi_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmovh @$dir9,@$R13+ */
{
{ { MNEM, ' ', '@', OP (DIR9), ',', '@', OP (R13), '+', 0 } },
& fmt_dmov2r13pih, { 0xd00 },
(PTR) & fmt_dmov2r13pih_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmovb @$dir8,@$R13+ */
{
{ { MNEM, ' ', '@', OP (DIR8), ',', '@', OP (R13), '+', 0 } },
& fmt_dmov2r13pib, { 0xe00 },
(PTR) & fmt_dmov2r13pib_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* dmov @$dir10,@-$R15 */
{
{ { MNEM, ' ', '@', OP (DIR10), ',', '@', '-', OP (R15), 0 } },
& fmt_dmov2r15pd, { 0xb00 },
(PTR) & fmt_dmov2r15pd_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ldres @$Ri+,$u4 */
{
{ { MNEM, ' ', '@', OP (RI), '+', ',', OP (U4), 0 } },
& fmt_ldres, { 0xbc00 },
(PTR) & fmt_ldres_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stres $u4,@$Ri+ */
{
{ { MNEM, ' ', OP (U4), ',', '@', OP (RI), '+', 0 } },
& fmt_ldres, { 0xbd00 },
(PTR) & fmt_ldres_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* copop $u4c,$ccc,$CRj,$CRi */
{
{ { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (CRI), 0 } },
& fmt_copop, { 0x9fc0 },
(PTR) 0,
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* copld $u4c,$ccc,$Rjc,$CRi */
{
{ { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (RJC), ',', OP (CRI), 0 } },
& fmt_copld, { 0x9fd0 },
(PTR) 0,
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* copst $u4c,$ccc,$CRj,$Ric */
{
{ { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
& fmt_copst, { 0x9fe0 },
(PTR) 0,
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* copsv $u4c,$ccc,$CRj,$Ric */
{
{ { MNEM, ' ', OP (U4C), ',', OP (CCC), ',', OP (CRJ), ',', OP (RIC), 0 } },
& fmt_copst, { 0x9ff0 },
(PTR) 0,
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* nop */
{
{ { MNEM, 0 } },
& fmt_nop, { 0x9fa0 },
(PTR) 0,
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andccr $u8 */
{
{ { MNEM, ' ', OP (U8), 0 } },
& fmt_andccr, { 0x8300 },
(PTR) & fmt_andccr_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* orccr $u8 */
{
{ { MNEM, ' ', OP (U8), 0 } },
& fmt_andccr, { 0x9300 },
(PTR) & fmt_andccr_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stilm $u8 */
{
{ { MNEM, ' ', OP (U8), 0 } },
& fmt_stilm, { 0x8700 },
(PTR) & fmt_stilm_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addsp $s10 */
{
{ { MNEM, ' ', OP (S10), 0 } },
& fmt_addsp, { 0xa300 },
(PTR) & fmt_addsp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* extsb $Ri */
{
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_extsb, { 0x9780 },
(PTR) & fmt_extsb_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* extub $Ri */
{
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_extub, { 0x9790 },
(PTR) & fmt_extub_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* extsh $Ri */
{
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_extsh, { 0x97a0 },
(PTR) & fmt_extsh_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* extuh $Ri */
{
{ { MNEM, ' ', OP (RI), 0 } },
& fmt_extuh, { 0x97b0 },
(PTR) & fmt_extuh_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldm0 ($reglist_low_ld) */
{
{ { MNEM, ' ', '(', OP (REGLIST_LOW_LD), ')', 0 } },
& fmt_ldm0, { 0x8c00 },
(PTR) & fmt_ldm0_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* ldm1 ($reglist_hi_ld) */
{
{ { MNEM, ' ', '(', OP (REGLIST_HI_LD), ')', 0 } },
& fmt_ldm1, { 0x8d00 },
(PTR) & fmt_ldm1_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* stm0 ($reglist_low_st) */
{
{ { MNEM, ' ', '(', OP (REGLIST_LOW_ST), ')', 0 } },
& fmt_stm0, { 0x8e00 },
(PTR) & fmt_stm0_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* stm1 ($reglist_hi_st) */
{
{ { MNEM, ' ', '(', OP (REGLIST_HI_ST), ')', 0 } },
& fmt_stm1, { 0x8f00 },
(PTR) & fmt_stm1_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* enter $u10 */
{
{ { MNEM, ' ', OP (U10), 0 } },
& fmt_enter, { 0xf00 },
(PTR) & fmt_enter_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
/* leave */
{
{ { MNEM, 0 } },
& fmt_leave, { 0x9f90 },
(PTR) & fmt_leave_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xchb @$Rj,$Ri */
{
{ { MNEM, ' ', '@', OP (RJ), ',', OP (RI), 0 } },
& fmt_xchb, { 0x8a00 },
(PTR) & fmt_xchb_ops[0],
- { 0, 0|A(NOT_IN_DELAY_SLOT), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
},
};
{ { MNEM, ' ', OP (I8), ',', OP (RI), 0 } },
& fmt_ldi8m, { 0xc000 },
(PTR) 0,
- { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
},
/* ldi20 $i20,$Ri */
{
{ { MNEM, ' ', OP (I20), ',', OP (RI), 0 } },
& fmt_ldi20m, { 0x9b00 },
(PTR) 0,
- { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
},
/* ldi32 $i32,$Ri */
{
{ { MNEM, ' ', OP (I32), ',', OP (RI), 0 } },
& fmt_ldi32m, { 0x9f80 },
(PTR) 0,
- { 0, 0|A(NO_DIS)|A(ALIAS), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
},
};
/* Enum declaration for general registers. */
typedef enum h_gr {
- H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_R0 = 0
- , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
- , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
- , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
- , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
+ H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
+ , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
+ , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
+ , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
+ , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
} H_GR;
/* Enum declaration for coprocessor registers. */
H_R15_R15
} H_R15;
-/* Enum declaration for fr30 operand types. */
-typedef enum cgen_operand_type {
- FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
- , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
- , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
- , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
- , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
- , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
- , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
- , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
- , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
- , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
- , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
- , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
- , FR30_OPERAND_ILM, FR30_OPERAND_MAX
-} CGEN_OPERAND_TYPE;
-
-/* Non-boolean attributes. */
+/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
/* Number of architecture variants. */
#define MAX_MACHS ((int) MACH_MAX)
-/* Number of operands types. */
-#define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
-
-/* Maximum number of operands referenced by any insn. */
-#define MAX_OPERAND_INSTANCES 12
-
-/* Hardware, operand and instruction attribute indices. */
-
-/* Enum declaration for cgen_hw attrs. */
-typedef enum cgen_hw_attr {
- CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
-} CGEN_HW_ATTR;
-
-/* Number of non-boolean elements in cgen_hw. */
-#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
-
-/* Hardware, operand and instruction attribute indices. */
+/* Ifield attribute indices. */
/* Enum declaration for cgen_ifld attrs. */
typedef enum cgen_ifld_attr {
- CGEN_IFLD_ABS_ADDR, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT
- , CGEN_IFLD_SIGNED, CGEN_IFLD_UNSIGNED, CGEN_IFLD_VIRTUAL
+ CGEN_IFLD_MACH, CGEN_IFLD_VIRTUAL, CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR
+ , CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT
} CGEN_IFLD_ATTR;
/* Number of non-boolean elements in cgen_ifld. */
-#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_ABS_ADDR)
+#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_VIRTUAL)
/* Enum declaration for fr30 ifield types. */
typedef enum ifield_type {
#define MAX_IFLD ((int) FR30_F_MAX)
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_MACH, CGEN_HW_VIRTUAL, CGEN_HW_UNSIGNED, CGEN_HW_SIGNED
+ , CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw. */
+#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_VIRTUAL)
+
+/* Enum declaration for fr30 hardware types. */
+typedef enum hw_type {
+ HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
+ , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
+ , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
+ , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
+ , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
+ , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
+ , HW_H_ILM, HW_MAX
+} HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
- CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR
- , CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED
- , CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_VIRTUAL
+ CGEN_OPERAND_MACH, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR
+ , CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX
+ , CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_HASH_PREFIX
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand. */
-#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
+#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_VIRTUAL)
+
+/* Enum declaration for fr30 operand types. */
+typedef enum cgen_operand_type {
+ FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
+ , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
+ , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
+ , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
+ , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
+ , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
+ , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
+ , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
+ , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
+ , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
+ , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
+ , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
+ , FR30_OPERAND_ILM, FR30_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS ((int) FR30_OPERAND_MAX)
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 12
+
+/* Insn attribute indices. */
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
- CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_NO_DIS
- , CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI
- , CGEN_INSN_UNCOND_CTI, CGEN_INSN_VIRTUAL
+ CGEN_INSN_MACH, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_ALIAS, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn. */
-#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
+#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_VIRTUAL)
/* Enum declaration for fr30 instruction types. */
typedef enum cgen_insn_type {
extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
-/* Enum declaration for fr30 hardware types. */
-typedef enum hw_type {
- HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
- , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
- , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
- , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
- , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
- , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
- , HW_H_ILM, HW_MAX
-} HW_TYPE;
-
-#define MAX_HW ((int) HW_MAX)
-
/* Hardware decls. */
extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
{
long value = fields->f_br_disp;
value = ((int) (((value) - (pc))) >> (2));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 19, 11, 32, total_length, buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 19, 11, 32, total_length, buffer);
}
break;
case I960_OPERAND_BR_LIT1 :
{
long value = fields->f_ctrl_disp;
value = ((int) (((value) - (pc))) >> (2));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 22, 32, total_length, buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 22, 32, total_length, buffer);
}
break;
#endif
/* Ensure VALUE will fit. */
- if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0)
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
{
unsigned long maxval = mask;
if ((unsigned long) value > maxval)
case I960_OPERAND_BR_DISP :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 19, 11, 32, total_length, pc, & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 19, 11, 32, total_length, pc, & value);
value = ((((value) << (2))) + (pc));
fields->f_br_disp = value;
}
case I960_OPERAND_CTRL_DISP :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 22, 32, total_length, pc, & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 22, 32, total_length, pc, & value);
value = ((((value) << (2))) + (pc));
fields->f_ctrl_disp = value;
}
print_keyword (od, info, & i960_cgen_opval_h_gr, fields->f_br_src2, 0|(1<<CGEN_OPERAND_UNSIGNED));
break;
case I960_OPERAND_BR_DISP :
- print_address (od, info, fields->f_br_disp, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (od, info, fields->f_br_disp, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
case I960_OPERAND_BR_LIT1 :
print_normal (od, info, fields->f_br_src1, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
break;
case I960_OPERAND_CTRL_DISP :
- print_address (od, info, fields->f_ctrl_disp, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+ print_address (od, info, fields->f_ctrl_disp, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
break;
default :
value = insn_value >> (word_length - (start + length));
value &= mask;
/* sign extend? */
- if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
+ if (! CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)
&& (value & (1L << (length - 1))))
value |= ~mask;
}
}
/* Attributes. */
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
static const CGEN_ATTR_ENTRY MACH_attr[] =
{
{ "base", MACH_BASE },
{ 0, 0 }
};
+const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
{
- { "CACHE-ADDR", NULL },
- { "PC", NULL },
- { "PROFILE", NULL },
- { 0, 0 }
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
};
const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
{
- { "ABS-ADDR", NULL },
- { "NEGATIVE", NULL },
- { "PCREL-ADDR", NULL },
- { "RELAX", NULL },
- { "RELOC", NULL },
- { "SEM-ONLY", NULL },
- { "SIGN-OPT", NULL },
- { "UNSIGNED", NULL },
- { 0, 0 }
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
};
const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
{
- { "ALIAS", NULL },
- { "COND-CTI", NULL },
- { "DELAY-SLOT", NULL },
- { "NO-DIS", NULL },
- { "RELAX", NULL },
- { "RELAXABLE", NULL },
- { "SKIP-CTI", NULL },
- { "UNCOND-CTI", NULL },
- { "VIRTUAL", NULL },
- { 0, 0 }
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
};
CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
#define HW_ENT(n) i960_cgen_hw_entries[n]
static const CGEN_HW_ENTRY i960_cgen_hw_entries[] =
{
- { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
- { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
- { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
- { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
+ { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
+ { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
+ { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
{ 0 }
};
static const CGEN_IFLD i960_cgen_ifld_table[] =
{
- { I960_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
- { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_M3, "f-m3", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_M2, "f-m2", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_M1, "f-m1", 0, 32, 20, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_INDEX, "f-index", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { 0, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { 0 } } },
- { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
- { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { 0, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { 0 } } },
- { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
+ { I960_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_M3, "f-m3", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_M2, "f-m2", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_M1, "f-m1", 0, 32, 20, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_INDEX, "f-index", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
{ 0 }
};
{
/* pc: program counter */
{ "pc", & HW_ENT (HW_H_PC), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* src1: source register 1 */
{ "src1", & HW_ENT (HW_H_GR), 27, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* src2: source register 2 */
{ "src2", & HW_ENT (HW_H_GR), 13, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* dst: source/dest register */
{ "dst", & HW_ENT (HW_H_GR), 8, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* lit1: literal 1 */
{ "lit1", & HW_ENT (HW_H_UINT), 27, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* lit2: literal 2 */
{ "lit2", & HW_ENT (HW_H_UINT), 13, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* st_src: store src */
{ "st_src", & HW_ENT (HW_H_GR), 8, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* abase: abase */
{ "abase", & HW_ENT (HW_H_GR), 13, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* offset: offset */
{ "offset", & HW_ENT (HW_H_UINT), 20, 12,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* scale: scale */
{ "scale", & HW_ENT (HW_H_UINT), 22, 3,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* index: index */
{ "index", & HW_ENT (HW_H_GR), 27, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* optdisp: optional displacement */
{ "optdisp", & HW_ENT (HW_H_UINT), 0, 32,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* br_src1: branch src1 */
{ "br_src1", & HW_ENT (HW_H_GR), 8, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* br_src2: branch src2 */
{ "br_src2", & HW_ENT (HW_H_GR), 13, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* br_disp: branch displacement */
{ "br_disp", & HW_ENT (HW_H_IADDR), 19, 11,
- { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
/* br_lit1: branch literal 1 */
{ "br_lit1", & HW_ENT (HW_H_UINT), 8, 5,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* ctrl_disp: ctrl branch disp */
{ "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22,
- { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
};
/* Operand references. */
{ 0 }
};
-static const CGEN_OPERAND_INSTANCE fmt_flushreg_ops[] = {
- { INPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
- { 0 }
-};
-
#undef INPUT
#undef OUTPUT
#undef COND_REF
#define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
+static const CGEN_IFMT fmt_empty = {
+ 0, 0, 0x0, { 0 }
+};
+
static const CGEN_IFMT fmt_mulo = {
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
};
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x70000080 },
(PTR) & fmt_mulo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mulo $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x70000880 },
(PTR) & fmt_mulo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mulo $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x70001080 },
(PTR) & fmt_mulo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mulo $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x70001880 },
(PTR) & fmt_mulo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remo $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x70000400 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remo $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x70000c00 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remo $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x70001400 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remo $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x70001c00 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divo $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x70000580 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divo $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x70000d80 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divo $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x70001580 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divo $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x70001d80 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remi $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x74000400 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remi $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x74000c00 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remi $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x74001400 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* remi $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x74001c00 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divi $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x74000580 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divi $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x74000d80 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divi $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x74001580 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* divi $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x74001d80 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addo $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x59000000 },
(PTR) & fmt_mulo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addo $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x59000800 },
(PTR) & fmt_mulo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addo $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x59001000 },
(PTR) & fmt_mulo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* addo $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x59001800 },
(PTR) & fmt_mulo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subo $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000100 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subo $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000900 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subo $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001100 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* subo $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001900 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notbit $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000000 },
(PTR) & fmt_mulo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notbit $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000800 },
(PTR) & fmt_mulo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notbit $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001000 },
(PTR) & fmt_mulo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notbit $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001800 },
(PTR) & fmt_mulo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000080 },
(PTR) & fmt_mulo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000880 },
(PTR) & fmt_mulo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001080 },
(PTR) & fmt_mulo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* and $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001880 },
(PTR) & fmt_mulo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andnot $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x58000100 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andnot $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x58000900 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andnot $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x58001100 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* andnot $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x58001900 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* setbit $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000180 },
(PTR) & fmt_mulo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* setbit $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000980 },
(PTR) & fmt_mulo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* setbit $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001180 },
(PTR) & fmt_mulo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* setbit $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001980 },
(PTR) & fmt_mulo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notand $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x58000200 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notand $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x58000a00 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notand $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x58001200 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* notand $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x58001a00 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xor $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000300 },
(PTR) & fmt_mulo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xor $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000b00 },
(PTR) & fmt_mulo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xor $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001300 },
(PTR) & fmt_mulo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* xor $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001b00 },
(PTR) & fmt_mulo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000380 },
(PTR) & fmt_mulo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000b80 },
(PTR) & fmt_mulo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001380 },
(PTR) & fmt_mulo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* or $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001b80 },
(PTR) & fmt_mulo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* nor $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x58000400 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* nor $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x58000c00 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* nor $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x58001400 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* nor $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x58001c00 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* not $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_not, { 0x58000500 },
(PTR) & fmt_not_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* not $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_not1, { 0x58000d00 },
(PTR) & fmt_not1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* not $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_not2, { 0x58001500 },
(PTR) & fmt_not2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* not $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_not3, { 0x58001d00 },
(PTR) & fmt_not3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* clrbit $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo, { 0x58000600 },
(PTR) & fmt_mulo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* clrbit $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_mulo1, { 0x58000e00 },
(PTR) & fmt_mulo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* clrbit $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo2, { 0x58001600 },
(PTR) & fmt_mulo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* clrbit $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_mulo3, { 0x58001e00 },
(PTR) & fmt_mulo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shlo $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000600 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shlo $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000e00 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shlo $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001600 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shlo $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001e00 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shro $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000400 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shro $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000c00 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shro $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001400 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shro $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001c00 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shli $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000700 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shli $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000f00 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shli $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001700 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shli $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001f00 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shri $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo, { 0x59000580 },
(PTR) & fmt_remo_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shri $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_remo1, { 0x59000d80 },
(PTR) & fmt_remo1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shri $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo2, { 0x59001580 },
(PTR) & fmt_remo2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* shri $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_remo3, { 0x59001d80 },
(PTR) & fmt_remo3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* emul $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_emul, { 0x67000000 },
(PTR) & fmt_emul_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* emul $lit1, $src2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_emul1, { 0x67000800 },
(PTR) & fmt_emul1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* emul $src1, $lit2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_emul2, { 0x67001000 },
(PTR) & fmt_emul2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* emul $lit1, $lit2, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
& fmt_emul3, { 0x67001800 },
(PTR) & fmt_emul3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $src1, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
& fmt_not2, { 0x5c001600 },
(PTR) & fmt_not2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* mov $lit1, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
& fmt_not3, { 0x5c001e00 },
(PTR) & fmt_not3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movl $src1, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
& fmt_movl, { 0x5d001600 },
(PTR) & fmt_movl_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movl $lit1, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
& fmt_movl1, { 0x5d001e00 },
(PTR) & fmt_movl1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movt $src1, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
& fmt_movt, { 0x5e001600 },
(PTR) & fmt_movt_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movt $lit1, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
& fmt_movt1, { 0x5e001e00 },
(PTR) & fmt_movt1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movq $src1, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
& fmt_movq, { 0x5f001600 },
(PTR) & fmt_movq_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* movq $lit1, $dst */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
& fmt_movq1, { 0x5f001e00 },
(PTR) & fmt_movq1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* modpc $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_modpc, { 0x65000280 },
(PTR) & fmt_modpc_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* modac $src1, $src2, $dst */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
& fmt_modpc, { 0x64000280 },
(PTR) & fmt_modpc_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_lda_offset, { 0x8c000000 },
(PTR) & fmt_lda_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect_offset, { 0x8c002000 },
(PTR) & fmt_lda_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect, { 0x8c001000 },
(PTR) & fmt_lda_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect_index, { 0x8c001c00 },
(PTR) & fmt_lda_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_lda_disp, { 0x8c003000 },
(PTR) & fmt_lda_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect_disp, { 0x8c003400 },
(PTR) & fmt_lda_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_lda_index_disp, { 0x8c003800 },
(PTR) & fmt_lda_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* lda $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_lda_indirect_index_disp, { 0x8c003c00 },
(PTR) & fmt_lda_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ld_offset, { 0x90000000 },
(PTR) & fmt_ld_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect_offset, { 0x90002000 },
(PTR) & fmt_ld_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect, { 0x90001000 },
(PTR) & fmt_ld_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect_index, { 0x90001c00 },
(PTR) & fmt_ld_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ld_disp, { 0x90003000 },
(PTR) & fmt_ld_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect_disp, { 0x90003400 },
(PTR) & fmt_ld_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ld_index_disp, { 0x90003800 },
(PTR) & fmt_ld_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ld $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ld_indirect_index_disp, { 0x90003c00 },
(PTR) & fmt_ld_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldob_offset, { 0x80000000 },
(PTR) & fmt_ldob_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect_offset, { 0x80002000 },
(PTR) & fmt_ldob_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect, { 0x80001000 },
(PTR) & fmt_ldob_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect_index, { 0x80001c00 },
(PTR) & fmt_ldob_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldob_disp, { 0x80003000 },
(PTR) & fmt_ldob_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect_disp, { 0x80003400 },
(PTR) & fmt_ldob_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldob_index_disp, { 0x80003800 },
(PTR) & fmt_ldob_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldob $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldob_indirect_index_disp, { 0x80003c00 },
(PTR) & fmt_ldob_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldos_offset, { 0x88000000 },
(PTR) & fmt_ldos_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect_offset, { 0x88002000 },
(PTR) & fmt_ldos_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect, { 0x88001000 },
(PTR) & fmt_ldos_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect_index, { 0x88001c00 },
(PTR) & fmt_ldos_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldos_disp, { 0x88003000 },
(PTR) & fmt_ldos_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect_disp, { 0x88003400 },
(PTR) & fmt_ldos_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldos_index_disp, { 0x88003800 },
(PTR) & fmt_ldos_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldos $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldos_indirect_index_disp, { 0x88003c00 },
(PTR) & fmt_ldos_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldib_offset, { 0xc0000000 },
(PTR) & fmt_ldib_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect_offset, { 0xc0002000 },
(PTR) & fmt_ldib_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect, { 0xc0001000 },
(PTR) & fmt_ldib_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect_index, { 0xc0001c00 },
(PTR) & fmt_ldib_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldib_disp, { 0xc0003000 },
(PTR) & fmt_ldib_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect_disp, { 0xc0003400 },
(PTR) & fmt_ldib_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldib_index_disp, { 0xc0003800 },
(PTR) & fmt_ldib_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldib $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldib_indirect_index_disp, { 0xc0003c00 },
(PTR) & fmt_ldib_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldis_offset, { 0xc8000000 },
(PTR) & fmt_ldis_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect_offset, { 0xc8002000 },
(PTR) & fmt_ldis_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect, { 0xc8001000 },
(PTR) & fmt_ldis_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect_index, { 0xc8001c00 },
(PTR) & fmt_ldis_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldis_disp, { 0xc8003000 },
(PTR) & fmt_ldis_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect_disp, { 0xc8003400 },
(PTR) & fmt_ldis_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldis_index_disp, { 0xc8003800 },
(PTR) & fmt_ldis_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldis $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldis_indirect_index_disp, { 0xc8003c00 },
(PTR) & fmt_ldis_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldl_offset, { 0x98000000 },
(PTR) & fmt_ldl_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect_offset, { 0x98002000 },
(PTR) & fmt_ldl_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect, { 0x98001000 },
(PTR) & fmt_ldl_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect_index, { 0x98001c00 },
(PTR) & fmt_ldl_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldl_disp, { 0x98003000 },
(PTR) & fmt_ldl_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect_disp, { 0x98003400 },
(PTR) & fmt_ldl_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldl_index_disp, { 0x98003800 },
(PTR) & fmt_ldl_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldl $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldl_indirect_index_disp, { 0x98003c00 },
(PTR) & fmt_ldl_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldt_offset, { 0xa0000000 },
(PTR) & fmt_ldt_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect_offset, { 0xa0002000 },
(PTR) & fmt_ldt_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect, { 0xa0001000 },
(PTR) & fmt_ldt_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect_index, { 0xa0001c00 },
(PTR) & fmt_ldt_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldt_disp, { 0xa0003000 },
(PTR) & fmt_ldt_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect_disp, { 0xa0003400 },
(PTR) & fmt_ldt_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldt_index_disp, { 0xa0003800 },
(PTR) & fmt_ldt_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldt $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldt_indirect_index_disp, { 0xa0003c00 },
(PTR) & fmt_ldt_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $offset, $dst */
{
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
& fmt_ldq_offset, { 0xb0000000 },
(PTR) & fmt_ldq_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $offset($abase), $dst */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect_offset, { 0xb0002000 },
(PTR) & fmt_ldq_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq ($abase), $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect, { 0xb0001000 },
(PTR) & fmt_ldq_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq ($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect_index, { 0xb0001c00 },
(PTR) & fmt_ldq_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp, $dst */
{
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
& fmt_ldq_disp, { 0xb0003000 },
(PTR) & fmt_ldq_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp($abase), $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect_disp, { 0xb0003400 },
(PTR) & fmt_ldq_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldq_index_disp, { 0xb0003800 },
(PTR) & fmt_ldq_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* ldq $optdisp($abase)[$index*S$scale], $dst */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
& fmt_ldq_indirect_index_disp, { 0xb0003c00 },
(PTR) & fmt_ldq_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $offset */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_st_offset, { 0x92000000 },
(PTR) & fmt_st_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $offset($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_st_indirect_offset, { 0x92002000 },
(PTR) & fmt_st_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, ($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_st_indirect, { 0x92001000 },
(PTR) & fmt_st_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, ($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_st_indirect_index, { 0x92001c00 },
(PTR) & fmt_st_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_st_disp, { 0x92003000 },
(PTR) & fmt_st_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_st_indirect_disp, { 0x92003400 },
(PTR) & fmt_st_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp[$index*S$scale */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_st_index_disp, { 0x92003800 },
(PTR) & fmt_st_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* st $st_src, $optdisp($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_st_indirect_index_disp, { 0x92003c00 },
(PTR) & fmt_st_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $offset */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stob_offset, { 0x82000000 },
(PTR) & fmt_stob_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $offset($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stob_indirect_offset, { 0x82002000 },
(PTR) & fmt_stob_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, ($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stob_indirect, { 0x82001000 },
(PTR) & fmt_stob_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, ($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stob_indirect_index, { 0x82001c00 },
(PTR) & fmt_stob_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stob_disp, { 0x82003000 },
(PTR) & fmt_stob_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stob_indirect_disp, { 0x82003400 },
(PTR) & fmt_stob_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp[$index*S$scale */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stob_index_disp, { 0x82003800 },
(PTR) & fmt_stob_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stob $st_src, $optdisp($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stob_indirect_index_disp, { 0x82003c00 },
(PTR) & fmt_stob_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $offset */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stos_offset, { 0x8a000000 },
(PTR) & fmt_stos_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $offset($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stos_indirect_offset, { 0x8a002000 },
(PTR) & fmt_stos_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, ($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stos_indirect, { 0x8a001000 },
(PTR) & fmt_stos_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, ($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stos_indirect_index, { 0x8a001c00 },
(PTR) & fmt_stos_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stos_disp, { 0x8a003000 },
(PTR) & fmt_stos_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stos_indirect_disp, { 0x8a003400 },
(PTR) & fmt_stos_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp[$index*S$scale */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stos_index_disp, { 0x8a003800 },
(PTR) & fmt_stos_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stos $st_src, $optdisp($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stos_indirect_index_disp, { 0x8a003c00 },
(PTR) & fmt_stos_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $offset */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stl_offset, { 0x9a000000 },
(PTR) & fmt_stl_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $offset($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stl_indirect_offset, { 0x9a002000 },
(PTR) & fmt_stl_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, ($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stl_indirect, { 0x9a001000 },
(PTR) & fmt_stl_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, ($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stl_indirect_index, { 0x9a001c00 },
(PTR) & fmt_stl_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stl_disp, { 0x9a003000 },
(PTR) & fmt_stl_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stl_indirect_disp, { 0x9a003400 },
(PTR) & fmt_stl_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp[$index*S$scale */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stl_index_disp, { 0x9a003800 },
(PTR) & fmt_stl_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stl $st_src, $optdisp($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stl_indirect_index_disp, { 0x9a003c00 },
(PTR) & fmt_stl_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $offset */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stt_offset, { 0xa2000000 },
(PTR) & fmt_stt_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $offset($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stt_indirect_offset, { 0xa2002000 },
(PTR) & fmt_stt_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, ($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stt_indirect, { 0xa2001000 },
(PTR) & fmt_stt_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, ($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stt_indirect_index, { 0xa2001c00 },
(PTR) & fmt_stt_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stt_disp, { 0xa2003000 },
(PTR) & fmt_stt_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stt_indirect_disp, { 0xa2003400 },
(PTR) & fmt_stt_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp[$index*S$scale */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stt_index_disp, { 0xa2003800 },
(PTR) & fmt_stt_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stt $st_src, $optdisp($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stt_indirect_index_disp, { 0xa2003c00 },
(PTR) & fmt_stt_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $offset */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
& fmt_stq_offset, { 0xb2000000 },
(PTR) & fmt_stq_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $offset($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_stq_indirect_offset, { 0xb2002000 },
(PTR) & fmt_stq_indirect_offset_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, ($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
& fmt_stq_indirect, { 0xb2001000 },
(PTR) & fmt_stq_indirect_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, ($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stq_indirect_index, { 0xb2001c00 },
(PTR) & fmt_stq_indirect_index_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
& fmt_stq_disp, { 0xb2003000 },
(PTR) & fmt_stq_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp($abase) */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_stq_indirect_disp, { 0xb2003400 },
(PTR) & fmt_stq_indirect_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp[$index*S$scale */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
& fmt_stq_index_disp, { 0xb2003800 },
(PTR) & fmt_stq_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* stq $st_src, $optdisp($abase)[$index*S$scale] */
{
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_stq_indirect_index_disp, { 0xb2003c00 },
(PTR) & fmt_stq_indirect_index_disp_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpobe $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x32000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobe $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x32002000 },
(PTR) & fmt_cmpobe_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobne $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x35000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobne $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x35002000 },
(PTR) & fmt_cmpobe_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobl $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_reg, { 0x34000000 },
(PTR) & fmt_cmpobl_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobl $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_lit, { 0x34002000 },
(PTR) & fmt_cmpobl_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpoble $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_reg, { 0x36000000 },
(PTR) & fmt_cmpobl_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpoble $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_lit, { 0x36002000 },
(PTR) & fmt_cmpobl_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobg $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_reg, { 0x31000000 },
(PTR) & fmt_cmpobl_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobg $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_lit, { 0x31002000 },
(PTR) & fmt_cmpobl_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobge $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_reg, { 0x33000000 },
(PTR) & fmt_cmpobl_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpobge $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobl_lit, { 0x33002000 },
(PTR) & fmt_cmpobl_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibe $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3a000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibe $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3a002000 },
(PTR) & fmt_cmpobe_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibne $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3d000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibne $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3d002000 },
(PTR) & fmt_cmpobe_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibl $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3c000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibl $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3c002000 },
(PTR) & fmt_cmpobe_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpible $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3e000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpible $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3e002000 },
(PTR) & fmt_cmpobe_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibg $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x39000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibg $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x39002000 },
(PTR) & fmt_cmpobe_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibge $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x3b000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpibge $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_lit, { 0x3b002000 },
(PTR) & fmt_cmpobe_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbc $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x30000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbc $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_bbc_lit, { 0x30002000 },
(PTR) & fmt_bbc_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbs $br_src1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_cmpobe_reg, { 0x37000000 },
(PTR) & fmt_cmpobe_reg_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bbs $br_lit1, $br_src2, $br_disp */
{
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
& fmt_bbc_lit, { 0x37002000 },
(PTR) & fmt_bbc_lit_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* cmpi $src1, $src2 */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
& fmt_cmpi, { 0x5a002080 },
(PTR) & fmt_cmpi_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpi $lit1, $src2 */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
& fmt_cmpi1, { 0x5a002880 },
(PTR) & fmt_cmpi1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpi $src1, $lit2 */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
& fmt_cmpi2, { 0x5a003080 },
(PTR) & fmt_cmpi2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpi $lit1, $lit2 */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
& fmt_cmpi3, { 0x5a003880 },
(PTR) & fmt_cmpi3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpo $src1, $src2 */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
& fmt_cmpi, { 0x5a002000 },
(PTR) & fmt_cmpi_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpo $lit1, $src2 */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
& fmt_cmpi1, { 0x5a002800 },
(PTR) & fmt_cmpi1_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpo $src1, $lit2 */
{
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
& fmt_cmpi2, { 0x5a003000 },
(PTR) & fmt_cmpi2_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* cmpo $lit1, $lit2 */
{
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
& fmt_cmpi3, { 0x5a003800 },
(PTR) & fmt_cmpi3_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testno $br_src1 */
{
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x20000000 },
(PTR) & fmt_testno_reg_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testg $br_src1 */
{
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x21000000 },
(PTR) & fmt_testno_reg_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* teste $br_src1 */
{
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x22000000 },
(PTR) & fmt_testno_reg_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testge $br_src1 */
{
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x23000000 },
(PTR) & fmt_testno_reg_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testl $br_src1 */
{
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x24000000 },
(PTR) & fmt_testno_reg_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testne $br_src1 */
{
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x25000000 },
(PTR) & fmt_testno_reg_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testle $br_src1 */
{
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x26000000 },
(PTR) & fmt_testno_reg_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* testo $br_src1 */
{
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
& fmt_testno_reg, { 0x27000000 },
(PTR) & fmt_testno_reg_ops[0],
- { 0, 0, { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
/* bno $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x10000000 },
(PTR) & fmt_bno_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bg $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x11000000 },
(PTR) & fmt_bno_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* be $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x12000000 },
(PTR) & fmt_bno_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bge $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x13000000 },
(PTR) & fmt_bno_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bl $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x14000000 },
(PTR) & fmt_bno_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bne $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x15000000 },
(PTR) & fmt_bno_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* ble $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x16000000 },
(PTR) & fmt_bno_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* bo $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_bno, { 0x17000000 },
(PTR) & fmt_bno_ops[0],
- { 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
},
/* b $ctrl_disp */
{
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
& fmt_b, { 0x8000000 },
(PTR) & fmt_b_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $offset($abase) */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_bx_indirect_offset, { 0x84002000 },
(PTR) & fmt_bx_indirect_offset_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx ($abase) */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
& fmt_bx_indirect, { 0x84001000 },
(PTR) & fmt_bx_indirect_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx ($abase)[$index*S$scale] */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
& fmt_bx_indirect_index, { 0x84001c00 },
(PTR) & fmt_bx_indirect_index_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $optdisp */
{
{ { MNEM, ' ', OP (OPTDISP), 0 } },
& fmt_bx_disp, { 0x84003000 },
(PTR) & fmt_bx_disp_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* bx $optdisp($abase) */
{
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
& fmt_bx_indirect_disp, { 0x84003400 },
(PTR) & fmt_bx_indirect_disp_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx $optdisp */
{
{ { MNEM, ' ', OP (OPTDISP), 0 } },
& fmt_callx_disp, { 0x86003000 },
(PTR) & fmt_callx_disp_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx ($abase) */
{
{ { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
& fmt_callx_indirect, { 0x86001000 },
(PTR) & fmt_callx_indirect_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* callx $offset($abase) */
{
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
& fmt_callx_indirect_offset, { 0x86002000 },
(PTR) & fmt_callx_indirect_offset_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* ret */
{
{ { MNEM, 0 } },
& fmt_ret, { 0xa000000 },
(PTR) & fmt_ret_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* calls $src1 */
{
{ { MNEM, ' ', OP (SRC1), 0 } },
& fmt_calls, { 0x66003000 },
(PTR) & fmt_calls_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* fmark */
{
{ { MNEM, 0 } },
& fmt_fmark, { 0x66003e00 },
(PTR) & fmt_fmark_ops[0],
- { 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
+ { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
},
/* flushreg */
{
I960_INSN_FLUSHREG, "flushreg", "flushreg",
{ { MNEM, 0 } },
& fmt_flushreg, { 0x66003e80 },
- (PTR) & fmt_flushreg_ops[0],
- { 0, 0, { 0 } }
+ (PTR) 0,
+ { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
},
};
H_CC_CC
} H_CC;
-/* Enum declaration for i960 operand types. */
-typedef enum cgen_operand_type {
- I960_OPERAND_PC, I960_OPERAND_SRC1, I960_OPERAND_SRC2, I960_OPERAND_DST
- , I960_OPERAND_LIT1, I960_OPERAND_LIT2, I960_OPERAND_ST_SRC, I960_OPERAND_ABASE
- , I960_OPERAND_OFFSET, I960_OPERAND_SCALE, I960_OPERAND_INDEX, I960_OPERAND_OPTDISP
- , I960_OPERAND_BR_SRC1, I960_OPERAND_BR_SRC2, I960_OPERAND_BR_DISP, I960_OPERAND_BR_LIT1
- , I960_OPERAND_CTRL_DISP, I960_OPERAND_MAX
-} CGEN_OPERAND_TYPE;
-
-/* Non-boolean attributes. */
+/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
/* Number of architecture variants. */
#define MAX_MACHS ((int) MACH_MAX)
-/* Number of operands types. */
-#define MAX_OPERANDS ((int) I960_OPERAND_MAX)
-
-/* Maximum number of operands referenced by any insn. */
-#define MAX_OPERAND_INSTANCES 54
-
-/* Hardware, operand and instruction attribute indices. */
-
-/* Enum declaration for cgen_hw attrs. */
-typedef enum cgen_hw_attr {
- CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
-} CGEN_HW_ATTR;
-
-/* Number of non-boolean elements in cgen_hw. */
-#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_CACHE_ADDR)
-
-/* Hardware, operand and instruction attribute indices. */
+/* Ifield attribute indices. */
/* Enum declaration for cgen_ifld attrs. */
typedef enum cgen_ifld_attr {
- CGEN_IFLD_ABS_ADDR, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_RELOC, CGEN_IFLD_RESERVED
- , CGEN_IFLD_UNSIGNED, CGEN_IFLD_VIRTUAL
+ CGEN_IFLD_MACH, CGEN_IFLD_VIRTUAL, CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR
+ , CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT
} CGEN_IFLD_ATTR;
/* Number of non-boolean elements in cgen_ifld. */
-#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_ABS_ADDR)
+#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_VIRTUAL)
/* Enum declaration for i960 ifield types. */
typedef enum ifield_type {
#define MAX_IFLD ((int) I960_F_MAX)
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_MACH, CGEN_HW_VIRTUAL, CGEN_HW_UNSIGNED, CGEN_HW_SIGNED
+ , CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw. */
+#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_VIRTUAL)
+
+/* Enum declaration for i960 hardware types. */
+typedef enum hw_type {
+ HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
+ , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC
+ , HW_MAX
+} HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
- CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX
- , CGEN_OPERAND_RELOC, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED
+ CGEN_OPERAND_MACH, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR
+ , CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX
+ , CGEN_OPERAND_SEM_ONLY
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand. */
-#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
+#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_VIRTUAL)
+
+/* Enum declaration for i960 operand types. */
+typedef enum cgen_operand_type {
+ I960_OPERAND_PC, I960_OPERAND_SRC1, I960_OPERAND_SRC2, I960_OPERAND_DST
+ , I960_OPERAND_LIT1, I960_OPERAND_LIT2, I960_OPERAND_ST_SRC, I960_OPERAND_ABASE
+ , I960_OPERAND_OFFSET, I960_OPERAND_SCALE, I960_OPERAND_INDEX, I960_OPERAND_OPTDISP
+ , I960_OPERAND_BR_SRC1, I960_OPERAND_BR_SRC2, I960_OPERAND_BR_DISP, I960_OPERAND_BR_LIT1
+ , I960_OPERAND_CTRL_DISP, I960_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS ((int) I960_OPERAND_MAX)
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 54
+
+/* Insn attribute indices. */
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
- CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_NO_DIS
- , CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SKIP_CTI, CGEN_INSN_UNCOND_CTI
- , CGEN_INSN_VIRTUAL
+ CGEN_INSN_MACH, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_ALIAS, CGEN_INSN_NO_DIS, CGEN_INSN_PBB
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn. */
-#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
+#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_VIRTUAL)
/* Enum declaration for i960 instruction types. */
typedef enum cgen_insn_type {
extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
-/* Enum declaration for i960 hardware types. */
-typedef enum hw_type {
- HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
- , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC
- , HW_MAX
-} HW_TYPE;
-
-#define MAX_HW ((int) HW_MAX)
-
/* Hardware decls. */
extern CGEN_KEYWORD i960_cgen_opval_h_gr;
#define INLINE
#endif
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
static const char * insert_normal
- PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, int, int, int,
- CGEN_INSN_BYTES_PTR));
+ PARAMS ((CGEN_OPCODE_DESC, long, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR));
static const char * parse_insn_normal
PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *,
const char **, CGEN_FIELDS *));
bfd_vma pc;
{
const char * errmsg;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
switch (opindex)
{
case M32R_OPERAND_SR :
- errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_DR :
- errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_SRC1 :
- errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_SRC2 :
- errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_SCR :
- errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_DCR :
- errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_SIMM8 :
- errmsg = insert_normal (od, fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 32, total_length, buffer);
break;
case M32R_OPERAND_SIMM16 :
- errmsg = insert_normal (od, fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 16, 16, 32, total_length, buffer);
break;
case M32R_OPERAND_UIMM4 :
- errmsg = insert_normal (od, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_UIMM5 :
- errmsg = insert_normal (od, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 11, 5, 32, total_length, buffer);
break;
case M32R_OPERAND_UIMM16 :
- errmsg = insert_normal (od, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, buffer);
break;
/* start-sanitize-m32rx */
case M32R_OPERAND_IMM1 :
{
long value = fields->f_imm1;
value = ((value) - (1));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 15, 1, 32, total_length, buffer);
}
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACCD :
- errmsg = insert_normal (od, fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 2, 32, total_length, buffer);
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACCS :
- errmsg = insert_normal (od, fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 2, 32, total_length, buffer);
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACC :
- errmsg = insert_normal (od, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 1, 32, total_length, buffer);
break;
/* end-sanitize-m32rx */
case M32R_OPERAND_HASH :
- errmsg = insert_normal (od, fields->f_nil, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer);
break;
case M32R_OPERAND_HI16 :
- errmsg = insert_normal (od, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, buffer);
break;
case M32R_OPERAND_SLO16 :
- errmsg = insert_normal (od, fields->f_simm16, 0, 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_simm16, 0, 0, 16, 16, 32, total_length, buffer);
break;
case M32R_OPERAND_ULO16 :
- errmsg = insert_normal (od, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, buffer);
break;
case M32R_OPERAND_UIMM24 :
- errmsg = insert_normal (od, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 24, 32, total_length, buffer);
break;
case M32R_OPERAND_DISP8 :
{
long value = fields->f_disp8;
value = ((int) (((value) - (((pc) & (-4))))) >> (2));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
}
break;
case M32R_OPERAND_DISP16 :
{
long value = fields->f_disp16;
value = ((int) (((value) - (pc))) >> (2));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
}
break;
case M32R_OPERAND_DISP24 :
{
long value = fields->f_disp24;
value = ((int) (((value) - (pc))) >> (2));
- errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, CGEN_FIELDS_BITSIZE (fields), buffer);
+ errmsg = insert_normal (od, value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
}
break;
/* ??? This may need reworking as these cases don't necessarily
want the first byte and the last two bytes handled like this. */
if (big_p)
- x = (bfd_getb8 (bufp) << 16) | bfd_getb16 (bufp + 1);
+ x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
else
- x = bfd_getl16 (bufp) | (bfd_getb8 (bufp + 2) << 16);
+ x = bfd_getl16 (bufp) | (bufp[2] << 16);
break;
case 32:
if (big_p)
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
if (CGEN_INSN_LSB0_P)
- shift = start;
+ shift = (start + 1) - length;
else
shift = (word_length - (start + length));
x = (x & ~(mask << shift)) | ((value & mask) << shift);
want the first byte and the last two bytes handled like this. */
if (big_p)
{
- bfd_putb8 (x >> 16, bufp);
+ bufp[0] = x >> 16;
bfd_putb16 (x, bufp + 1);
}
else
{
bfd_putl16 (x, bufp);
- bfd_putb8 (x >> 16, bufp + 2);
+ bufp[2] = x >> 16;
}
break;
case 32:
/* Default insertion routine.
ATTRS is a mask of the boolean attributes.
- START is the starting bit number, architecture origin.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
LENGTH is the length of VALUE in bits.
- TOTAL_LENGTH is the total length of the insn.
+ TOTAL_LENGTH is the total length of the insn in bits.
The result is an error message or NULL if success. */
-/* ??? May need to know word length in order to properly place values as
- an insn may be made of multiple words and the current bit number handling
- may be insufficient. Word length is an architectural attribute and thus
- methinks the way to go [if needed] is to fetch this value from OD or
- define a macro in <arch>-opc.h rather than adding an extra argument -
- after all that's how endianness is handled. */
/* ??? This duplicates functionality with bfd's howto table and
bfd_install_relocation. */
-/* ??? For architectures where insns can be representable as ints,
- store insn in `field' struct and add registers, etc. while parsing? */
/* ??? This doesn't handle bfd_vma's. Create another function when
necessary. */
static const char *
-insert_normal (od, value, attrs, start, length, total_length, buffer)
+insert_normal (od, value, attrs, word_offset, start, length, word_length,
+ total_length, buffer)
CGEN_OPCODE_DESC od;
long value;
unsigned int attrs;
- int start;
- int length;
- int total_length;
+ unsigned int word_offset, start, length, word_length, total_length;
CGEN_INSN_BYTES_PTR buffer;
{
static char errbuf[100];
if (length == 0)
return NULL;
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
+
+ if (word_length > 32)
+ abort ();
+
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+#endif
+
/* Ensure VALUE will fit. */
- if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0)
+ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
{
unsigned long maxval = mask;
if ((unsigned long) value > maxval)
#if CGEN_INT_INSN_P
- if (total_length > 32)
- abort ();
{
int shift;
if (CGEN_INSN_LSB0_P)
- shift = start;
+ shift = (start + 1) - length;
else
- shift = total_length - (start + length);
+ shift = word_length - (start + length);
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
}
-#else
-
- /* FIXME: unfinished and untested */
-
-/* ??? To be defined in <arch>-opc.h as necessary. */
-#ifndef CGEN_WORD_ENDIAN
-#define CGEN_WORD_ENDIAN(od) CGEN_OPCODE_ENDIAN (od)
-#endif
-#ifndef CGEN_INSN_WORD_ENDIAN
-#define CGEN_INSN_WORD_ENDIAN(od) CGEN_WORD_ENDIAN (od)
-#endif
-
- /* The hard case is probably too slow for the normal cases.
- It's certainly more difficult to understand than the normal case.
- Thus this is split into two. Keep it that way. The hard case is defined
- to be when a field straddles a (loosely defined) word boundary
- (??? which may require target specific help to determine). */
-
-#if 0 /*wip*/
-
-#define HARD_CASE_P 0 /* FIXME:wip */
-
- if (HARD_CASE_P)
- {
- unsigned char *bufp = (unsigned char *) buffer;
- int insn_length_left = total_length;
-
- if (CGEN_INSN_LSB0_P)
- {
- int word_offset = (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG
- ? ...
- : start / CGEN_BASE_INSN_BITSIZE);
- bufp += word_offset * (CGEN_BASE_INSN_BITSIZE / 8);
- if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
- else
- start -= word_offset * CGEN_BASE_INSN_BITSIZE;
- }
- else
- {
- int word_offset = (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG
- ? start / CGEN_BASE_INSN_BITSIZE
- : ...);
- bufp += word_offset * (CGEN_BASE_INSN_BITSIZE / 8);
- if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
- start -= word_offset * CGEN_BASE_INSN_BITSIZE;
- else
- }
-
- /* Loop so we handle a field straddling an insn word boundary
- (remember, "insn word boundary" is loosely defined here). */
-
- while (length > 0)
- {
- int this_pass_length = length;
- int this_pass_start = start;
- int this_pass_word_length = min (insn_length_left,
- (CGEN_BASE_INSN_BITSIZE == 8
- ? 32
- : CGEN_BASE_INSN_BITSIZE));
-
- insert_1 (od, value, attrs,
- this_pass_start, this_pass_length, this_pass_word_length,
- bufp);
-
- length -= this_pass_length;
- insn_length_left -= this_pass_word_length;
- if (???)
- {
- value >>= ???;
- start += ???;
- }
- else
- {
- value >>= ???;
- start += ???;
- }
- bufp += this_pass_word_length / 8;
- }
- }
- else
-#endif /* 0 */
- {
- unsigned char *bufp = (unsigned char *) buffer;
-
- if (length > 32)
- abort ();
-
- /* Adjust start,total_length,bufp to point to the pseudo-word that holds
- the value. For example in a 48 bit insn where the value to insert
- (say an immediate value) is the last 16 bits then word_length here
- would be 16. To handle a 24 bit insn with an 18 bit immediate,
- insert_1 handles 24 bits (using a combination of bfd_get8,16). */
-
- if (total_length > 32)
- {
- int needed_width = start % 8 + length;
- int fetch_length = (needed_width <= 8 ? 8
- : needed_width <= 16 ? 16
- : 32);
+#else /* ! CGEN_INT_INSN_P */
- if (CGEN_INSN_LSB0_P)
- {
- if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
- {
- abort (); /* wip */
- }
- else
- {
- int offset = start & ~7;
-
- bufp += offset / 8;
- start -= offset;
- total_length -= offset;
- }
- }
- else
- {
- if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
- {
- int offset = start & ~7;
-
- bufp += offset / 8;
- start -= offset;
- total_length -= offset;
- }
- else
- {
- abort (); /* wip */
- }
- }
- }
+ {
+ unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
- insert_1 (od, value, start, length, total_length, bufp);
- }
+ insert_1 (od, value, start, length, word_length, bufp);
+ }
#endif /* ! CGEN_INT_INSN_P */
const unsigned char * syn;
CGEN_INIT_INSERT (od);
- value = CGEN_INSN_VALUE (insn);
+ value = CGEN_INSN_BASE_VALUE (insn);
/* If we're recording insns as numbers (rather than a string of bytes),
target byte order handling is deferred until later. */
#else
- cgen_insn_put_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE,
+ cgen_put_insn_value (od, buffer, min (CGEN_BASE_INSN_BITSIZE,
CGEN_FIELDS_BITSIZE (fields)),
value);
#endif /* ! CGEN_INT_INSN_P */
- /* ??? Rather than scanning the syntax string again, we could store
- in `fields' a null terminated list of the fields that are present. */
+ /* ??? It would be better to scan the format's fields.
+ Still need to be able to insert a value based on the operand though;
+ e.g. storing a branch displacement that got resolved later.
+ Needs more thought first. */
for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn)
{
str = start;
- /* Record a default length for the insn. This will get set to the
- correct value while parsing. */
- /* FIXME: wip */
+ /* Allow parse/insert handlers to obtain length of insn. */
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
if (! CGEN_PARSE_FN (insn) (od, insn, & str, fields))
/* Default text to print if an instruction isn't recognized. */
#define UNKNOWN_INSN_MSG _("*unknown*")
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
static int extract_normal
- PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_BYTES,
- unsigned int, int, int, int, long *));
+ PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+ unsigned int, unsigned int, unsigned int, unsigned int,
+ unsigned int, unsigned int, bfd_vma, long *));
static void print_normal
PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int));
static void print_address
PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
static int extract_insn_normal
PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
- unsigned long, CGEN_FIELDS *, bfd_vma));
+ CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
static void print_insn_normal
PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
bfd_vma, int));
CGEN_OPCODE_DESC od;
int opindex;
CGEN_EXTRACT_INFO *ex_info;
- CGEN_INSN_BYTES insn_value;
+ CGEN_INSN_INT insn_value;
CGEN_FIELDS * fields;
bfd_vma pc;
{
int length;
+ unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
switch (opindex)
{
case M32R_OPERAND_SR :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2);
break;
case M32R_OPERAND_DR :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1);
break;
case M32R_OPERAND_SRC1 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1);
break;
case M32R_OPERAND_SRC2 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2);
break;
case M32R_OPERAND_SCR :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r2);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2);
break;
case M32R_OPERAND_DCR :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_r1);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1);
break;
case M32R_OPERAND_SIMM8 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 8, 8, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm8);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
break;
case M32R_OPERAND_SIMM16 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
break;
case M32R_OPERAND_UIMM4 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm4);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
break;
case M32R_OPERAND_UIMM5 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm5);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
break;
case M32R_OPERAND_UIMM16 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
break;
/* start-sanitize-m32rx */
case M32R_OPERAND_IMM1 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 15, 1, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 15, 1, 32, total_length, pc, & value);
value = ((value) + (1));
fields->f_imm1 = value;
}
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACCD :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_accd);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 2, 32, total_length, pc, & fields->f_accd);
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACCS :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, CGEN_FIELDS_BITSIZE (fields), & fields->f_accs);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 2, 32, total_length, pc, & fields->f_accs);
break;
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
case M32R_OPERAND_ACC :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, CGEN_FIELDS_BITSIZE (fields), & fields->f_acc);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 1, 32, total_length, pc, & fields->f_acc);
break;
/* end-sanitize-m32rx */
case M32R_OPERAND_HASH :
- length = extract_normal (od, ex_info, insn_value, 0, 0, 0, CGEN_FIELDS_BITSIZE (fields), & fields->f_nil);
+ length = extract_normal (od, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil);
break;
case M32R_OPERAND_HI16 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_hi16);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
break;
case M32R_OPERAND_SLO16 :
- length = extract_normal (od, ex_info, insn_value, 0, 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_simm16);
+ length = extract_normal (od, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
break;
case M32R_OPERAND_ULO16 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm16);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
break;
case M32R_OPERAND_UIMM24 :
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, CGEN_FIELDS_BITSIZE (fields), & fields->f_uimm24);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
break;
case M32R_OPERAND_DISP8 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
value = ((((value) << (2))) + (((pc) & (-4))));
fields->f_disp8 = value;
}
case M32R_OPERAND_DISP16 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
value = ((((value) << (2))) + (pc));
fields->f_disp16 = value;
}
case M32R_OPERAND_DISP24 :
{
long value;
- length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, CGEN_FIELDS_BITSIZE (fields), & value);
+ length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
value = ((((value) << (2))) + (pc));
fields->f_disp24 = value;
}
\f
#if ! CGEN_INT_INSN_P
+/* Subroutine of extract_normal.
+ Ensure sufficient bytes are cached in EX_INFO.
+ OFFSET is the offset in bytes from the start of the insn of the value.
+ BYTES is the length of the needed value.
+ Returns 1 for success, 0 for failure. */
+
+static INLINE int
+fill_cache (od, ex_info, offset, bytes, pc)
+ CGEN_OPCODE_DESC od;
+ CGEN_EXTRACT_INFO *ex_info;
+ int offset, bytes;
+ bfd_vma pc;
+{
+ /* It's doubtful that the middle part has already been fetched so
+ we don't optimize that case. kiss. */
+ int mask;
+ disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+ /* First do a quick check. */
+ mask = (1 << bytes) - 1;
+ if (((ex_info->valid >> offset) & mask) == mask)
+ return 1;
+
+ /* Search for the first byte we need to read. */
+ for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+ if (! (mask & ex_info->valid))
+ break;
+
+ if (bytes)
+ {
+ int status;
+
+ pc += offset;
+ status = (*info->read_memory_func)
+ (pc, ex_info->insn_bytes + offset, bytes, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return 0;
+ }
+
+ ex_info->valid |= ((1 << bytes) - 1) << offset;
+ }
+
+ return 1;
+}
+
/* Subroutine of extract_normal. */
static INLINE long
-extract_1 (od, ex_info, start, length, word_length, bufp)
+extract_1 (od, ex_info, start, length, word_length, bufp, pc)
CGEN_OPCODE_DESC od;
- CGEN_EXTRACT_INFO *info;
+ CGEN_EXTRACT_INFO *ex_info;
int start,length,word_length;
unsigned char *bufp;
+ bfd_vma pc;
{
unsigned long x,mask;
int shift;
int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG;
- /* FIXME: Need to use ex_info to ensure bytes have been fetched. */
-
switch (word_length)
{
case 8:
/* ??? This may need reworking as these cases don't necessarily
want the first byte and the last two bytes handled like this. */
if (big_p)
- x = (bfd_getb8 (bufp) << 16) | bfd_getb16 (bufp + 1);
+ x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
else
- x = bfd_getl16 (bufp) | (bfd_getb8 (bufp + 2) << 16);
+ x = bfd_getl16 (bufp) | (bufp[2] << 16);
break;
case 32:
if (big_p)
/* Written this way to avoid undefined behaviour. */
mask = (((1L << (length - 1)) - 1) << 1) | 1;
if (CGEN_INSN_LSB0_P)
- shift = start;
+ shift = (start + 1) - length;
else
shift = (word_length - (start + length));
return (x >> shift) & mask;
/* Default extraction routine.
- ATTRS is a mask of the boolean attributes. We only need `unsigned',
- but for generality we take a bitmask of all of them. */
+ INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order,
+ or sometimes less for cases like the m32r where the base insn size is 32
+ but some insns are 16 bits.
+ ATTRS is a mask of the boolean attributes. We only need `UNSIGNED',
+ but for generality we take a bitmask of all of them.
+ WORD_OFFSET is the offset in bits from the start of the insn of the value.
+ WORD_LENGTH is the length of the word in bits in which the value resides.
+ START is the starting bit number in the word, architecture origin.
+ LENGTH is the length of VALUE in bits.
+ TOTAL_LENGTH is the total length of the insn in bits.
+
+ Returns 1 for success, 0 for failure. */
+
+/* ??? The return code isn't properly used. wip. */
/* ??? This doesn't handle bfd_vma's. Create another function when
necessary. */
static int
-extract_normal (od, ex_info, insn_value, attrs, start, length, total_length, valuep)
+extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length,
+ word_length, total_length, pc, valuep)
CGEN_OPCODE_DESC od;
CGEN_EXTRACT_INFO *ex_info;
- CGEN_INSN_BYTES insn_value;
+ CGEN_INSN_INT insn_value;
unsigned int attrs;
- int start, length, total_length;
+ unsigned int word_offset, start, length, word_length, total_length;
+ bfd_vma pc;
long *valuep;
{
- unsigned long value;
+ CGEN_INSN_INT value;
/* If LENGTH is zero, this operand doesn't contribute to the value
so give it a standard value of zero. */
return 1;
}
-#if CGEN_INT_INSN_P
-
- {
- /* Written this way to avoid undefined behaviour. */
- unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
-
- if (CGEN_INSN_LSB0_P)
- value = insn_value >> start;
- else
- value = insn_value >> (total_length - (start + length));
- value &= mask;
- /* sign extend? */
- if (! (attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED))
- && (value & (1L << (length - 1))))
- value |= ~mask;
- }
-
-#else
+ if (CGEN_INT_INSN_P
+ && word_offset != 0)
+ abort ();
- /* The hard case is probably too slow for the normal cases.
- It's certainly more difficult to understand than the normal case.
- Thus this is split into two. Keep it that way. The hard case is defined
- to be when a field straddles a (loosely defined) word boundary
- (??? which may require target specific help to determine). */
+ if (word_length > 32)
+ abort ();
-#if 0 /*wip*/
+ /* For architectures with insns smaller than the insn-base-bitsize,
+ word_length may be too big. */
+#if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE
+ if (word_offset == 0
+ && word_length > total_length)
+ word_length = total_length;
+#endif
-#define HARD_CASE_P 0 /* FIXME:wip */
+ /* Does the value reside in INSN_VALUE? */
- if (HARD_CASE_P)
+ if (word_offset == 0)
{
+ /* Written this way to avoid undefined behaviour. */
+ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+ if (CGEN_INSN_LSB0_P)
+ value = insn_value >> ((start + 1) - length);
+ else
+ value = insn_value >> (word_length - (start + length));
+ value &= mask;
+ /* sign extend? */
+ if (! CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)
+ && (value & (1L << (length - 1))))
+ value |= ~mask;
}
-#endif
+
+#if ! CGEN_INT_INSN_P
+
else
{
- unsigned char *bufp = (unsigned char *) insn_value;
+ unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
- if (length > 32)
+ if (word_length > 32)
abort ();
- /* Adjust start,total_length,bufp to point to the pseudo-word that holds
- the value. For example in a 48 bit insn where the value to insert
- (say an immediate value) is the last 16 bits then word_length here
- would be 16. To handle a 24 bit insn with an 18 bit immediate,
- extract_1 handles 24 bits (using a combination of bfd_get8,16). */
-
- if (total_length > 32)
- {
- int needed_width = start % 8 + length;
- int fetch_length = (needed_width <= 8 ? 8
- : needed_width <= 16 ? 16
- : 32);
-
- if (CGEN_INSN_LSB0_P)
- {
- if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
- {
- abort (); /* wip */
- }
- else
- {
- int offset = start & ~7;
-
- bufp += offset / 8;
- start -= offset;
- total_length -= offset;
- }
- }
- else
- {
- if (CGEN_INSN_WORD_ENDIAN (od) == CGEN_ENDIAN_BIG)
- {
- int offset = start & ~7;
-
- bufp += offset / 8;
- start -= offset;
- total_length -= offset;
- }
- else
- {
- abort (); /* wip */
- }
- }
- }
+ if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+ return 0;
- /* FIXME: which bytes are being extracted have been lost. */
- value = extract_1 (od, ex_info, start, length, total_length, bufp);
+ value = extract_1 (od, ex_info, start, length, word_length, bufp, pc);
}
#endif /* ! CGEN_INT_INSN_P */
*valuep = value;
- /* FIXME: for now */
return 1;
}
CGEN_OPCODE_DESC od;
const CGEN_INSN *insn;
CGEN_EXTRACT_INFO *ex_info;
- unsigned long insn_value;
+ CGEN_INSN_INT insn_value;
CGEN_FIELDS *fields;
bfd_vma pc;
{
ex_info.dis_info = info;
ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1;
- ex_info.bytes = buf;
+ ex_info.insn_bytes = buf;
switch (buflen)
{
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the extract
handler. */
- if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ if ((insn_value & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
{
/* Printing is handled in two passes. The first pass parses the
machine insn and extracts the fields. The second pass prints
#include "m32r-opc.h"
#include "opintl.h"
+/* Used by the ifield rtx function. */
+#define FLD(f) (fields->f)
+
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
static unsigned int asm_hash_insn PARAMS ((const char *));
static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
-static unsigned int dis_hash_insn PARAMS ((const char *, unsigned long));
-
-/* Cover function to read and properly byteswap an insn value. */
-
-CGEN_INSN_INT
-cgen_get_insn_value (od, buf, length)
- CGEN_OPCODE_DESC od;
- unsigned char *buf;
- int length;
-{
- CGEN_INSN_INT value;
-
- switch (length)
- {
- case 8:
- value = *buf;
- break;
- case 16:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- value = bfd_getb16 (buf);
- else
- value = bfd_getl16 (buf);
- break;
- case 32:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- value = bfd_getb32 (buf);
- else
- value = bfd_getl32 (buf);
- break;
- default:
- abort ();
- }
-
- return value;
-}
-
-/* Cover function to store an insn value properly byteswapped. */
-
-void
-cgen_put_insn_value (od, buf, length, value)
- CGEN_OPCODE_DESC od;
- unsigned char *buf;
- int length;
- CGEN_INSN_INT value;
-{
- switch (length)
- {
- case 8:
- buf[0] = value;
- break;
- case 16:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- bfd_putb16 (value, buf);
- else
- bfd_putl16 (value, buf);
- break;
- case 32:
- if (CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG)
- bfd_putb32 (value, buf);
- else
- bfd_putl32 (value, buf);
- break;
- default:
- abort ();
- }
-}
+static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
/* Look up instruction INSN_VALUE and extract its fields.
INSN, if non-null, is the insn table entry.
If INSN != NULL, LENGTH must be valid.
ALIAS_P is non-zero if alias insns are to be included in the search.
- The result a pointer to the insn table entry, or NULL if the instruction
+ The result is a pointer to the insn table entry, or NULL if the instruction
wasn't recognized. */
const CGEN_INSN *
CGEN_FIELDS *fields;
int alias_p;
{
- unsigned char buf[16];
+ unsigned char buf[CGEN_MAX_INSN_SIZE];
unsigned char *bufp;
- unsigned int base_insn;
+ CGEN_INSN_INT base_insn;
#if CGEN_INT_INSN_P
CGEN_EXTRACT_INFO *info = NULL;
#else
CGEN_EXTRACT_INFO *info = &ex_info;
#endif
-#if ! CGEN_INT_INSN_P
+#if CGEN_INT_INSN_P
+ cgen_put_insn_value (od, buf, length, insn_value);
+ bufp = buf;
+ base_insn = insn_value; /*???*/
+#else
ex_info.dis_info = NULL;
- ex_info.bytes = insn_value;
+ ex_info.insn_bytes = insn_value;
ex_info.valid = -1;
+ base_insn = cgen_get_insn_value (od, buf, length);
+ bufp = insn_value;
#endif
if (!insn)
{
const CGEN_INSN_LIST *insn_list;
-#if CGEN_INT_INSN_P
- cgen_put_insn_value (od, buf, length, insn_value);
- bufp = buf;
- base_insn = insn_value; /*???*/
-#else
- base_insn = cgen_get_insn_value (od, buf, length);
- bufp = insn_value;
-#endif
-
/* The instructions are stored in hash lists.
Pick the first one and keep trying until we find the right one. */
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the
extract handler. */
- if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
+ if ((base_insn & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
{
/* ??? 0 is passed for `pc' */
int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
- insn_value, fields,
+ base_insn, fields,
(bfd_vma) 0);
if (elength > 0)
{
abort ();
/* ??? 0 is passed for `pc' */
- length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, insn_value, fields,
+ length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
(bfd_vma) 0);
/* Sanity check: must succeed.
Could relax this later if it ever proves useful. */
}
/* Attributes. */
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
static const CGEN_ATTR_ENTRY MACH_attr[] =
{
{ "base", MACH_BASE },
};
/* end-sanitize-m32rx */
+const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "RELOC", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
{
{ "MACH", & MACH_attr[0] },
- { "CACHE-ADDR", NULL },
- { "FUN-ACCESS", NULL },
- { "PC", NULL },
- { "PROFILE", NULL },
- { "SIGN-OPT", NULL },
- { "UNSIGNED", NULL },
- { 0, 0 }
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
};
const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
{
- { "ABS-ADDR", NULL },
- { "HASH-PREFIX", NULL },
- { "NEGATIVE", NULL },
- { "PCREL-ADDR", NULL },
- { "RELAX", NULL },
- { "RELOC", NULL },
- { "SEM-ONLY", NULL },
- { "SIGN-OPT", NULL },
- { "UNSIGNED", NULL },
- { 0, 0 }
+ { "MACH", & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { "RELOC", &bool_attr[0], &bool_attr[0] },
+ { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
};
const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
/* start-sanitize-m32rx */
{ "PIPE", & PIPE_attr[0] },
/* end-sanitize-m32rx */
- { "ALIAS", NULL },
- { "COND-CTI", NULL },
- { "FILL-SLOT", NULL },
- { "NO-DIS", NULL },
- { "RELAX", NULL },
- { "RELAXABLE", NULL },
- { "SKIP-CTI", NULL },
- { "SPECIAL", NULL },
- { "UNCOND-CTI", NULL },
- { "VIRTUAL", NULL },
- { 0, 0 }
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
+/* start-sanitize-m32rx */
+ { "SPECIAL", &bool_attr[0], &bool_attr[0] },
+/* end-sanitize-m32rx */
+ { 0, 0, 0 }
};
CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
{ HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
{ HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
{ HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
- { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_SIGN_OPT)|(1<<CGEN_HW_UNSIGNED), { (1<<MACH_BASE) } } },
+ { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
{ HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
{ HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
{ HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
{ 0 }
};
+/* The instruction field table. */
+
+static const CGEN_IFLD m32r_cgen_ifld_table[] =
+{
+ { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_COND, "f-cond", 0, 32, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_R1, "f-r1", 0, 32, 4, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_R2, "f-r2", 0, 32, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
+ { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_SIGN_OPT)|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+ { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } } },
+/* start-sanitize-m32rx */
+ { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } } },
+/* end-sanitize-m32rx */
+ { 0 }
+};
+
/* The operand table. */
#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
{
/* pc: program counter */
{ "pc", & HW_ENT (HW_H_PC), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* sr: source register */
{ "sr", & HW_ENT (HW_H_GR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* dr: destination register */
{ "dr", & HW_ENT (HW_H_GR), 4, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* src1: source register 1 */
{ "src1", & HW_ENT (HW_H_GR), 4, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* src2: source register 2 */
{ "src2", & HW_ENT (HW_H_GR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* scr: source control register */
{ "scr", & HW_ENT (HW_H_CR), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* dcr: destination control register */
{ "dcr", & HW_ENT (HW_H_CR), 4, 4,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* simm8: 8 bit signed immediate */
{ "simm8", & HW_ENT (HW_H_SINT), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
/* simm16: 16 bit signed immediate */
{ "simm16", & HW_ENT (HW_H_SINT), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm4: 4 bit trap number */
{ "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* uimm5: 5 bit shift count */
{ "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* start-sanitize-m32rx */
/* imm1: 1 bit immediate */
{ "imm1", & HW_ENT (HW_H_UINT), 15, 1,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* accd: accumulator destination register */
{ "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* accs: accumulator source register */
{ "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
/* acc: accumulator reg (d) */
{ "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* end-sanitize-m32rx */
/* hash: # prefix */
{ "hash", & HW_ENT (HW_H_SINT), 0, 0,
- { 0, 0, { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", & HW_ENT (HW_H_HI16), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
- { 0, 0, { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* uimm24: 24 bit address */
{ "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
- { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } } },
/* disp8: 8 bit displacement */
{ "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
- { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp16: 16 bit displacement */
{ "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
- { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp24: 24 bit displacement */
{ "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
- { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } } },
/* condbit: condition bit */
{ "condbit", & HW_ENT (HW_H_COND), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
/* accum: accumulator */
{ "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
- { 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
+ { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } } },
};
/* Operand references. */
#define INPUT CGEN_OPERAND_INSTANCE_INPUT
#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
+#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_and3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "uimm16", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_or3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "ulo16", & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_bc8_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+ { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+ { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+ { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+ { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+ { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
{ 0 }
};
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
+ { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
{ 0 }
};
/* end-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_bra8_ops[] = {
- { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_bra24_ops[] = {
- { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, COND_REF },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
{ 0 }
};
/* end-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_jl_ops[] = {
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
- { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+ { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
- { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+ { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
- { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+ { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
- { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ld24_ops[] = {
- { INPUT, "uimm24", & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "uimm24", & HW_ENT (HW_H_ADDR), CGEN_MODE_USI, & OP_ENT (UIMM24), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ldi8_ops[] = {
- { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "simm8", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = {
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0 },
- { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+ { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_machi_ops[] = {
- { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_machi_a_ops[] = {
- { INPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
+ { INPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_mulhi_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_mulhi_a_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "acc", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_mv_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_mvfachi_ops[] = {
- { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_mvfachi_a_ops[] = {
- { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_mvfc_ops[] = {
- { INPUT, "scr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "scr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_mvtachi_ops[] = {
- { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_mvtachi_a_ops[] = {
- { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
+ { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_mvtc_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "dcr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { OUTPUT, "dcr", & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = {
- { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
- { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
+ { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
+ { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = {
- { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
- { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
- { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
+ { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 },
+ { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0, 0 },
+ { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = {
- { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
- { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14 },
- { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
- { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
- { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
- { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
+ { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
+ { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
+ { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
+ { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+ { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
+ { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
+ { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = {
- { INPUT, "hi16", & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "hi16", & HW_ENT (HW_H_HI16), CGEN_MODE_SI, & OP_ENT (HI16), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = {
- { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
- { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
+ { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = {
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
+ { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = {
- { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
- { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
- { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
- { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
- { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0 },
- { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14 },
- { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6 },
- { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0 },
- { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0 },
- { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0 },
- { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0 },
+ { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
+ { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
+ { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
+ { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
+ { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0, 0 },
+ { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 },
+ { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 },
+ { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 },
+ { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 },
+ { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 },
+ { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
{ 0 }
};
static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = {
- { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
- { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, COND_REF },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, COND_REF },
+ { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF },
+ { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_satb_ops[] = {
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
- { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
- { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
+ { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, COND_REF },
+ { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = {
- { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
- { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
- { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
+ { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
+ { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 },
+ { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = {
- { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = {
- { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
- { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
- { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
+ { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
/* start-sanitize-m32rx */
static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = {
- { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0 },
+ { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 },
{ 0 }
};
/* end-sanitize-m32rx */
#undef INPUT
#undef OUTPUT
+#undef COND_REF
+
+/* Instruction formats. */
+
+#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
+
+static const CGEN_IFMT fmt_empty = {
+ 0, 0, 0x0, { 0 }
+};
+
+static const CGEN_IFMT fmt_add = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_add3 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_and3 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_or3 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_addi = {
+ 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
+};
+
+static const CGEN_IFMT fmt_addv = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_addv3 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_addx = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_bc8 = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT fmt_bc24 = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+static const CGEN_IFMT fmt_beq = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
+};
+
+static const CGEN_IFMT fmt_beqz = {
+ 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 }
+};
+
+static const CGEN_IFMT fmt_bl8 = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT fmt_bl24 = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_bcl8 = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_bcl24 = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_bra8 = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT fmt_bra24 = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+static const CGEN_IFMT fmt_cmp = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_cmpi = {
+ 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_cmpz = {
+ 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_div = {
+ 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_jc = {
+ 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_jl = {
+ 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_jmp = {
+ 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ld = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_d = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_ldb = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ldb_d = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_ldh = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ldh_d = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_plus = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ld24 = {
+ 32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 }
+};
+
+static const CGEN_IFMT fmt_ldi8 = {
+ 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
+};
+
+static const CGEN_IFMT fmt_ldi16 = {
+ 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_lock = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_machi = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_machi_a = {
+ 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_mulhi = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_mulhi_a = {
+ 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_mv = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_mvfachi = {
+ 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_mvfachi_a = {
+ 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_mvfc = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_mvtachi = {
+ 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_mvtachi_a = {
+ 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_mvtc = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_nop = {
+ 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_rac = {
+ 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_rac_dsi = {
+ 16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_rte = {
+ 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_seth = {
+ 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 }
+};
+
+static const CGEN_IFMT fmt_sll3 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_slli = {
+ 16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 }
+};
+
+static const CGEN_IFMT fmt_st = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_st_d = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_stb = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_stb_d = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_sth = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_sth_d = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_st_plus = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_trap = {
+ 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 }
+};
+
+static const CGEN_IFMT fmt_unlock = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_satb = {
+ 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_sat = {
+ 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_sadd = {
+ 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_macwu1 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_mulwu1 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_sc = {
+ 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+/* end-sanitize-m32rx */
+#undef F
#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
{ 1, 1, 1, 1 },
M32R_INSN_ADD, "add", "add",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0xa0,
+ & fmt_add, { 0xa0 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ADD3, "add3", "add3",
{ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
- { 32, 32, 0xf0f00000 }, 0x80a00000,
+ & fmt_add3, { 0x80a00000 },
(PTR) & fmt_add3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_AND, "and", "and",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0xc0,
+ & fmt_add, { 0xc0 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_AND3, "and3", "and3",
{ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
- { 32, 32, 0xf0f00000 }, 0x80c00000,
+ & fmt_and3, { 0x80c00000 },
(PTR) & fmt_and3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_OR, "or", "or",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0xe0,
+ & fmt_add, { 0xe0 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_OR3, "or3", "or3",
{ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
- { 32, 32, 0xf0f00000 }, 0x80e00000,
+ & fmt_or3, { 0x80e00000 },
(PTR) & fmt_or3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_XOR, "xor", "xor",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0xd0,
+ & fmt_add, { 0xd0 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_XOR3, "xor3", "xor3",
{ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
- { 32, 32, 0xf0f00000 }, 0x80d00000,
+ & fmt_and3, { 0x80d00000 },
(PTR) & fmt_and3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ADDI, "addi", "addi",
{ { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
- { 16, 16, 0xf000 }, 0x4000,
+ & fmt_addi, { 0x4000 },
(PTR) & fmt_addi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ADDV, "addv", "addv",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x80,
+ & fmt_addv, { 0x80 },
(PTR) & fmt_addv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ADDV3, "addv3", "addv3",
{ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
- { 32, 32, 0xf0f00000 }, 0x80800000,
+ & fmt_addv3, { 0x80800000 },
(PTR) & fmt_addv3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ADDX, "addx", "addx",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x90,
+ & fmt_addx, { 0x90 },
(PTR) & fmt_addx_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BC8, "bc8", "bc.s",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7c00,
+ & fmt_bc8, { 0x7c00 },
(PTR) & fmt_bc8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BC24, "bc24", "bc.l",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xfc000000,
+ & fmt_bc24, { 0xfc000000 },
(PTR) & fmt_bc24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BEQ, "beq", "beq",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
- { 32, 32, 0xf0f00000 }, 0xb0000000,
+ & fmt_beq, { 0xb0000000 },
(PTR) & fmt_beq_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BEQZ, "beqz", "beqz",
{ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
- { 32, 32, 0xfff00000 }, 0xb0800000,
+ & fmt_beqz, { 0xb0800000 },
(PTR) & fmt_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BGEZ, "bgez", "bgez",
{ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
- { 32, 32, 0xfff00000 }, 0xb0b00000,
+ & fmt_beqz, { 0xb0b00000 },
(PTR) & fmt_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BGTZ, "bgtz", "bgtz",
{ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
- { 32, 32, 0xfff00000 }, 0xb0d00000,
+ & fmt_beqz, { 0xb0d00000 },
(PTR) & fmt_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BLEZ, "blez", "blez",
{ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
- { 32, 32, 0xfff00000 }, 0xb0c00000,
+ & fmt_beqz, { 0xb0c00000 },
(PTR) & fmt_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BLTZ, "bltz", "bltz",
{ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
- { 32, 32, 0xfff00000 }, 0xb0a00000,
+ & fmt_beqz, { 0xb0a00000 },
(PTR) & fmt_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BNEZ, "bnez", "bnez",
{ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
- { 32, 32, 0xfff00000 }, 0xb0900000,
+ & fmt_beqz, { 0xb0900000 },
(PTR) & fmt_beqz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BL8, "bl8", "bl.s",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7e00,
+ & fmt_bl8, { 0x7e00 },
(PTR) & fmt_bl8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BL24, "bl24", "bl.l",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xfe000000,
+ & fmt_bl24, { 0xfe000000 },
(PTR) & fmt_bl24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BCL8, "bcl8", "bcl.s",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7800,
+ & fmt_bcl8, { 0x7800 },
(PTR) & fmt_bcl8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BCL24, "bcl24", "bcl.l",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xf8000000,
+ & fmt_bcl24, { 0xf8000000 },
(PTR) & fmt_bcl24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BNC8, "bnc8", "bnc.s",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7d00,
+ & fmt_bc8, { 0x7d00 },
(PTR) & fmt_bc8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BNC24, "bnc24", "bnc.l",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xfd000000,
+ & fmt_bc24, { 0xfd000000 },
(PTR) & fmt_bc24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BNE, "bne", "bne",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
- { 32, 32, 0xf0f00000 }, 0xb0100000,
+ & fmt_beq, { 0xb0100000 },
(PTR) & fmt_beq_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BRA8, "bra8", "bra.s",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7f00,
+ & fmt_bra8, { 0x7f00 },
(PTR) & fmt_bra8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BRA24, "bra24", "bra.l",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xff000000,
+ & fmt_bra24, { 0xff000000 },
(PTR) & fmt_bra24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BNCL8, "bncl8", "bncl.s",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7900,
+ & fmt_bcl8, { 0x7900 },
(PTR) & fmt_bcl8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_BNCL24, "bncl24", "bncl.l",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xf9000000,
+ & fmt_bcl24, { 0xf9000000 },
(PTR) & fmt_bcl24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_CMP, "cmp", "cmp",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x40,
+ & fmt_cmp, { 0x40 },
(PTR) & fmt_cmp_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_CMPI, "cmpi", "cmpi",
{ { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
- { 32, 32, 0xfff00000 }, 0x80400000,
+ & fmt_cmpi, { 0x80400000 },
(PTR) & fmt_cmpi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_CMPU, "cmpu", "cmpu",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x50,
+ & fmt_cmp, { 0x50 },
(PTR) & fmt_cmp_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_CMPUI, "cmpui", "cmpui",
{ { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
- { 32, 32, 0xfff00000 }, 0x80500000,
+ & fmt_cmpi, { 0x80500000 },
(PTR) & fmt_cmpi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_CMPEQ, "cmpeq", "cmpeq",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x60,
+ & fmt_cmp, { 0x60 },
(PTR) & fmt_cmp_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_CMPZ, "cmpz", "cmpz",
{ { MNEM, ' ', OP (SRC2), 0 } },
- { 16, 16, 0xfff0 }, 0x70,
+ & fmt_cmpz, { 0x70 },
(PTR) & fmt_cmpz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_DIV, "div", "div",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 32, 32, 0xf0f0ffff }, 0x90000000,
+ & fmt_div, { 0x90000000 },
(PTR) & fmt_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_DIVU, "divu", "divu",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 32, 32, 0xf0f0ffff }, 0x90100000,
+ & fmt_div, { 0x90100000 },
(PTR) & fmt_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_REM, "rem", "rem",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 32, 32, 0xf0f0ffff }, 0x90200000,
+ & fmt_div, { 0x90200000 },
(PTR) & fmt_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_REMU, "remu", "remu",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 32, 32, 0xf0f0ffff }, 0x90300000,
+ & fmt_div, { 0x90300000 },
(PTR) & fmt_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_DIVH, "divh", "divh",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 32, 32, 0xf0f0ffff }, 0x90000010,
+ & fmt_div, { 0x90000010 },
(PTR) & fmt_div_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_JC, "jc", "jc",
{ { MNEM, ' ', OP (SR), 0 } },
- { 16, 16, 0xfff0 }, 0x1cc0,
+ & fmt_jc, { 0x1cc0 },
(PTR) & fmt_jc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_JNC, "jnc", "jnc",
{ { MNEM, ' ', OP (SR), 0 } },
- { 16, 16, 0xfff0 }, 0x1dc0,
+ & fmt_jc, { 0x1dc0 },
(PTR) & fmt_jc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_JL, "jl", "jl",
{ { MNEM, ' ', OP (SR), 0 } },
- { 16, 16, 0xfff0 }, 0x1ec0,
+ & fmt_jl, { 0x1ec0 },
(PTR) & fmt_jl_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_JMP, "jmp", "jmp",
{ { MNEM, ' ', OP (SR), 0 } },
- { 16, 16, 0xfff0 }, 0x1fc0,
+ & fmt_jmp, { 0x1fc0 },
(PTR) & fmt_jmp_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LD, "ld", "ld",
{ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x20c0,
+ & fmt_ld, { 0x20c0 },
(PTR) & fmt_ld_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LD_D, "ld-d", "ld",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0c00000,
+ & fmt_ld_d, { 0xa0c00000 },
(PTR) & fmt_ld_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDB, "ldb", "ldb",
{ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x2080,
+ & fmt_ldb, { 0x2080 },
(PTR) & fmt_ldb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDB_D, "ldb-d", "ldb",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0800000,
+ & fmt_ldb_d, { 0xa0800000 },
(PTR) & fmt_ldb_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDH, "ldh", "ldh",
{ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x20a0,
+ & fmt_ldh, { 0x20a0 },
(PTR) & fmt_ldh_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDH_D, "ldh-d", "ldh",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0a00000,
+ & fmt_ldh_d, { 0xa0a00000 },
(PTR) & fmt_ldh_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDUB, "ldub", "ldub",
{ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x2090,
+ & fmt_ldb, { 0x2090 },
(PTR) & fmt_ldb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDUB_D, "ldub-d", "ldub",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0900000,
+ & fmt_ldb_d, { 0xa0900000 },
(PTR) & fmt_ldb_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDUH, "lduh", "lduh",
{ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x20b0,
+ & fmt_ldh, { 0x20b0 },
(PTR) & fmt_ldh_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDUH_D, "lduh-d", "lduh",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0b00000,
+ & fmt_ldh_d, { 0xa0b00000 },
(PTR) & fmt_ldh_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LD_PLUS, "ld-plus", "ld",
{ { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
- { 16, 16, 0xf0f0 }, 0x20e0,
+ & fmt_ld_plus, { 0x20e0 },
(PTR) & fmt_ld_plus_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LD24, "ld24", "ld24",
{ { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
- { 32, 32, 0xf0000000 }, 0xe0000000,
+ & fmt_ld24, { 0xe0000000 },
(PTR) & fmt_ld24_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDI8, "ldi8", "ldi8",
{ { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
- { 16, 16, 0xf000 }, 0x6000,
+ & fmt_ldi8, { 0x6000 },
(PTR) & fmt_ldi8_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LDI16, "ldi16", "ldi16",
{ { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
- { 32, 32, 0xf0ff0000 }, 0x90f00000,
+ & fmt_ldi16, { 0x90f00000 },
(PTR) & fmt_ldi16_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_LOCK, "lock", "lock",
{ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x20d0,
+ & fmt_lock, { 0x20d0 },
(PTR) & fmt_lock_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACHI, "machi", "machi",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x3040,
+ & fmt_machi, { 0x3040 },
(PTR) & fmt_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACHI_A, "machi-a", "machi",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
- { 16, 16, 0xf070 }, 0x3040,
+ & fmt_machi_a, { 0x3040 },
(PTR) & fmt_machi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACLO, "maclo", "maclo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x3050,
+ & fmt_machi, { 0x3050 },
(PTR) & fmt_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACLO_A, "maclo-a", "maclo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
- { 16, 16, 0xf070 }, 0x3050,
+ & fmt_machi_a, { 0x3050 },
(PTR) & fmt_machi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACWHI, "macwhi", "macwhi",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x3060,
+ & fmt_machi, { 0x3060 },
(PTR) & fmt_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACWHI_A, "macwhi-a", "macwhi",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
- { 16, 16, 0xf070 }, 0x3060,
+ & fmt_machi_a, { 0x3060 },
(PTR) & fmt_machi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACWLO, "macwlo", "macwlo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x3070,
+ & fmt_machi, { 0x3070 },
(PTR) & fmt_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACWLO_A, "macwlo-a", "macwlo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
- { 16, 16, 0xf070 }, 0x3070,
+ & fmt_machi_a, { 0x3070 },
(PTR) & fmt_machi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MUL, "mul", "mul",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x1060,
+ & fmt_add, { 0x1060 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULHI, "mulhi", "mulhi",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x3000,
+ & fmt_mulhi, { 0x3000 },
(PTR) & fmt_mulhi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULHI_A, "mulhi-a", "mulhi",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
- { 16, 16, 0xf070 }, 0x3000,
+ & fmt_mulhi_a, { 0x3000 },
(PTR) & fmt_mulhi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULLO, "mullo", "mullo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x3010,
+ & fmt_mulhi, { 0x3010 },
(PTR) & fmt_mulhi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULLO_A, "mullo-a", "mullo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
- { 16, 16, 0xf070 }, 0x3010,
+ & fmt_mulhi_a, { 0x3010 },
(PTR) & fmt_mulhi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULWHI, "mulwhi", "mulwhi",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x3020,
+ & fmt_mulhi, { 0x3020 },
(PTR) & fmt_mulhi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
- { 16, 16, 0xf070 }, 0x3020,
+ & fmt_mulhi_a, { 0x3020 },
(PTR) & fmt_mulhi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULWLO, "mulwlo", "mulwlo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x3030,
+ & fmt_mulhi, { 0x3030 },
(PTR) & fmt_mulhi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
- { 16, 16, 0xf070 }, 0x3030,
+ & fmt_mulhi_a, { 0x3030 },
(PTR) & fmt_mulhi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MV, "mv", "mv",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x1080,
+ & fmt_mv, { 0x1080 },
(PTR) & fmt_mv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVFACHI, "mvfachi", "mvfachi",
{ { MNEM, ' ', OP (DR), 0 } },
- { 16, 16, 0xf0ff }, 0x50f0,
+ & fmt_mvfachi, { 0x50f0 },
(PTR) & fmt_mvfachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi",
{ { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
- { 16, 16, 0xf0f3 }, 0x50f0,
+ & fmt_mvfachi_a, { 0x50f0 },
(PTR) & fmt_mvfachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo",
{ { MNEM, ' ', OP (DR), 0 } },
- { 16, 16, 0xf0ff }, 0x50f1,
+ & fmt_mvfachi, { 0x50f1 },
(PTR) & fmt_mvfachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo",
{ { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
- { 16, 16, 0xf0f3 }, 0x50f1,
+ & fmt_mvfachi_a, { 0x50f1 },
(PTR) & fmt_mvfachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi",
{ { MNEM, ' ', OP (DR), 0 } },
- { 16, 16, 0xf0ff }, 0x50f2,
+ & fmt_mvfachi, { 0x50f2 },
(PTR) & fmt_mvfachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi",
{ { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
- { 16, 16, 0xf0f3 }, 0x50f2,
+ & fmt_mvfachi_a, { 0x50f2 },
(PTR) & fmt_mvfachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVFC, "mvfc", "mvfc",
{ { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
- { 16, 16, 0xf0f0 }, 0x1090,
+ & fmt_mvfc, { 0x1090 },
(PTR) & fmt_mvfc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVTACHI, "mvtachi", "mvtachi",
{ { MNEM, ' ', OP (SRC1), 0 } },
- { 16, 16, 0xf0ff }, 0x5070,
+ & fmt_mvtachi, { 0x5070 },
(PTR) & fmt_mvtachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi",
{ { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
- { 16, 16, 0xf0f3 }, 0x5070,
+ & fmt_mvtachi_a, { 0x5070 },
(PTR) & fmt_mvtachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo",
{ { MNEM, ' ', OP (SRC1), 0 } },
- { 16, 16, 0xf0ff }, 0x5071,
+ & fmt_mvtachi, { 0x5071 },
(PTR) & fmt_mvtachi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo",
{ { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
- { 16, 16, 0xf0f3 }, 0x5071,
+ & fmt_mvtachi_a, { 0x5071 },
(PTR) & fmt_mvtachi_a_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MVTC, "mvtc", "mvtc",
{ { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
- { 16, 16, 0xf0f0 }, 0x10a0,
+ & fmt_mvtc, { 0x10a0 },
(PTR) & fmt_mvtc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_NEG, "neg", "neg",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x30,
+ & fmt_mv, { 0x30 },
(PTR) & fmt_mv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_NOP, "nop", "nop",
{ { MNEM, 0 } },
- { 16, 16, 0xffff }, 0x7000,
+ & fmt_nop, { 0x7000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_NOT, "not", "not",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0xb0,
+ & fmt_mv, { 0xb0 },
(PTR) & fmt_mv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_RAC, "rac", "rac",
{ { MNEM, 0 } },
- { 16, 16, 0xffff }, 0x5090,
+ & fmt_rac, { 0x5090 },
(PTR) & fmt_rac_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_RAC_DSI, "rac-dsi", "rac",
{ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
- { 16, 16, 0xf3f2 }, 0x5090,
+ & fmt_rac_dsi, { 0x5090 },
(PTR) & fmt_rac_dsi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_RACH, "rach", "rach",
{ { MNEM, 0 } },
- { 16, 16, 0xffff }, 0x5080,
+ & fmt_rac, { 0x5080 },
(PTR) & fmt_rac_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_RACH_DSI, "rach-dsi", "rach",
{ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
- { 16, 16, 0xf3f2 }, 0x5080,
+ & fmt_rac_dsi, { 0x5080 },
(PTR) & fmt_rac_dsi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_RTE, "rte", "rte",
{ { MNEM, 0 } },
- { 16, 16, 0xffff }, 0x10d6,
+ & fmt_rte, { 0x10d6 },
(PTR) & fmt_rte_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SETH, "seth", "seth",
{ { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
- { 32, 32, 0xf0ff0000 }, 0xd0c00000,
+ & fmt_seth, { 0xd0c00000 },
(PTR) & fmt_seth_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SLL, "sll", "sll",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x1040,
+ & fmt_add, { 0x1040 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SLL3, "sll3", "sll3",
{ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
- { 32, 32, 0xf0f00000 }, 0x90c00000,
+ & fmt_sll3, { 0x90c00000 },
(PTR) & fmt_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SLLI, "slli", "slli",
{ { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
- { 16, 16, 0xf0e0 }, 0x5040,
+ & fmt_slli, { 0x5040 },
(PTR) & fmt_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SRA, "sra", "sra",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x1020,
+ & fmt_add, { 0x1020 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SRA3, "sra3", "sra3",
{ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
- { 32, 32, 0xf0f00000 }, 0x90a00000,
+ & fmt_sll3, { 0x90a00000 },
(PTR) & fmt_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SRAI, "srai", "srai",
{ { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
- { 16, 16, 0xf0e0 }, 0x5020,
+ & fmt_slli, { 0x5020 },
(PTR) & fmt_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SRL, "srl", "srl",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x1000,
+ & fmt_add, { 0x1000 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SRL3, "srl3", "srl3",
{ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
- { 32, 32, 0xf0f00000 }, 0x90800000,
+ & fmt_sll3, { 0x90800000 },
(PTR) & fmt_sll3_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SRLI, "srli", "srli",
{ { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
- { 16, 16, 0xf0e0 }, 0x5000,
+ & fmt_slli, { 0x5000 },
(PTR) & fmt_slli_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ST, "st", "st",
{ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x2040,
+ & fmt_st, { 0x2040 },
(PTR) & fmt_st_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ST_D, "st-d", "st",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0400000,
+ & fmt_st_d, { 0xa0400000 },
(PTR) & fmt_st_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_STB, "stb", "stb",
{ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x2000,
+ & fmt_stb, { 0x2000 },
(PTR) & fmt_stb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_STB_D, "stb-d", "stb",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0000000,
+ & fmt_stb_d, { 0xa0000000 },
(PTR) & fmt_stb_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_STH, "sth", "sth",
{ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x2020,
+ & fmt_sth, { 0x2020 },
(PTR) & fmt_sth_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_STH_D, "sth-d", "sth",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0200000,
+ & fmt_sth_d, { 0xa0200000 },
(PTR) & fmt_sth_d_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ST_PLUS, "st-plus", "st",
{ { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x2060,
+ & fmt_st_plus, { 0x2060 },
(PTR) & fmt_st_plus_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_ST_MINUS, "st-minus", "st",
{ { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x2070,
+ & fmt_st_plus, { 0x2070 },
(PTR) & fmt_st_plus_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SUB, "sub", "sub",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x20,
+ & fmt_add, { 0x20 },
(PTR) & fmt_add_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SUBV, "subv", "subv",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x0,
+ & fmt_addv, { 0x0 },
(PTR) & fmt_addv_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SUBX, "subx", "subx",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 16, 16, 0xf0f0 }, 0x10,
+ & fmt_addx, { 0x10 },
(PTR) & fmt_addx_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_TRAP, "trap", "trap",
{ { MNEM, ' ', OP (UIMM4), 0 } },
- { 16, 16, 0xfff0 }, 0x10f0,
+ & fmt_trap, { 0x10f0 },
(PTR) & fmt_trap_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_UNLOCK, "unlock", "unlock",
{ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x2050,
+ & fmt_unlock, { 0x2050 },
(PTR) & fmt_unlock_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SATB, "satb", "satb",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 32, 32, 0xf0f0ffff }, 0x80600300,
+ & fmt_satb, { 0x80600300 },
(PTR) & fmt_satb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SATH, "sath", "sath",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 32, 32, 0xf0f0ffff }, 0x80600200,
+ & fmt_satb, { 0x80600200 },
(PTR) & fmt_satb_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SAT, "sat", "sat",
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
- { 32, 32, 0xf0f0ffff }, 0x80600000,
+ & fmt_sat, { 0x80600000 },
(PTR) & fmt_sat_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz",
{ { MNEM, ' ', OP (SRC2), 0 } },
- { 16, 16, 0xfff0 }, 0x370,
+ & fmt_cmpz, { 0x370 },
(PTR) & fmt_cmpz_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SADD, "sadd", "sadd",
{ { MNEM, 0 } },
- { 16, 16, 0xffff }, 0x50e4,
+ & fmt_sadd, { 0x50e4 },
(PTR) & fmt_sadd_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACWU1, "macwu1", "macwu1",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x50b0,
+ & fmt_macwu1, { 0x50b0 },
(PTR) & fmt_macwu1_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MSBLO, "msblo", "msblo",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x50d0,
+ & fmt_machi, { 0x50d0 },
(PTR) & fmt_machi_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MULWU1, "mulwu1", "mulwu1",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x50a0,
+ & fmt_mulwu1, { 0x50a0 },
(PTR) & fmt_mulwu1_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_MACLH1, "maclh1", "maclh1",
{ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
- { 16, 16, 0xf0f0 }, 0x50c0,
+ & fmt_macwu1, { 0x50c0 },
(PTR) & fmt_macwu1_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SC, "sc", "sc",
{ { MNEM, 0 } },
- { 16, 16, 0xffff }, 0x7401,
+ & fmt_sc, { 0x7401 },
(PTR) & fmt_sc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
{ 1, 1, 1, 1 },
M32R_INSN_SNC, "snc", "snc",
{ { MNEM, 0 } },
- { 16, 16, 0xffff }, 0x7501,
+ & fmt_sc, { 0x7501 },
(PTR) & fmt_sc_ops[0],
{ CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
NULL
};
+/* Formats for ALIAS macro-insns. */
+
+#define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)]
+
+static const CGEN_IFMT fmt_bc8r = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT fmt_bc24r = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+static const CGEN_IFMT fmt_bl8r = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT fmt_bl24r = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_bcl8r = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_bcl24r = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_bnc8r = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT fmt_bnc24r = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+static const CGEN_IFMT fmt_bra8r = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+static const CGEN_IFMT fmt_bra24r = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_bncl8r = {
+ 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_bncl24r = {
+ 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_ld_2 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ld_d2 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_ldb_2 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ldb_d2 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_ldh_2 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ldh_d2 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_ldub_2 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ldub_d2 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_lduh_2 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_lduh_d2 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_pop = {
+ 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_ldi8a = {
+ 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 }
+};
+
+static const CGEN_IFMT fmt_ldi16a = {
+ 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_rac_d = {
+ 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_rac_ds = {
+ 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_rach_d = {
+ 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+static const CGEN_IFMT fmt_rach_ds = {
+ 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 }
+};
+
+/* end-sanitize-m32rx */
+static const CGEN_IFMT fmt_st_2 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_st_d2 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_stb_2 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_stb_d2 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_sth_2 = {
+ 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+static const CGEN_IFMT fmt_sth_d2 = {
+ 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 }
+};
+
+static const CGEN_IFMT fmt_push = {
+ 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 }
+};
+
+#undef F
+
/* Each non-simple macro entry points to an array of expansion possibilities. */
#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
{ 1, 1, 1, 1 },
-1, "bc8r", "bc",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7c00,
+ & fmt_bc8r, { 0x7c00 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "bc24r", "bc",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xfc000000,
+ & fmt_bc24r, { 0xfc000000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "bl8r", "bl",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7e00,
+ & fmt_bl8r, { 0x7e00 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "bl24r", "bl",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xfe000000,
+ & fmt_bl24r, { 0xfe000000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
+/* start-sanitize-m32rx */
/* bcl $disp8 */
{
{ 1, 1, 1, 1 },
-1, "bcl8r", "bcl",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7800,
+ & fmt_bcl8r, { 0x7800 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
},
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
/* bcl $disp24 */
{
{ 1, 1, 1, 1 },
-1, "bcl24r", "bcl",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xf8000000,
+ & fmt_bcl24r, { 0xf8000000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
},
+/* end-sanitize-m32rx */
/* bnc $disp8 */
{
{ 1, 1, 1, 1 },
-1, "bnc8r", "bnc",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7d00,
+ & fmt_bnc8r, { 0x7d00 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "bnc24r", "bnc",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xfd000000,
+ & fmt_bnc24r, { 0xfd000000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "bra8r", "bra",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7f00,
+ & fmt_bra8r, { 0x7f00 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "bra24r", "bra",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xff000000,
+ & fmt_bra24r, { 0xff000000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
+/* start-sanitize-m32rx */
/* bncl $disp8 */
{
{ 1, 1, 1, 1 },
-1, "bncl8r", "bncl",
{ { MNEM, ' ', OP (DISP8), 0 } },
- { 16, 16, 0xff00 }, 0x7900,
+ & fmt_bncl8r, { 0x7900 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
},
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
/* bncl $disp24 */
{
{ 1, 1, 1, 1 },
-1, "bncl24r", "bncl",
{ { MNEM, ' ', OP (DISP24), 0 } },
- { 32, 32, 0xff000000 }, 0xf9000000,
+ & fmt_bncl24r, { 0xf9000000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
},
+/* end-sanitize-m32rx */
/* ld $dr,@($sr) */
{
{ 1, 1, 1, 1 },
-1, "ld-2", "ld",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
- { 16, 16, 0xf0f0 }, 0x20c0,
+ & fmt_ld_2, { 0x20c0 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "ld-d2", "ld",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0c00000,
+ & fmt_ld_d2, { 0xa0c00000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "ldb-2", "ldb",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
- { 16, 16, 0xf0f0 }, 0x2080,
+ & fmt_ldb_2, { 0x2080 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "ldb-d2", "ldb",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0800000,
+ & fmt_ldb_d2, { 0xa0800000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "ldh-2", "ldh",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
- { 16, 16, 0xf0f0 }, 0x20a0,
+ & fmt_ldh_2, { 0x20a0 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "ldh-d2", "ldh",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0a00000,
+ & fmt_ldh_d2, { 0xa0a00000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "ldub-2", "ldub",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
- { 16, 16, 0xf0f0 }, 0x2090,
+ & fmt_ldub_2, { 0x2090 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "ldub-d2", "ldub",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0900000,
+ & fmt_ldub_d2, { 0xa0900000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "lduh-2", "lduh",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
- { 16, 16, 0xf0f0 }, 0x20b0,
+ & fmt_lduh_2, { 0x20b0 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "lduh-d2", "lduh",
{ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0b00000,
+ & fmt_lduh_d2, { 0xa0b00000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "pop", "pop",
{ { MNEM, ' ', OP (DR), 0 } },
- { 16, 16, 0xf0ff }, 0x20ef,
+ & fmt_pop, { 0x20ef },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "ldi8a", "ldi",
{ { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
- { 16, 16, 0xf000 }, 0x6000,
+ & fmt_ldi8a, { 0x6000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
},
{ 1, 1, 1, 1 },
-1, "ldi16a", "ldi",
{ { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
- { 32, 32, 0xf0ff0000 }, 0x90f00000,
+ & fmt_ldi16a, { 0x90f00000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
+/* start-sanitize-m32rx */
/* rac $accd */
{
{ 1, 1, 1, 1 },
-1, "rac-d", "rac",
{ { MNEM, ' ', OP (ACCD), 0 } },
- { 16, 16, 0xf3ff }, 0x5090,
+ & fmt_rac_d, { 0x5090 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
/* rac $accd,$accs */
{
{ 1, 1, 1, 1 },
-1, "rac-ds", "rac",
{ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
- { 16, 16, 0xf3f3 }, 0x5090,
+ & fmt_rac_ds, { 0x5090 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
/* rach $accd */
{
{ 1, 1, 1, 1 },
-1, "rach-d", "rach",
{ { MNEM, ' ', OP (ACCD), 0 } },
- { 16, 16, 0xf3ff }, 0x5080,
+ & fmt_rach_d, { 0x5080 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
/* rach $accd,$accs */
{
{ 1, 1, 1, 1 },
-1, "rach-ds", "rach",
{ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
- { 16, 16, 0xf3f3 }, 0x5080,
+ & fmt_rach_ds, { 0x5080 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
},
+/* end-sanitize-m32rx */
/* st $src1,@($src2) */
{
{ 1, 1, 1, 1 },
-1, "st-2", "st",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
- { 16, 16, 0xf0f0 }, 0x2040,
+ & fmt_st_2, { 0x2040 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "st-d2", "st",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0400000,
+ & fmt_st_d2, { 0xa0400000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "stb-2", "stb",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
- { 16, 16, 0xf0f0 }, 0x2000,
+ & fmt_stb_2, { 0x2000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "stb-d2", "stb",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0000000,
+ & fmt_stb_d2, { 0xa0000000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "sth-2", "sth",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
- { 16, 16, 0xf0f0 }, 0x2020,
+ & fmt_sth_2, { 0x2020 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
{ 1, 1, 1, 1 },
-1, "sth-d2", "sth",
{ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
- { 32, 32, 0xf0f00000 }, 0xa0200000,
+ & fmt_sth_d2, { 0xa0200000 },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
{ 1, 1, 1, 1 },
-1, "push", "push",
{ { MNEM, ' ', OP (SRC1), 0 } },
- { 16, 16, 0xf0ff }, 0x207f,
+ & fmt_push, { 0x207f },
(PTR) 0,
{ CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
},
static unsigned int
dis_hash_insn (buf, value)
const char * buf;
- unsigned long value;
+ CGEN_INSN_INT value;
{
return CGEN_DIS_HASH (buf, value);
}
CGEN_OPCODE_HW_LIST (table) = & m32r_cgen_hw_entries[0];
+ CGEN_OPCODE_IFLD_TABLE (table) = & m32r_cgen_ifld_table[0];
+
CGEN_OPCODE_OPERAND_TABLE (table) = & m32r_cgen_operand_table[0];
* CGEN_OPCODE_INSN_TABLE (table) = insn_table;
#define CGEN_ARCH m32r
-/* Given symbol S, return m32r_cgen_<s>. */
+/* Given symbol S, return m32r_cgen_<S>. */
#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
/* Selected cpu families. */
-#define HAVE_CPU_M32R
+#define HAVE_CPU_M32RBF
/* start-sanitize-m32rx */
-#define HAVE_CPU_M32RX
+#define HAVE_CPU_M32RXF
/* end-sanitize-m32rx */
+#define CGEN_INSN_LSB0_P 0
#define CGEN_WORD_BITSIZE 32
#define CGEN_DEFAULT_INSN_BITSIZE 32
#define CGEN_BASE_INSN_BITSIZE 32
#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
-#define CGEN_INT_INSN
+#define CGEN_INT_INSN_P 1
/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
/* Maximum number of operands any insn or macro-insn has. */
#define CGEN_MAX_INSN_OPERANDS 16
+/* Maximum number of fields in an instruction. */
+#define CGEN_MAX_IFMT_OPERANDS 7
+
/* Enums. */
/* Enum declaration for insn format enums. */
/* Enum declaration for control registers. */
typedef enum h_cr {
H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
- , H_CR_BPC = 6, H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2
- , H_CR_CR3 = 3, H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6
- , H_CR_CR7 = 7, H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10
- , H_CR_CR11 = 11, H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14
- , H_CR_CR15 = 15
+ , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0
+ , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4
+ , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8
+ , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12
+ , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
} H_CR;
/* start-sanitize-m32rx */
} H_ACCUMS;
/* end-sanitize-m32rx */
-/* Enum declaration for m32r operand types. */
-typedef enum cgen_operand_type {
- M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
- , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
- , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
-/* start-sanitize-m32rx */
- , M32R_OPERAND_IMM1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ACCD
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ACCS
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ACC
-/* end-sanitize-m32rx */
- , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
- , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
- , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
-} CGEN_OPERAND_TYPE;
-
-/* Non-boolean attributes. */
+/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
- MACH_M32R
+ MACH_BASE, MACH_M32R
/* start-sanitize-m32rx */
, MACH_M32RX
/* end-sanitize-m32rx */
/* Number of architecture variants. */
#define MAX_MACHS ((int) MACH_MAX)
-/* Number of operands types. */
-#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
+/* Ifield attribute indices. */
-/* Maximum number of operands referenced by any insn. */
-#define MAX_OPERAND_INSTANCES 8
+/* Enum declaration for cgen_ifld attrs. */
+typedef enum cgen_ifld_attr {
+ CGEN_IFLD_MACH, CGEN_IFLD_VIRTUAL, CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR
+ , CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_RELOC
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld. */
+#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_VIRTUAL)
+
+/* Enum declaration for m32r ifield types. */
+typedef enum ifield_type {
+ M32R_F_NIL, M32R_F_OP1, M32R_F_OP2, M32R_F_COND
+ , M32R_F_R1, M32R_F_R2, M32R_F_SIMM8, M32R_F_SIMM16
+ , M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM16
+ , M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16
+ , M32R_F_DISP24
+/* start-sanitize-m32rx */
+ , M32R_F_OP23
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_F_OP3
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_F_ACC
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_F_ACCS
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_F_ACCD
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_F_BITS67
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_F_BIT14
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_F_IMM1
+/* end-sanitize-m32rx */
+ , M32R_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) M32R_F_MAX)
-/* Operand and instruction attribute indices. */
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_MACH, CGEN_HW_VIRTUAL, CGEN_HW_UNSIGNED, CGEN_HW_SIGNED
+ , CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS, CGEN_HW_PC, CGEN_HW_PROFILE
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw. */
+#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_VIRTUAL)
+
+/* Enum declaration for m32r hardware types. */
+typedef enum hw_type {
+ HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
+ , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
+ , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
+/* start-sanitize-m32rx */
+ , HW_H_ACCUMS
+/* end-sanitize-m32rx */
+ , HW_H_COND, HW_H_PSW, HW_H_BPSW, HW_H_BBPSW
+ , HW_H_LOCK, HW_MAX
+} HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
- CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE
- , CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT
- , CGEN_OPERAND_UNSIGNED
+ CGEN_OPERAND_MACH, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR
+ , CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX
+ , CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand. */
-#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
+#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_VIRTUAL)
+
+/* Enum declaration for m32r operand types. */
+typedef enum cgen_operand_type {
+ M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
+ , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
+ , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
+/* start-sanitize-m32rx */
+ , M32R_OPERAND_IMM1
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_OPERAND_ACCD
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_OPERAND_ACCS
+/* end-sanitize-m32rx */
+/* start-sanitize-m32rx */
+ , M32R_OPERAND_ACC
+/* end-sanitize-m32rx */
+ , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
+ , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
+ , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 11
+
+/* Insn attribute indices. */
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
/* start-sanitize-m32rx */
, CGEN_INSN_PIPE
/* end-sanitize-m32rx */
- , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_NO_DIS
- , CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SPECIAL
- , CGEN_INSN_UNCOND_CTI
+ , CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI
+ , CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX, CGEN_INSN_ALIAS
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT
+/* start-sanitize-m32rx */
+ , CGEN_INSN_SPECIAL
+/* end-sanitize-m32rx */
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn. */
-#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_ALIAS)
+#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_VIRTUAL)
/* Enum declaration for m32r instruction types. */
typedef enum cgen_insn_type {
- M32R_INSN_ILLEGAL, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND
+ M32R_INSN_INVALID, M32R_INSN_ADD, M32R_INSN_ADD3, M32R_INSN_AND
, M32R_INSN_AND3, M32R_INSN_OR, M32R_INSN_OR3, M32R_INSN_XOR
, M32R_INSN_XOR3, M32R_INSN_ADDI, M32R_INSN_ADDV, M32R_INSN_ADDV3
, M32R_INSN_ADDX, M32R_INSN_BC8, M32R_INSN_BC24, M32R_INSN_BEQ
, M32R_INSN_MAX
} CGEN_INSN_TYPE;
-/* Index of `illegal' insn place holder. */
-#define CGEN_INSN_ILLEGAL M32R_INSN_ILLEGAL
+/* Index of `invalid' insn place holder. */
+#define CGEN_INSN_INVALID M32R_INSN_INVALID
/* Total number of insns in table. */
#define MAX_INSNS ((int) M32R_INSN_MAX)
};
/* Attributes. */
+extern const CGEN_ATTR_TABLE m32r_cgen_hw_attr_table[];
extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[];
-/* Enum declaration for m32r hardware types. */
-typedef enum hw_type {
- HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
- , HW_H_ADDR, HW_H_IADDR, HW_H_HI16, HW_H_SLO16
- , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
-/* start-sanitize-m32rx */
- , HW_H_ACCUMS
-/* end-sanitize-m32rx */
- , HW_H_COND, HW_H_SM, HW_H_BSM, HW_H_IE
- , HW_H_BIE, HW_H_BCOND, HW_H_BPC, HW_H_LOCK
- , HW_MAX
-} HW_TYPE;
-
-#define MAX_HW ((int) HW_MAX)
-
/* Hardware decls. */
extern CGEN_KEYWORD m32r_cgen_opval_h_gr;
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