re PR target/53511 (SH Target: Add support for fma patterns)

	PR target/53511
	* config/sh/sh.md (mulsf3_ie): Delete.
	(mulsf3_i4): Rename to mulsf3_i.
	(mulsf3): Emit mulsf3_i insn.

From-SVN: r189796

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 76872a68003524e5e1702250782dfffb386dc1dc..790677c26d851b5e7d2ca870f55f2eac5c7d5191 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2012-07-23  Oleg Endo  <olegendo@gcc.gnu.org>
+
+       PR target/53511
+       * config/sh/sh.md (mulsf3_ie): Delete.
+       (mulsf3_i4): Rename to mulsf3_i.
+       (mulsf3): Emit mulsf3_i insn.
+
 2012-07-23  Oleg Endo  <olegendo@gcc.gnu.org>
 
        * config/sh/sh.md (addc1, subc1): Delete.

diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 9d3e0c4facdf405294b55b54e03334882b2dc541..08926d990d9ef10bed0670db43cf903e6e5caabc 100644 (file)
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -10229,7 +10229,14 @@ label:
        (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
                 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
   "TARGET_SH2E || TARGET_SHMEDIA_FPU"
-  "")
+{
+  if (TARGET_SH2E)
+    {
+      emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2],
+                get_fpscr_rtx ()));
+      DONE;
+    }
+})
 
 (define_insn "*mulsf3_media"
   [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
@@ -10239,30 +10246,7 @@ label:
   "fmul.s      %1, %2, %0"
   [(set_attr "type" "fparith_media")])
 
-;; FIXME: These fmac combine pass assisting specifics are obsolete since 
-;;       we now use the FMA patterns, which do not depend on the combine
-;;       pass anymore.
-;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
-;; register in feeding fp instructions.  Thus, in order to generate fmac,
-;; we start out with a mulsf pattern that does not depend on fpscr.
-;; This is split after combine to introduce the dependency, in order to
-;; get mode switching and scheduling right.
-(define_insn_and_split "mulsf3_ie"
-  [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
-       (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
-                (match_operand:SF 2 "fp_arith_reg_operand" "f")))]
-  "TARGET_SH2E"
-  "fmul        %2,%0"
-  "TARGET_SH4 || TARGET_SH2A_SINGLE"
-  [(const_int 0)]
-{
-  emit_insn (gen_mulsf3_i4 (operands[0], operands[1], operands[2],
-            get_fpscr_rtx ()));
-  DONE;
-}
-  [(set_attr "type" "fp")])
-
-(define_insn "mulsf3_i4"
+(define_insn "mulsf3_i"
   [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
        (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
                 (match_operand:SF 2 "fp_arith_reg_operand" "f")))