ARM: Make LDM that loads the PC perform an interworking branch.

diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 474e4fab0504bb0315356a74e5efb75698415399..13eb70b39f55e9c21e713612479ec5d38ff51801 100644 (file)
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -53,7 +53,7 @@ let {{
 let {{
     microLdrUopIop = InstObjParams('ldr_uop', 'MicroLdrUop',
                                    'MicroMemOp',
-                                   {'memacc_code': 'Ra = Mem;',
+                                   {'memacc_code': 'IWRa = Mem;',
                                     'ea_code': 'EA = Rb + (up ? imm : -imm);',
                                     'predicate_test': predicateTest},
                                    ['IsMicroop'])

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index c507864b6b685418e4c8fd406417d677f53a8fd5..c845acc94f0bc314ae3795e0ef63a81d75ba3e6e 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -129,6 +129,8 @@ def operands {{
 
     #Register fields for microops
     'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
+    'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11,
+            maybePCRead, maybeIWPCWrite),
     'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11),
     'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),