radeonsi: remove TC L2 cache flush for index buffers on VI

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 43170ec446b96192ad2f3e5bda3474b9a1ac5504..5face4239413287b7339e1d7ec453a8cbf337ac2 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -813,9 +813,9 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                }
        }
 
-       /* TODO: VI should read index buffers through TC, so this shouldn't be
-        * needed on VI. */
-       if (info->indexed && r600_resource(ib.buffer)->TC_L2_dirty) {
+       /* VI reads index buffers through TC L2. */
+       if (info->indexed && sctx->b.chip_class <= CIK &&
+           r600_resource(ib.buffer)->TC_L2_dirty) {
                sctx->b.flags |= SI_CONTEXT_INV_TC_L2;
                r600_resource(ib.buffer)->TC_L2_dirty = false;
        }