re PR rtl-optimization/87361 (gcc.target/sparc/20161111-1.c FAILs)

	PR rtl-optimization/87361
	* rtlanal.c (nonzero_bits1): Revert accidental change.

From-SVN: r264420

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 68d8be20e71dcb78e679251906acadbf279f749d..1ad3fd05002aefcc3e77a69307452785c2c1687b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-09-19  Eric Botcazou  <ebotcazou@adacore.com>
+
+       PR rtl-optimization/87361
+       * rtlanal.c (nonzero_bits1): Revert accidental change.
+
 2018-09-19  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/87349

diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 366df7c9b3fa23a9750941884cc1116498b8399c..e8b6b9c7a4288fe21362903a28b62d4a797e82c4 100644 (file)
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -4758,17 +4758,17 @@ nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
          nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
                                          known_x, known_mode, known_ret);
 
-         /* On many CISC machines, accessing an object in a wider mode
+          /* On many CISC machines, accessing an object in a wider mode
             causes the high-order bits to become undefined.  So they are
             not known to be zero.  */
          rtx_code extend_op;
          if ((!WORD_REGISTER_OPERATIONS
               /* If this is a typical RISC machine, we only have to worry
                  about the way loads are extended.  */
-              || !MEM_P (SUBREG_REG (x))
               || ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND
                   ? val_signbit_known_set_p (inner_mode, nonzero)
-                  : extend_op != ZERO_EXTEND))
+                  : extend_op != ZERO_EXTEND)
+              || (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x))))
              && xmode_width > inner_width)
            nonzero
              |= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK (inner_mode));