S/390: Mode attrs "bitoff[_plus]" simplify risbg instructions.

Add a new mode attribute to simplify some instruction patterns.

gcc/ChangeLog:

2016-09-23  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* config/s390/s390.md (bitoff, bitoff_plus): Neq mode attributes.
	("*extzv<mode>_zEC12", "*insv<mode>_zEC12", "*insv<mode>_z10")
	("*insv<mode>_zEC12_appendbitsleft")
	("*insv<mode>_z10_appendbitsleft", "*r<noxa>sbg_<mode>_sll")
	("*r<noxa>sbg_<mode>_srl"): Use new attributes.

gcc/testsuite/ChangeLog:

2016-09-23  Dominik Vogt  <vogt@linux.vnet.ibm.com>

	* gcc.target/s390/md/rXsbg_mode_sXl.c: Adapt expected assembly
	output to the simplified instructions.

From-SVN: r240409

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 36795f41211401ba958bb2e192118ca07ef3197e..bd699e9d0719f8b82de66b65a070a1e41abdb169 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2016-09-23  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+       * config/s390/s390.md (bitoff, bitoff_plus): Neq mode attributes.
+       ("*extzv<mode>_zEC12", "*insv<mode>_zEC12", "*insv<mode>_z10")
+       ("*insv<mode>_zEC12_appendbitsleft")
+       ("*insv<mode>_z10_appendbitsleft", "*r<noxa>sbg_<mode>_sll")
+       ("*r<noxa>sbg_<mode>_srl"): Use new attributes.
+
 2016-09-23  Jakub Jelinek  <jakub@redhat.com>
 
        * ipa-cp.c (ipcp_store_vr_results): Avoid static local

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 30ddc14a46f609e65fd0d22f9fe91547cc406e3d..21ff33ed53962dd75fa96bd95afa5f4e71c1aa38 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -761,6 +761,9 @@
 
 ;; In place of GET_MODE_BITSIZE (<MODE>mode)
 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
+;; 64 - bitsize
+(define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
+(define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
 
 ;; In place of GET_MODE_SIZE (<MODE>mode)
 (define_mode_attr modesize [(DI "8") (SI "4")])
@@ -3754,7 +3757,7 @@
         (match_operand 2 "const_int_operand" "")   ; size
         (match_operand 3 "const_int_operand" "")))] ; start]
   "TARGET_ZEC12"
-  "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
+  "risbgn\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
   [(set_attr "op_type" "RIE")])
 
 (define_insn "*extzv<mode>_z10"
@@ -3846,7 +3849,7 @@
        (match_operand:GPR 3 "nonimmediate_operand" "d"))]
   "TARGET_ZEC12
    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
-  "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
+  "risbgn\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
   [(set_attr "op_type" "RIE")])
 
 (define_insn "*insv<mode>_z10"
@@ -3857,7 +3860,7 @@
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_Z10
    && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
-  "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
+  "risbg\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
 
@@ -3894,7 +3897,7 @@
                 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
                             (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
   "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
-  "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
+  "risbgn\t%0,%3,<bitoff>,64-%4-1,%4"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
 
@@ -3906,7 +3909,7 @@
                             (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
-  "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
+  "risbg\t%0,%3,<bitoff>,64-%4-1,%4"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
 
@@ -4035,7 +4038,7 @@
          (match_operand:GPR 3 "nonimmediate_operand" "0")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_Z10"
-  "r<noxa>sbg\t%0,%1,64-<bitsize>,63-%2,%2"
+  "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2"
   [(set_attr "op_type" "RIE")])
 
 ;; unsigned {int,long} a, b
@@ -4050,7 +4053,7 @@
          (match_operand:GPR 3 "nonimmediate_operand" "0")))
    (clobber (reg:CC CC_REGNUM))]
   "TARGET_Z10"
-  "r<noxa>sbg\t%0,%1,64-<bitsize>+%2,63,64-%2"
+  "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2"
   [(set_attr "op_type" "RIE")])
 
 ;; These two are generated by combine for s.bf &= val.

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3475f5a81cbcf7b0ba6af4b150ddaae4dc224718..dd416a6314a9ebd16d078e6533274a376edac1f3 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-09-23  Dominik Vogt  <vogt@linux.vnet.ibm.com>
+
+       * gcc.target/s390/md/rXsbg_mode_sXl.c: Adapt expected assembly
+       output to the simplified instructions.
+
 2016-09-23  Matthew Wahab  <matthew.wahab@arm.com>
 
        * gcc.target/arm/armv8_2_fp16-move-1.c: New.

diff --git a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
index 178a537b1de560398031e8a41095a1df7d01447f..ad442dad9317b334f6358bc1ee0cfb39a329d1bc 100644 (file)
--- a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
+++ b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c
@@ -39,28 +39,28 @@ rosbg_si_sll (unsigned int a, unsigned int b)
 {
   return a | (b << 1);
 }
-/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-32,63-1,1" 1 } } */
+/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,63-1,1" 1 } } */
 
 __attribute__ ((noinline)) unsigned int
 rosbg_si_srl (unsigned int a, unsigned int b)
 {
   return a | (b >> 2);
 }
-/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-32\\+2,63,64-2" 1 } } */
+/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */
 
 __attribute__ ((noinline)) unsigned int
 rxsbg_si_sll (unsigned int a, unsigned int b)
 {
   return a ^ (b << 1);
 }
-/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-32,63-1,1" 1 } } */
+/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,63-1,1" 1 } } */
 
 __attribute__ ((noinline)) unsigned int
 rxsbg_si_srl (unsigned int a, unsigned int b)
 {
   return a ^ (b >> 2);
 }
-/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-32\\+2,63,64-2" 1 } } */
+/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */
 
 __attribute__ ((noinline)) unsigned long long
 di_sll (unsigned long long x)
@@ -79,28 +79,28 @@ rosbg_di_sll (unsigned long long a, unsigned long long b)
 {
   return a | (b << 1);
 }
-/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-64,63-1,1" 1 } } */
+/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,0,63-1,1" 1 } } */
 
 __attribute__ ((noinline)) unsigned long long
 rosbg_di_srl (unsigned long long a, unsigned long long b)
 {
   return a | (b >> 2);
 }
-/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-64\\+2,63,64-2" 1 } } */
+/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,2,63,64-2" 1 } } */
 
 __attribute__ ((noinline)) unsigned long long
 rxsbg_di_sll (unsigned long long a, unsigned long long b)
 {
   return a ^ (b << 1);
 }
-/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-64,63-1,1" 1 } } */
+/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,0,63-1,1" 1 } } */
 
 __attribute__ ((noinline)) unsigned long long
 rxsbg_di_srl (unsigned long long a, unsigned long long b)
 {
   return a ^ (b >> 2);
 }
-/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-64\\+2,63,64-2" 1 } } */
+/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,2,63,64-2" 1 } } */
 
 int
 main (void)