arch-riscv: fix GDB register cache

Fixes the definition of the RISC-V GDB register cache.  The latest
version, of RISC-V gdb, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8,
appears to only accept the 32 integer registers + the PC in the 'g'
packet.

This functions with the Linux toolchain (riscv64-unknown-linux-gnu-*),
but works best with the Newlib toolchain (riscv64-unknown-elf-*).

Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20028
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index fe339ffc8fd1e06e928f1d23f01d2797c5fe1e30..15d47e265e1ddfc749e3ebf8603f9899851f41d9 100644 (file)
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -167,15 +167,6 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
     for (int i = 0; i < NumIntArchRegs; i++)
         r.gpr[i] = context->readIntReg(i);
     r.pc = context->pcState().pc();
-    for (int i = 0; i < NumFloatRegs; i++)
-        r.fpr[i] = context->readFloatReg(i);
-
-    r.csr_base = context->readMiscReg(0);
-    r.fflags = context->readMiscReg(CSR_FFLAGS);
-    r.frm = context->readMiscReg(CSR_FRM);
-    r.fcsr = context->readMiscReg(CSR_FCSR);
-    for (int i = ExplicitCSRs; i < NumMiscRegs; i++)
-        r.csr[i - ExplicitCSRs] = context->readMiscReg(i);
 }
 
 void
@@ -185,15 +176,6 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
     for (int i = 0; i < NumIntArchRegs; i++)
         context->setIntReg(i, r.gpr[i]);
     context->pcState(r.pc);
-    for (int i = 0; i < NumFloatRegs; i++)
-        context->setFloatReg(i, r.fpr[i]);
-
-    context->setMiscReg(0, r.csr_base);
-    context->setMiscReg(CSR_FFLAGS, r.fflags);
-    context->setMiscReg(CSR_FRM, r.frm);
-    context->setMiscReg(CSR_FCSR, r.fcsr);
-    for (int i = ExplicitCSRs; i < NumMiscRegs; i++)
-        context->setMiscReg(i, r.csr[i - ExplicitCSRs]);
 }
 
 BaseGdbRegCache*

diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index 7fcb28dbf81921ac11ac944566db2bd4129068f6..02f68d2b21316199744aeb6d6d6e543047e49821 100644 (file)
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -50,9 +50,12 @@ namespace RiscvISA
 class RemoteGDB : public BaseRemoteGDB
 {
   protected:
-    static const int ExplicitCSRs = 4;
+    static const int NumGDBRegs = 4162;
+    static const int NumCSRs = 4096;
 
     bool acc(Addr addr, size_t len);
+    // A breakpoint will be 2 bytes if it is compressed and 4 if not
+    bool checkBpLen(size_t len) override { return len == 2 || len == 4; }
 
     class RiscvGdbRegCache : public BaseGdbRegCache
     {
@@ -61,14 +64,7 @@ class RemoteGDB : public BaseRemoteGDB
         struct {
             uint64_t gpr[NumIntArchRegs];
             uint64_t pc;
-            uint64_t fpr[NumFloatRegs];
-
-            uint64_t csr_base;
-            uint32_t fflags;
-            uint32_t frm;
-            uint32_t fcsr;
-            uint64_t csr[NumMiscRegs - ExplicitCSRs];
-        } __attribute__((__packed__)) r;
+        } r;
       public:
         char *data() const { return (char *)&r; }
         size_t size() const { return sizeof(r); }