kernel_stats.hh
locked_mem.hh
microcode_rom.hh
- mmaped_ipr.hh
+ mmapped_ipr.hh
mt.hh
process.hh
predecoder.hh
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-#ifndef __ARCH_ALPHA_MMAPED_IPR_HH__
-#define __ARCH_ALPHA_MMAPED_IPR_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for memory mapped IPR accesses.
- */
-
-#include "base/types.hh"
-#include "mem/packet.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-inline Tick
-handleIprRead(ThreadContext *xc, Packet *pkt)
-{
- panic("No handleIprRead implementation in Alpha\n");
-}
-
-
-inline Tick
-handleIprWrite(ThreadContext *xc, Packet *pkt)
-{
- panic("No handleIprWrite implementation in Alpha\n");
-}
-
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_MMAPED_IPR_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __ARCH_ALPHA_MMAPPED_IPR_HH__
+#define __ARCH_ALPHA_MMAPPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "base/types.hh"
+#include "mem/packet.hh"
+
+class ThreadContext;
+
+namespace AlphaISA {
+
+inline Tick
+handleIprRead(ThreadContext *xc, Packet *pkt)
+{
+ panic("No handleIprRead implementation in Alpha\n");
+}
+
+
+inline Tick
+handleIprWrite(ThreadContext *xc, Packet *pkt)
+{
+ panic("No handleIprWrite implementation in Alpha\n");
+}
+
+
+} // namespace AlphaISA
+
+#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Stephen Hines
- */
-
-#ifndef __ARCH_ARM_MMAPED_IPR_HH__
-#define __ARCH_ARM_MMAPED_IPR_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for memory mapped IPR accesses.
- */
-
-#include "base/misc.hh"
-#include "mem/packet.hh"
-
-class ThreadContext;
-
-namespace ArmISA
-{
-inline Tick
-handleIprRead(ThreadContext *xc, Packet *pkt)
-{
- panic("No implementation for handleIprRead in ARM\n");
-}
-
-inline Tick
-handleIprWrite(ThreadContext *xc, Packet *pkt)
-{
- panic("No implementation for handleIprWrite in ARM\n");
-}
-
-
-} // namespace ArmISA
-
-#endif
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Stephen Hines
+ */
+
+#ifndef __ARCH_ARM_MMAPPED_IPR_HH__
+#define __ARCH_ARM_MMAPPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "base/misc.hh"
+#include "mem/packet.hh"
+
+class ThreadContext;
+
+namespace ArmISA
+{
+inline Tick
+handleIprRead(ThreadContext *xc, Packet *pkt)
+{
+ panic("No implementation for handleIprRead in ARM\n");
+}
+
+inline Tick
+handleIprWrite(ThreadContext *xc, Packet *pkt)
+{
+ panic("No implementation for handleIprWrite in ARM\n");
+}
+
+
+} // namespace ArmISA
+
+#endif
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-#ifndef __ARCH_MIPS_MMAPED_IPR_HH__
-#define __ARCH_MIPS_MMAPED_IPR_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for memory mapped IPR accesses.
- */
-
-#include "base/misc.hh"
-#include "mem/packet.hh"
-
-class ThreadContext;
-
-namespace MipsISA
-{
-
-inline Tick
-handleIprRead(ThreadContext *xc, Packet *pkt)
-{
- panic("No implementation for handleIprRead in MIPS\n");
-}
-
-inline Tick
-handleIprWrite(ThreadContext *xc, Packet *pkt)
-{
- panic("No implementation for handleIprWrite in MIPS\n");
-}
-
-} // namespace MipsISA
-
-#endif
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __ARCH_MIPS_MMAPPED_IPR_HH__
+#define __ARCH_MIPS_MMAPPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "base/misc.hh"
+#include "mem/packet.hh"
+
+class ThreadContext;
+
+namespace MipsISA
+{
+
+inline Tick
+handleIprRead(ThreadContext *xc, Packet *pkt)
+{
+ panic("No implementation for handleIprRead in MIPS\n");
+}
+
+inline Tick
+handleIprWrite(ThreadContext *xc, Packet *pkt)
+{
+ panic("No implementation for handleIprWrite in MIPS\n");
+}
+
+} // namespace MipsISA
+
+#endif
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * Copyright (c) 2009 The University of Edinburgh
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Stephen Hines
- * Timothy M. Jones
- */
-
-#ifndef __ARCH_POWER_MMAPED_IPR_HH__
-#define __ARCH_POWER_MMAPED_IPR_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for memory mapped IPR accesses.
- */
-
-#include "base/misc.hh"
-#include "mem/packet.hh"
-
-class ThreadContext;
-
-namespace PowerISA
-{
-
-inline Tick
-handleIprRead(ThreadContext *xc, Packet *pkt)
-{
- panic("No implementation for handleIprRead in POWER\n");
-}
-
-inline Tick
-handleIprWrite(ThreadContext *xc, Packet *pkt)
-{
- panic("No implementation for handleIprWrite in POWER\n");
-}
-
-} // namespace PowerISA
-
-#endif // __ARCH_POWER_MMAPED_IPR_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007-2008 The Florida State University
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ * Stephen Hines
+ * Timothy M. Jones
+ */
+
+#ifndef __ARCH_POWER_MMAPPED_IPR_HH__
+#define __ARCH_POWER_MMAPPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "base/misc.hh"
+#include "mem/packet.hh"
+
+class ThreadContext;
+
+namespace PowerISA
+{
+
+inline Tick
+handleIprRead(ThreadContext *xc, Packet *pkt)
+{
+ panic("No implementation for handleIprRead in POWER\n");
+}
+
+inline Tick
+handleIprWrite(ThreadContext *xc, Packet *pkt)
+{
+ panic("No implementation for handleIprWrite in POWER\n");
+}
+
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_MMAPPED_IPR_HH__
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-#ifndef __ARCH_SPARC_MMAPED_IPR_HH__
-#define __ARCH_SPARC_MMAPED_IPR_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for memory mapped IPR accesses.
- */
-
-#include "config/full_system.hh"
-#include "cpu/thread_context.hh"
-#include "mem/packet.hh"
-#include "arch/sparc/tlb.hh"
-
-
-namespace SparcISA
-{
-
-inline Tick
-handleIprRead(ThreadContext *xc, Packet *pkt)
-{
-#if FULL_SYSTEM
- return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
-#else
- panic("Shouldn't have a memory mapped register in SE\n");
-#endif
-}
-
-inline Tick
-handleIprWrite(ThreadContext *xc, Packet *pkt)
-{
-#if FULL_SYSTEM
- return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
-#else
- panic("Shouldn't have a memory mapped register in SE\n");
-#endif
-}
-
-
-} // namespace SparcISA
-
-#endif
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
+#define __ARCH_SPARC_MMAPPED_IPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "config/full_system.hh"
+#include "cpu/thread_context.hh"
+#include "mem/packet.hh"
+#include "arch/sparc/tlb.hh"
+
+
+namespace SparcISA
+{
+
+inline Tick
+handleIprRead(ThreadContext *xc, Packet *pkt)
+{
+#if FULL_SYSTEM
+ return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
+#else
+ panic("Shouldn't have a memory mapped register in SE\n");
+#endif
+}
+
+inline Tick
+handleIprWrite(ThreadContext *xc, Packet *pkt)
+{
+#if FULL_SYSTEM
+ return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
+#else
+ panic("Shouldn't have a memory mapped register in SE\n");
+#endif
+}
+
+
+} // namespace SparcISA
+
+#endif
regAccessOk:
handleMmuRegAccess:
DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
- req->setFlags(Request::MMAPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR);
req->setPaddr(req->getVaddr());
return NoFault;
};
+++ /dev/null
-/*
- * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_X86_MMAPEDIPR_HH__
-#define __ARCH_X86_MMAPEDIPR_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for memory mapped IPR accesses.
- */
-
-#include "arch/x86/regs/misc.hh"
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-#include "mem/packet.hh"
-
-namespace X86ISA
-{
- inline Tick
- handleIprRead(ThreadContext *xc, Packet *pkt)
- {
-#if !FULL_SYSTEM
- panic("Shouldn't have a memory mapped register in SE\n");
-#else
- Addr offset = pkt->getAddr() & mask(3);
- MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
- MiscReg data = htog(xc->readMiscReg(index));
- // Make sure we don't trot off the end of data.
- assert(offset + pkt->getSize() <= sizeof(MiscReg));
- pkt->setData(((uint8_t *)&data) + offset);
-#endif
- return xc->getCpuPtr()->ticks(1);
- }
-
- inline Tick
- handleIprWrite(ThreadContext *xc, Packet *pkt)
- {
-#if !FULL_SYSTEM
- panic("Shouldn't have a memory mapped register in SE\n");
-#else
- Addr offset = pkt->getAddr() & mask(3);
- MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
- MiscReg data;
- data = htog(xc->readMiscRegNoEffect(index));
- // Make sure we don't trot off the end of data.
- assert(offset + pkt->getSize() <= sizeof(MiscReg));
- pkt->writeData(((uint8_t *)&data) + offset);
- xc->setMiscReg(index, gtoh(data));
-#endif
- return xc->getCpuPtr()->ticks(1);
- }
-};
-
-#endif // __ARCH_X86_MMAPEDIPR_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_MMAPPEDIPR_HH__
+#define __ARCH_X86_MMAPPEDIPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "arch/x86/regs/misc.hh"
+#include "config/full_system.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "mem/packet.hh"
+
+namespace X86ISA
+{
+ inline Tick
+ handleIprRead(ThreadContext *xc, Packet *pkt)
+ {
+#if !FULL_SYSTEM
+ panic("Shouldn't have a memory mapped register in SE\n");
+#else
+ Addr offset = pkt->getAddr() & mask(3);
+ MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
+ MiscReg data = htog(xc->readMiscReg(index));
+ // Make sure we don't trot off the end of data.
+ assert(offset + pkt->getSize() <= sizeof(MiscReg));
+ pkt->setData(((uint8_t *)&data) + offset);
+#endif
+ return xc->getCpuPtr()->ticks(1);
+ }
+
+ inline Tick
+ handleIprWrite(ThreadContext *xc, Packet *pkt)
+ {
+#if !FULL_SYSTEM
+ panic("Shouldn't have a memory mapped register in SE\n");
+#else
+ Addr offset = pkt->getAddr() & mask(3);
+ MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
+ MiscReg data;
+ data = htog(xc->readMiscRegNoEffect(index));
+ // Make sure we don't trot off the end of data.
+ assert(offset + pkt->getSize() <= sizeof(MiscReg));
+ pkt->writeData(((uint8_t *)&data) + offset);
+ xc->setMiscReg(index, gtoh(data));
+#endif
+ return xc->getCpuPtr()->ticks(1);
+ }
+};
+
+#endif // __ARCH_X86_MMAPPEDIPR_HH__
panic("CPUID memory space not yet implemented!\n");
} else if (prefix == IntAddrPrefixMSR) {
vaddr = vaddr >> 3;
- req->setFlags(Request::MMAPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR);
Addr regNum = 0;
switch (vaddr & ~IntAddrPrefixMask) {
case 0x10:
// space.
assert(!(IOPort & ~0xFFFF));
if (IOPort == 0xCF8 && req->getSize() == 4) {
- req->setFlags(Request::MMAPED_IPR);
+ req->setFlags(Request::MMAPPED_IPR);
req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
} else if ((IOPort & ~mask(2)) == 0xCFC) {
req->setFlags(Request::UNCACHEABLE);
*/
#include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
#include "config/the_isa.hh"
Packet::Broadcast);
pkt.dataStatic(data);
- if (req->isMmapedIpr())
+ if (req->isMmappedIpr())
dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
else {
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
Packet pkt = Packet(req, cmd, Packet::Broadcast);
pkt.dataStatic(data);
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
dcache_latency +=
TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
*/
#include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
#include "config/the_isa.hh"
TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
{
RequestPtr req = pkt->req;
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
Tick delay;
delay = TheISA::handleIprRead(thread->getTC(), pkt);
new IprEvent(pkt, this, nextCycle(curTick() + delay));
{
pkt1 = pkt2 = NULL;
- assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
+ assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
if (req->getFlags().isSet(Request::NO_ACCESS)) {
buildPacket(pkt1, req, read);
TimingSimpleCPU::handleWritePacket()
{
RequestPtr req = dcache_pkt->req;
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
Tick delay;
delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
fatal("Insufficient memory to allocate compression state for %s\n",
filename);
- // unmap file that was mmaped in the constructor
+ // unmap file that was mmapped in the constructor
// This is done here to make sure that gzip and open don't muck with our
// nice large space of memory before we reallocate it
munmap((char*)pmemAddr, size());
/** The request is to an uncacheable address. */
static const FlagsType UNCACHEABLE = 0x00001000;
/** This request is to a memory mapped register. */
- static const FlagsType MMAPED_IPR = 0x00002000;
+ static const FlagsType MMAPPED_IPR = 0x00002000;
/** This request is a clear exclusive. */
static const FlagsType CLEAR_LL = 0x00004000;
bool isLocked() const { return _flags.isSet(LOCKED); }
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
- bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
+ bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); }
bool isClearLL() const { return _flags.isSet(CLEAR_LL); }
};
projects / gem5.git / commitdiff