Added extra notes after watching Luke's comparison vid

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index 99e800f9888340fcf3b97ee99178af132ec63cba..91da580f395dbbe404690da32b7bd5f9ce9831a9 100644 (file)
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -106,8 +106,8 @@ overlaying the Vector Registers onto the Floating Point registers, similar
 to x86 "MMX".
 
 Simple-V's "Vector" Registers are specifically designed to fit
-on top of the Scalar (GPR, FPR) register files, which are extended from
-32 to 128 entries.  This is a primary reason why Simple-V can be added
+on top of the Scalar (GPR, FPR) register files with \textbf{(byte-addressable access required?)}, which are extended from
+ the default of 32 (see PowerISA 3.2.1 General Purpose Registers and 4.2.1 Floating-Point Registers \textbf{[WHICH SPEC VERSION?]}), to 128 entries in the Libre-SOC implementation \textbf{[CAN WE REFER TO LIBRE-SOC?]}.  This is a primary reason why Simple-V can be added
 on top of an existing Scalar ISA, and \textit{in particular} why there
 is no need to add Vector Registers or Vector instructions.