ARM: Ignore reads and writes to DCIMVAC.

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 03fb86287991cbaf876333df8f29040cc5b565d7..1c00a3d6b68eff816386c5dedc06ce9bf5183394 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -107,6 +107,9 @@ let {{
           case MISCREG_DCCIMVAC:
             return new WarnUnimplemented(
                     isRead ? "mrc dccimvac" : "mcr dccimvac", machInst);
+          case MISCREG_DCIMVAC:
+            return new WarnUnimplemented(
+                    isRead ? "mrc dcimvac" : "mcr dcimvac", machInst);
           case MISCREG_DCCMVAC:
             return new WarnUnimplemented(
                     isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);