Set default value for dram_rst

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 538d3357ba1b8b45fc367ef30fb2af73ce2aba67..de800821ff287ae62cb270c69fb1e186b560eec8 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -40,7 +40,7 @@ module simsoctb;
   wire [1:0] dram_dm;
   wire dram_odt;
   wire [1:0] dram_tdqs_n;
-  reg dram_rst;
+  reg dram_rst = 0;
 
   ddr3 #(
     .check_strict_timing(0)