add SV VLIW idea

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 3d0838a78d9a6e5d6328d97906d5e30d5f778713..bbed3393126bf2bc9a24d5716d8fd2ee823a63b2 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -2233,6 +2233,7 @@ Reminder of the variable-length format from Section 1.5 of the RISC-V ISA:
 | base+4 | base+2           | base             | number of bits             |
 | ------ | ---------------- | ---------------- | -------------------------- |
 | ..xxxx | xxxxxxxxxxxxxxxx | xnnnxxxxx1111111 | (80+16\*nnn)-bit, nnn!=111 |
+| {ops}{Pred}{Reg}{VL}     || SV Prefix        |                            |
 
 Notes: