(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 44bba6d23cc69621cfe3fb511433230bc7ee7f3f..fe7cc9509e4432a3e20d95350401c797ab440349 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -120,7 +120,6 @@ widths as part of the actual operation, and the source and destination
 elwidth overrides, was particularly obtuse and hard to derive: some care
 and attention is advised, here, when reading the specification.
 
-
 **Non-vectorised**
 
 The concept of a Vectorised halt (`attn`) makes no sense. There are never
@@ -171,7 +170,19 @@ it is possible to apply one predicate to the source register (compressing
 the source element array) and another *completely separate* predicate
 to the destination register, *in one instruction* and not just on Load/Stores.
 
-
+No other Vector ISA in the world has this capability.  All true Vector
+ISAs have Predicate Masks: it is an absolutely essential characteristic.
+However none of them have abstracted dual predicates out to the extent
+where they are applicable *in general* to a wide range of arithmetic
+instructions, as well as Load/Store.
+
+It is however important to note that not all instructions can be Twin
+Predicated: some remain only Single Predicated, as is normally found
+in other Vector ISAs. Arithmetic operations with
+four registers (3-in, 1-out, VA-Form for example) are Single. The reason
+is that there just wasn't enough space in the 24-bits of the SVP64 Prefix.
+Consequently, when using a given instruction, it is necessary to look
+up in the ISA Tables whether it is 1P or 2P. caveat emptor!
 
 # CR weird instructions